CN111192869B - Substrate and display device - Google Patents
Substrate and display device Download PDFInfo
- Publication number
- CN111192869B CN111192869B CN202010017483.1A CN202010017483A CN111192869B CN 111192869 B CN111192869 B CN 111192869B CN 202010017483 A CN202010017483 A CN 202010017483A CN 111192869 B CN111192869 B CN 111192869B
- Authority
- CN
- China
- Prior art keywords
- conductive bump
- volume
- conductive
- substrate
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 117
- 239000002184 metal Substances 0.000 description 30
- 238000010586 diagram Methods 0.000 description 14
- 230000035882 stress Effects 0.000 description 11
- 238000000034 method Methods 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- 239000000969 carrier Substances 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000001125 extrusion Methods 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 206010011469 Crying Diseases 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000013013 elastic material Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000008646 thermal stress Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/16—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits
- H01L25/167—Assemblies consisting of a plurality of semiconductor or other solid state devices the devices being of types provided for in two or more different subclasses of H10B, H10D, H10F, H10H, H10K or H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
- H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
- H10H20/80—Constructional details
- H10H20/85—Packages
- H10H20/857—Interconnections, e.g. lead-frames, bond wires or solder balls
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
Description
技术领域technical field
本申请是关于一种基板和显示设备,特别是关于一种用于接收多个微型组件的基板和包括多个微型组件的显示设备。The present application relates to a substrate and a display device, and more particularly, to a substrate for receiving a plurality of micro-components and a display device including a plurality of micro-components.
背景技术Background technique
于制造微型发光二极管(micro LED)显示器时,需要先在一个基板(例如临时基板)上形成多个的微型发光二极管,再将微型发光二极管大范围地巨量转移到另一个基板(例如临时基板或永久基板)上的对应位置。然而,设置微型发光二极管的基板在加热与散热时,因为各种材料之间的热膨胀系数不同,有可能因为受到热应力而使基板发生翘曲(bowing or warpage)的情况。实务上,当基板发生翘曲时,会一并带动基板上的微型发光二极管产生位移,使得微型发光二极管不容易对准另一个基板上的组件,进而影响转移良率。When manufacturing a micro LED display, it is necessary to form a plurality of micro LEDs on one substrate (such as a temporary substrate), and then transfer the micro LEDs to another substrate (such as a temporary substrate) in large quantities. or the corresponding position on the permanent substrate). However, during heating and heat dissipation of the substrate on which the micro light-emitting diodes are arranged, the thermal expansion coefficient of various materials may be different, and the substrate may be bowed or warpaged due to thermal stress. In practice, when the substrate is warped, the micro LEDs on the substrate will be displaced together, making it difficult for the micro LEDs to align with the components on another substrate, thereby affecting the transfer yield.
发明内容SUMMARY OF THE INVENTION
有鉴于此,本申请的主要目的在于提供一种基板,能够更有效率地接收发生翘曲的载板上的微型组件。In view of this, the main purpose of the present application is to provide a substrate that can more efficiently receive the micro-components on the warped carrier.
本申请提供一种基板,用以接收载板中的多个微型组件。所述基板包含板体、第一导电凸块与第二导电凸块。板体具有第一表面,第一表面定义有至少一个转移区域,且转移区域定义有中心位置与边缘位置。第一导电凸块设置于中心位置,且具有第一体积。第二导电凸块设置于边缘位置,且具有第二体积。其中第一体积相异于第二体积。The present application provides a substrate for receiving a plurality of micro-components in a carrier board. The substrate includes a board body, a first conductive bump and a second conductive bump. The plate body has a first surface, the first surface defines at least one transfer area, and the transfer area defines a center position and an edge position. The first conductive bump is arranged at the center and has a first volume. The second conductive bump is disposed at the edge and has a second volume. wherein the first volume is different from the second volume.
于一些实施例中,第一导电凸块可以具有第一厚度,第二导电凸块可以具有第二厚度,当第一体积小于第二体积时,第一厚度小于第二厚度。在此,第一导电凸块于第一表面可以具有第一接触面积,第二导电凸块于第一表面可以具有第二接触面积,第一接触面积与第二接触面积大致相同。In some embodiments, the first conductive bumps may have a first thickness, the second conductive bumps may have a second thickness, and when the first volume is smaller than the second volume, the first thickness is smaller than the second thickness. Here, the first conductive bump may have a first contact area on the first surface, the second conductive bump may have a second contact area on the first surface, and the first contact area and the second contact area are substantially the same.
于一些实施例中,第一导电凸块于第一表面可以具有第一接触面积,第二导电凸块于第一表面可以具有第二接触面积,当第一体积小于第二体积时,第一接触面积小于第二接触面积。在此,第一导电凸块可以具有第一厚度,第二导电凸块可以具有第二厚度,第一厚度与第二厚度大致相同。此外,基板更可以包含另一个第一导电凸块,相邻两个的第一导电凸块间隔第一距离,相邻的第一导电凸块与第二导电凸块间隔第二距离,当第一体积小于第二体积时,第一距离大于第二距离。In some embodiments, the first conductive bump may have a first contact area on the first surface, and the second conductive bump may have a second contact area on the first surface. When the first volume is smaller than the second volume, the first The contact area is smaller than the second contact area. Here, the first conductive bumps may have a first thickness, the second conductive bumps may have a second thickness, and the first thickness and the second thickness are substantially the same. In addition, the substrate may further include another first conductive bump, two adjacent first conductive bumps are separated by a first distance, and adjacent first conductive bumps and second conductive bumps are separated by a second distance. When one volume is smaller than the second volume, the first distance is greater than the second distance.
于一些实施例中,第一导电凸块可以具有第一厚度,第二导电凸块可以具有第二厚度,当第一体积大于第二体积时,第一厚度大于第二厚度。在此,第一导电凸块于第一表面可以具有第一接触面积,第二导电凸块于第一表面可以具有第二接触面积,第一接触面积与第二接触面积大致相同。In some embodiments, the first conductive bumps may have a first thickness, the second conductive bumps may have a second thickness, and when the first volume is greater than the second volume, the first thickness is greater than the second thickness. Here, the first conductive bump may have a first contact area on the first surface, the second conductive bump may have a second contact area on the first surface, and the first contact area and the second contact area are substantially the same.
于一些实施例中,第一导电凸块于第一表面可以具有第一接触面积,第二导电凸块于第一表面可以具有第二接触面积,当第一体积大于第二体积时,第一接触面积大于第二接触面积。在此,第一导电凸块可以具有第一厚度,第二导电凸块可以具有第二厚度,第一厚度与第二厚度大致相同。此外,基板更可以包含另一个第一导电凸块,相邻两个的第一导电凸块间隔第一距离,相邻的第一导电凸块与第二导电凸块间隔第二距离,当第一体积大于第二体积时,第一距离小于第二距离。In some embodiments, the first conductive bump may have a first contact area on the first surface, and the second conductive bump may have a second contact area on the first surface. When the first volume is greater than the second volume, the first The contact area is larger than the second contact area. Here, the first conductive bumps may have a first thickness, the second conductive bumps may have a second thickness, and the first thickness and the second thickness are substantially the same. In addition, the substrate may further include another first conductive bump, two adjacent first conductive bumps are separated by a first distance, and adjacent first conductive bumps and second conductive bumps are separated by a second distance. When one volume is larger than the second volume, the first distance is smaller than the second distance.
本申请还提供一种基板,用以接收载板中的多个微型组件,所述基板包含板体、第一导电凸块以及第二导电凸块。板体具有第一表面,第一表面定义有至少一个转移区域,且转移区域定义有中心点。第一导电凸块设置于转移区域中,具有第一剖面形状。第二导电凸块设置于转移区域中,具有第二剖面形状,第一剖面形状相异于第二剖面形状,且第一导电凸块与中心点的距离小于第二导电凸块与中心点的距离。The present application also provides a substrate for receiving a plurality of micro-components in a carrier, the substrate comprising a board body, a first conductive bump and a second conductive bump. The plate body has a first surface, the first surface defines at least one transfer area, and the transfer area defines a center point. The first conductive bump is disposed in the transfer area and has a first cross-sectional shape. The second conductive bump is disposed in the transfer area and has a second cross-sectional shape, the first cross-sectional shape is different from the second cross-sectional shape, and the distance between the first conductive bump and the center point is smaller than the distance between the second conductive bump and the center point distance.
于一些实施例中,第一导电凸块具有第一体积且第二导电凸块具有第二体积,第一体积可以大致相同于第二体积。在此,第一导电凸块可以具有第一厚度,第二导电凸块可以具有第二厚度,第一厚度小于第二厚度,且第一导电凸块于第一表面可以具有第一接触面积,第二导电凸块于第一表面可以具有第二接触面积,第一接触面积大于第二接触面积。另外,第一导电凸块可以具有第一厚度,第二导电凸块可以具有第二厚度,第一厚度也可以大于第二厚度,且第一导电凸块于第一表面可以具有第一接触面积,第二导电凸块于第一表面可以具有第二接触面积,第一接触面积小于第二接触面积。另一方面,第一导电凸块可以具有第一杨氏模量,第二导电凸块可以具有第二杨氏模量,其中第一杨氏模量大于第二杨氏模量。In some embodiments, the first conductive bump has a first volume and the second conductive bump has a second volume, and the first volume may be substantially the same as the second volume. Here, the first conductive bumps may have a first thickness, the second conductive bumps may have a second thickness, the first thickness is smaller than the second thickness, and the first conductive bumps may have a first contact area on the first surface, The second conductive bump may have a second contact area on the first surface, and the first contact area is larger than the second contact area. In addition, the first conductive bumps may have a first thickness, the second conductive bumps may have a second thickness, the first thickness may also be greater than the second thickness, and the first conductive bumps may have a first contact area on the first surface , the second conductive bump may have a second contact area on the first surface, and the first contact area is smaller than the second contact area. On the other hand, the first conductive bumps may have a first Young's modulus, and the second conductive bumps may have a second Young's modulus, wherein the first Young's modulus is greater than the second Young's modulus.
本申请还提供了一种显示设备,显示设备中有基板,所述基板能够更有效率地接收发生翘曲的载板上的微型组件。The present application also provides a display device having a substrate that can more efficiently receive micro-components on a warped carrier.
本申请提供一种显示设备,显示设备包含了基板与多个微型组件。所述基板包含板体、第一导电凸块与第二导电凸块。板体具有第一表面,第一表面定义有至少一个转移区域,且转移区域定义有中心点。第一导电凸块设置于转移区域中,具有第一体积和第一剖面形状。第二导电凸块设置于转移区域中,具有第二体积和第二剖面形状,其中第一体积相异于第二体积或是第一剖面形状相异于第二剖面形状。其中第一导电凸块与中心点的距离小于第二导电凸块与中心点的距离。所述多个微型组件对应配置于第一导电凸块和第二导电凸块上。The present application provides a display device, which includes a substrate and a plurality of micro-components. The substrate includes a board body, a first conductive bump and a second conductive bump. The plate body has a first surface, the first surface defines at least one transfer area, and the transfer area defines a center point. The first conductive bump is disposed in the transfer region and has a first volume and a first cross-sectional shape. The second conductive bump is disposed in the transfer area and has a second volume and a second cross-sectional shape, wherein the first volume is different from the second volume or the first cross-sectional shape is different from the second cross-sectional shape. The distance between the first conductive bump and the center point is smaller than the distance between the second conductive bump and the center point. The plurality of micro components are correspondingly disposed on the first conductive bump and the second conductive bump.
于一些实施例中,所述多个微型组件分别对应的第一导电凸块和第二导电凸块的接合面积可以大致相同。此外,对应配置于基板上的第一导电凸块和微型组件具有第一高度,对应配置于基板上的第二导电凸块和微型组件具有第二高度,第一高度可以相异于第二高度。In some embodiments, the bonding areas of the first conductive bumps and the second conductive bumps corresponding to the plurality of micro-components may be approximately the same. In addition, the first conductive bumps and the micro-components disposed on the substrate have a first height, and the second conductive bumps and the micro-components corresponding to the substrate have a second height, and the first height may be different from the second height .
综上所述,本申请提供了一种基板和显示设备,基板上不同位置的导电凸块不相同,从而可以对应不同翘曲形状的载板。例如当载板发生上凹式(笑脸)翘曲时,基板上边缘位置的导电凸块可以有更大的体积或更大的剖面面积。反之,当载板发生下凹式(哭脸)翘曲时,基板上边缘位置的导电凸块则可以对应较小的体积或较小的剖面面积。因此,本申请的基板能够更有效率地接收发生翘曲的载板上的微型微型组件。To sum up, the present application provides a substrate and a display device. The conductive bumps at different positions on the substrate are different, so that they can correspond to carriers with different warped shapes. For example, when the carrier board is warped upwardly (smiley face), the conductive bumps at the upper edge of the substrate can have a larger volume or a larger cross-sectional area. On the contrary, when the carrier board is warped in a concave (crying face) type, the conductive bumps on the upper edge of the substrate can correspond to a smaller volume or a smaller cross-sectional area. Therefore, the substrate of the present application can more efficiently receive the micro-miniature components on the warped carrier.
有关本申请的其它功效及实施例的详细内容,配合附图说明如下。The details of other functions and embodiments of the present application are described below with reference to the accompanying drawings.
附图说明Description of drawings
为了更清楚地说明本申请实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本申请中记载的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其它的附图。In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the accompanying drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only These are some embodiments described in this application. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.
图1绘示依据本申请一实施例的对应上凹载板的基板的结构示意图;FIG. 1 is a schematic structural diagram of a substrate corresponding to an upper concave carrier according to an embodiment of the present application;
图2A是绘示依据本申请另一实施例的基板的俯视图;2A is a top view illustrating a substrate according to another embodiment of the present application;
图2B是绘示依据图2A沿AA线的剖面示意图;2B is a schematic cross-sectional view along line AA according to FIG. 2A;
图3是绘示依据本申请另一实施例的对应上凹载板的基板的结构示意图;3 is a schematic structural diagram illustrating a substrate corresponding to an upper concave carrier according to another embodiment of the present application;
图4是绘示依据本申请再一实施例的对应上凹载板的基板的结构示意图;4 is a schematic structural diagram illustrating a substrate corresponding to an upper concave carrier according to yet another embodiment of the present application;
图5是绘示依据本申请又一实施例的对应上凹载板的基板的结构示意图;5 is a schematic structural diagram illustrating a substrate corresponding to an upper concave carrier according to another embodiment of the present application;
图6是绘示依据本申请一实施例的对应下凹载板的基板的结构示意图;6 is a schematic structural diagram illustrating a substrate corresponding to a recessed carrier plate according to an embodiment of the present application;
图7是绘示依据本申请另一实施例的对应下凹载板的基板的结构示意图;7 is a schematic structural diagram illustrating a substrate corresponding to a recessed carrier plate according to another embodiment of the present application;
图8是绘示依据本申请再一实施例的对应下凹载板的基板的结构示意图。FIG. 8 is a schematic diagram illustrating a structure of a substrate corresponding to a recessed carrier according to yet another embodiment of the present application.
符号说明Symbol Description
1、2、3、4、5、6:基板1, 2, 3, 4, 5, 6: substrate
10、20、30、40、50、60:板体10, 20, 30, 40, 50, 60: plate body
10a、20a、30a、40a、50a、60a:第一表面10a, 20a, 30a, 40a, 50a, 60a: first surface
12、22、32、42、52、62:第一导电凸块12, 22, 32, 42, 52, 62: first conductive bumps
12a、22a、32a、42a、52a、62a:第一导电凸块的表面12a, 22a, 32a, 42a, 52a, 62a: the surface of the first conductive bump
14、24、34、44、54、64:第二导电凸块14, 24, 34, 44, 54, 64: second conductive bumps
14a、24a、34a、44a、54a、64a:第二导电凸块的表面14a, 24a, 34a, 44a, 54a, 64a: the surface of the second conductive bump
al、a2、a3:面积al, a2, a3: area
hl、h2、h3:厚度hl, h2, h3: thickness
dl、d2:距离dl, d2: distance
90:载板90: carrier board
92、92a、92b:微型组件92, 92a, 92b: Micro components
94、94a、94b:金属连接垫94, 94a, 94b: Metal connection pads
S1:转移区域S1: Transfer area
具体实施方式Detailed ways
以下为具体说明本申请的实施方式与达成功效,提供一实施例并搭配图式说明如下。The following is a specific description of the embodiments of the present application and the achieved effects, and an example is provided and described with the drawings as follows.
请一并参阅图1,图1是绘示依据本申请一实施例的对应上凹载板的基板的结构示意图。如图1所示,本实施例公开的基板1可以用来接收载板90上的多个微型组件92。在此,微型组件92可以例如是一种垂直式或覆晶式的微型发光二极管,某些实施例亦可应用到其他微型组件,包括微型集成电路、微型雷射二极管、微型感测组件。载板90可以例如是微型组件92的成长基板或者临时基板,而此时的本实施例的基板1可以是微型组件92的永久基板(显示面板)或者是另一个临时基板。由图1可知,载板90可以包含多个微型组件92,微型组件92设置于载板90面向基板1的一侧。于一个例子中,载板90可以是玻璃载板、蓝宝石载板(Sapphire)、硅载板(Si)或氧化铝载板(Al2O3)等无工作电路的临时载板,本实施例不加以限制。Please also refer to FIG. 1 . FIG. 1 is a schematic diagram illustrating a structure of a substrate corresponding to an upper concave carrier according to an embodiment of the present application. As shown in FIG. 1 , the
基板1包含板体10、多个第一导电凸块12与多个第二导电凸块14,其中板体10可以是一互补式金属氧化物半导体(Complementary Metal-Oxide-Semiconductor,CMOS)基板、一低温多晶硅基板(Low Temperature Poly-silicon,LTPS)、一薄膜晶体管(Thin FilmTransistor,TFT)基板或其他具有工作电路的基板,本实施例不加以限制。在此,板体10可以具有第一表面10a,第一表面10a朝向载板90,且第一导电凸块12与第二导电凸块14设置于第一表面10a上。实务上,第一导电凸块12与第二导电凸块14是分别用来对应连接金属连接垫(pad)94,且第一导电凸块12与第二导电凸块14可以设置于第一表面10a的一个特定范围内,所述特定范围例如是第一表面10a中的一个转移区域。实务上,当本实施例示范的基板1接收了多个微型组件92之后,可以成为一种显示面板或者成为部分的显示设备。换句话说,显示设备可以包含多个微型组件92,并且多个微型组件92会分别配置在对应的第一导电凸块12与第二导电凸块14上。The
举例来说,请一并参考图2A与图2B,图2A是绘示依据本申请另一实施例的基板的俯视图,图2B是绘示依据图2A沿AA线的剖面示意图。如图所示,第一表面10a上可以设有多个第一导电凸块12与多个第二导电凸块14,而这些第一导电凸块12与第二导电凸块14可以分成多个群组,每一个群组可以是一个转移区域。换句话说,第一表面10a中可以包含多个转移区域,例如图2A所标示的转移区域S1,从而在转移微型组件92时,第一表面10a可以分次于不同的转移区域接收微型组件92。当然,第一表面10a也有可能只对应到一个转移区域,即转移区域可以是部分或全部的第一表面10a,本实施例不加以限制。For example, please refer to FIG. 2A and FIG. 2B together. FIG. 2A is a top view of a substrate according to another embodiment of the present application, and FIG. 2B is a schematic cross-sectional view taken along line AA according to FIG. 2A . As shown in the figure, a plurality of first
于一个例子中,转移区域可以定义有中心位置与边缘位置,第一导电凸块12可以设置于中心位置,而第二导电凸块14可以设置于边缘位置。举例来说,假设转移区域是矩形,则边缘位置可以相对较靠近矩形周缘,而中心位置可以是相对较靠近矩形中心点的位置。换句话说,本实施例定义的第一导电凸块12较靠近转移区域的中心点,而第二导电凸块14较远离转移区域的中心点。本实施例在此不限制转移区域的形状或面积,转移区域可以是矩形、圆形、三角形或是其他适合的几何形状。实务上,由于载板90上的微型组件92是有规律地排列,为了要接收微型组件92,一般来说第一导电凸块12与第二导电凸块14也会对应微型组件92的排列方式。In one example, the transfer area may define a center position and an edge position, the first
然而传统上,在转移设置于载板90上的微型组件92时,会遇到一些实务上的问题而影响转移良率。其中一个问题是载板90有可能因为在加热与散热的过程中产生些微的翘曲,导致微型组件92于载板90上的位置改变或排列间隔产生差异。常见的载板90翘曲例如是上凹式的翘曲以及下凹式的翘曲,上凹式的翘曲意味着载板90的中心部分较接近板体10,而边缘部分较远离板体10。下凹式的翘曲则是相反,意味着载板90的中心部分较远离板体10,而边缘部分较接近板体10。传统上,由于载板90上的微型组件92可能因为载板90翘曲的问题,已经不在同一个水平面,例如上凹式的翘曲的载板90中,靠近载板90中心的微型组件92会较低。由于传统的基板的导电凸块都是相同的,当载板90压向传统的基板时,载板90上不同位置的微型组件92,其金属连接垫94与导电凸块的连接紧密度会产生差异。例如靠近载板90中心的微型组件92,其金属连接垫94与导电凸块的连接紧密度较高。相对地,靠近载板90边缘的微型组件92,其金属连接垫94与导电凸块的连接紧密度较低。如此一来,传统的基板可能产生每个微型组件92导电性不均匀的问题,甚至影响转移良率。However, conventionally, when transferring the micro-components 92 disposed on the
有别于传统的基板,本实施例提出了一种新的基板1。以图1来看,载板90是上凹式的翘曲,此时为了使基板1可以更有效地接收载板90上的多个微型组件92,本实施例的第一导电凸块12与第二导电凸块14会因为所在位置的不同而设计有不同的体积。于所属技术领域具有通常知识者应可以明白,体积关联于面积与高度,本实施例示范了一种固定面积调整高度的例子。于图1的例子中,假设第一导电凸块12预定与微型组件92接触的一第一表面12a的面积(第一接触面积)和第二导电凸块142预定与微型组件92接触的接触一第二表面14a的面积(第二接触面积)相同,例如都是面积a1。此时,第一导电凸块12与第二导电凸块14的厚度会有所不同,例如第一导电凸块12的厚度(第一厚度)是h1,则第二导电凸块14的厚度(第二厚度)是h2,而厚度h1会小于厚度h2。也就是说,当载板90是上凹式的翘曲时,图1示范了第一导电凸块12的体积(第一体积)会略小于第二导电凸块14的体积(第二体积)的例子。Different from the conventional substrate, this embodiment proposes a
承接上述,由于图1的载板90是上凹式的翘曲,使得接近载板90中心的微型组件92会比较靠近板体10,而接近载板90边缘的微型组件92与板体10之间的距离较大。当外部给载板90施加压力压向基板1时,载板90会越来越靠近板体10。此时,由于本实施例的第二导电凸块14相较于第一导电凸块12更凸出,因此可以使得不同位置的第一导电凸块12和第二导电凸块14可以大约同时接触到各别的金属连接垫94。于所属技术领域具有通常知识者可知,第一导电凸块12和第二导电凸块14的体积可以依据载板90的翘曲程度而定,例如使用者可以先行量测载板90的翘曲程度,再来判断第一导电凸块12与第二导电凸块14各自应该要有多少厚度。于一例子中,中间的导电凸块(第一导电凸块12)与边缘的导电凸块(如第二导电凸块14)厚度相异不超过50%,避免制程上因高低差太大降低良率。可见于本实施例基板1中,第一导电凸块12与第二导电凸块14可以与对应位置的金属连接垫94具有大致相同的连接紧密度,使得每个微型组件92都可以有均匀的导电性,从而提高转移良率。于未绘示出的实施例中,也可以包括另一导电凸块,其中该些导电凸块因应上凹式的翘曲而由内往外厚度、体积渐增。Following the above, since the
另一方面,当载板90压向传统的基板时,也有可能使传统的基板承受不平均的应力,而容易造成微型组件92或基板的损坏,并导致转移良率不佳。举前述使传统基板的例子来说,因为载板90边缘位置的微型组件92,其金属连接垫94较不容易连接到下方的导电凸块。当外部给载板90施加压力压向传统的基板时,为了确保载板90边缘位置的微型组件92也能被转移,有可能施加过大的压力而导致载板90中央位置的微型组件92过度推向基板。例如,载板90中央位置的微型组件92,其金属连接垫94可能已经过度挤压下方的导电凸块,造成微型组件92或基板的损坏。On the other hand, when the
图3的实施例提出了另一种新的基板2。请一并参阅图1与图3,图3是绘示依据本申请另一实施例的对应上凹载板的基板的结构示意图。与图1的实施例相同的是,图3示范的载板90同样是上凹式的翘曲,且基板2同样包含板体20、多个第一导电凸块22与多个第二导电凸块24。为了使基板2可以更有效地接收载板90上的多个微型组件92,本实施例的第一导电凸块22与第二导电凸块24同样会因为所在位置的不同而设计有不同的体积,且同样是第一导电凸块12的体积(第一体积)会略小于第二导电凸块14的体积(第二体积)的例子。与图1的实施例不同的是,图3假设第一导电凸块22的厚度(第一厚度)与第二导电凸块24的厚度(第二厚度)相同,例如都是厚度h1。此时,第一导电凸块22与预定与微型组件92接触的一第一表面22a的面积(第一接触面积)可以是a1,第二导电凸块24预定与微型组件92接触的一第二表面24a的面积(第二接触面积)可以是a2,而接触面积a1会小于接触面积a2。The embodiment of FIG. 3 proposes another
承接上述,由于图1的载板90是上凹式的翘曲,使得接近载板90中心的微型组件92会比较靠近板体10,而接近载板90边缘的微型组件92与板体10之间的距离较大。当外部给载板90施加压力压向基板1时,载板90会越来越靠近板体10。此时,于所属技术领域具有通常知识者应可以理解当各个金属连接垫94接触到第一导电凸块22和第二导电凸块24时,第一导电凸块22承受的应力应该会略大于第二导电凸块24承受的应力。然而,由于本实施例第一导电凸块22的体积更小,纵使外部给载板90施加压力大到足以确保载板90边缘位置的微型组件92能被转移,第一导电凸块22更容易用形变(例如溢流于金属连接垫94和板体10之间)来因应外部压力的挤压,可以避免应力造成微型组件92或基板2的损坏,从而提高转移良率。Following the above, since the
此外,举前述使传统基板的例子来说,不论上凹式的翘曲或下凹式的翘曲都会使载板90上的微型组件92偏离原本应该在的位置,使得传统的基板上的导电凸块有可能无法准确对准微型组件92,使后续转移与对位的步骤产生误差。有别于传统的基板,图3也示范了第一导电凸块22和第二导电凸块24可以用非等间隔的方式排列。于所属技术领域具有通常知识者应可以明白,由于图3绘示的载板90是上凹式的,载板90中央位置的微型组件92向两侧移位的程度较多,而载板90边缘位置的微型组件92移位程度较少。为了使第一导电凸块22和第二导电凸块24能够准确地对准移位后微型组件92上的金属连接垫94,第一导电凸块22和第二导电凸块24也应该各自设置在板体20(或转移区域)相应的位置上。举例来说,相邻的两个第一导电凸块22之间可以间隔有第一距离d1,而相邻的第一导电凸块22和第二导电凸块24之间可以间隔有第二距离d2。于本实施例中,第一距离d1会略大于第二距离d2。换句话说,越靠近板体20中心点的导电凸块(例如第一导电凸块22)排列会拉开一些,而远离板体20中心点的导电凸块(例如第二导电凸块24)排列会稍紧密一点。In addition, taking the above-mentioned conventional substrate as an example, whether the concave-up warpage or the concave-down warpage will cause the micro-components 92 on the
为了方便说明,图1绘示了每个微型组件92上有一个金属连接垫(pad)94,但本实施例并不限制金属连接垫94的数量,例如每个覆晶式的微型组件上也可以有两个以上的金属连接垫。请参阅图4,图4是绘示依据本申请再一实施例的对应上凹载板的基板的结构示意图。如图4所示,假设载板90上有多个覆晶式的微型组件92a与微型组件92b,微型组件92a在载板90中央位置且具有两个对应的金属连接垫94a,微型组件92b在载板90边缘位置且具有两个对应的金属连接垫94b。实务上,为了连接微型组件92a的两个金属连接垫94a,板体20相应的位置上也会设有两个第一导电凸块22。同样地,为了连接微型组件92b的两个金属连接垫94b,板体20相应的位置上也会设有两个第二导电凸块24。For the convenience of description, FIG. 1 shows that each micro-component 92 has a
如同前一实施例的理由,由于载板90是上凹式的,载板90中央位置的微型组件92a向两侧移位的程度较多,而载板90边缘位置的微型组件92b移位程度较少。因此,微型组件92a中的两个金属连接垫94a之间的距离会较分开一些,微型组件92b中的两个金属连接垫94b之间的距离会较紧密。为了对准两个金属连接垫94a,两个第一导电凸块22之间的距离d3会略大于两个第二导电凸块24之间的距离d4。换句话说,前一实施例示范的是,每一个导电凸块对应不同位置的微型组件,且越靠近板体20中心点的导电凸块的间隔距离越大,越远离板体20中心点的导电凸块之间的间隔距离越小。本实施例示范的是,如果微型组件有多个金属连接垫,则会有多个导电凸块对应同一个微型组件,此时越靠近板体20中心点的那一组导电凸块之间的间隔距离越大,而越远离板体20中心点的那一组导电凸块之间的间隔距离越小。For the same reason as in the previous embodiment, since the
另一方面,导电凸块也有可能具有相同的体积,但会因为所在位置的不同而有不同的形状。请一并参阅图1与图5,图5是绘示依据本申请再一实施例的对应上凹载板的基板的结构示意图。与图1的实施例相同的是,图5示范的载板90同样是上凹式的翘曲,且基板3同样包含板体30、多个第一导电凸块32与多个第二导电凸块34。此外,第一导电凸块32预定与微型组件92接触的一第一表面32a的面积(第一接触面积)同样可以是a1,且第一导电凸块32的厚度(第一厚度)同样可以是h1。与图1的实施例不同的是,第一导电凸块32和第二导电凸块34的体积可以是相同的,但具有不同的剖面形状。举例来说,图5的第二导电凸块34预定与微型组件92接触的一第二表面34a的面积(第二接触面积)是面积a3,且第二导电凸块34的厚度(第二厚度)是h3。此时,面积a3会小于面积a1,且厚度h3会大于厚度h1。本实施例在此不限制第二导电凸块34的形状,但由图5可知,第二导电凸块34会高于第一导电凸块32,且第二导电凸块34会窄于第一导电凸块32。On the other hand, it is also possible for the conductive bumps to have the same volume but have different shapes depending on where they are located. Please refer to FIG. 1 and FIG. 5 together. FIG. 5 is a schematic diagram illustrating a structure of a substrate corresponding to an upper concave carrier according to yet another embodiment of the present application. Similar to the embodiment of FIG. 1 , the
上述图1到图5的实施例中,第一导电凸块和第二导电凸块的杨氏模量(Young'smodulus)可以被设计为不相同的数值,而第一导电凸块和第二导电凸块的杨氏模量可以对应载板90不同的翘曲类型。例如载板90是上凹式的翘曲时,则可以设计越靠近板体中心点的导电凸块(例如第一导电凸块)的杨氏模量越小。反之,远离板体中心点的导电凸块(例如第二导电凸块)的杨氏模量可以设计成较大的数值。于所属技术领域具有通常知识者可以理解,杨氏模量是一种弹性材料的参数,关联于第一导电凸块和第二导电凸块承受正向应力时会产生的形变量,本实施例在此不予赘述。于一个例子中,由于第一导电凸块的杨氏模量比第二导电凸块的杨氏模量小,意味着第二导电凸块较不容易形变,当外部给载板施加压力时,不容易形变的第二导电凸块可以用来分散集中于板体中心点的应力,使得第一导电凸块和第二导电凸块承受的应力大致相同,从而提高转移良率。In the above embodiments of FIGS. 1 to 5 , the Young's modulus of the first conductive bump and the second conductive bump can be designed to be different values, and the first conductive bump and the second conductive bump The Young's modulus of the conductive bumps may correspond to different warpage types of the
前述图1到图5的例子是对应到载板90是上凹式的翘曲时的实施方式,但本申请不以此为限。请一并参阅图1与图6,图6是绘示依据本申请一实施例的对应下凹载板的基板的结构示意图。与图1的实施例相同的是,图6示范的基板4同样包含板体40、多个第一导电凸块42与多个第二导电凸块44,载板90同样包含多个微型组件92,且每个微型组件92都具有金属连接垫94。与图1的实施例不同的是,图6示范的载板90是下凹式的翘曲,也就是载板90的中心部分较远离板体40,而边缘部分较接近板体40。以图6来看,载板90是下凹式的翘曲,此时为了使基板4可以更有效地接收载板90上的多个微型组件92,本实施例的第一导电凸块42与第二导电凸块44与图1相反,即第一导电凸块42的体积(第一体积)会略大于第二导电凸块44的体积(第二体积)。The aforementioned examples in FIGS. 1 to 5 are embodiments corresponding to the case where the
本实施例同样示范了一种固定面积调整高度的例子。于图6的例子中,第一导电凸块42预定与微型组件92接触的一第一表面42a的面积(第一接触面积)和第二导电凸块44预定与微型组件92接触的接触一第二表面44a的面积(第二接触面积)相同,例如都是面积a1。此时,第一导电凸块42与第二导电凸块44的厚度会有所不同,例如第一导电凸块42的厚度(第一厚度)是h2,则第二导电凸块44的厚度(第二厚度)是h1,而厚度h2会大于厚度h1。由于本实施例的第一导电凸块42相较于第二导电凸块44更凸出,当外部给载板90施加压力压向基板4时,不同位置的第一导电凸块42和第二导电凸块44可以大约同时接触到各别的金属连接垫94。于一个例子中,第一导电凸块42与第二导电凸块44同样可以与对应位置的金属连接垫94具有大致相同的连接紧密度,使得每个微型组件92都可以有均匀的导电性,从而提高转移良率。于所属技术领域具有通常知识者可知,第一导电凸块42和第二导电凸块44的体积同样可以依据载板90的翘曲程度而定,本实施例在此不加以限制。于未绘示出的实施例中,也可以包括另一导电凸块,其中该些导电凸块因应上凹式的翘曲而由外往内厚度、体积渐增。This embodiment also exemplifies an example of adjusting the height with a fixed area. In the example of FIG. 6, the area of a
此外,请一并参阅图3与图7,图7是绘示依据本申请另一实施例的对应下凹载板的基板的结构示意图。与图3的实施例相同的是,图7示范的基板5同样包含板体50、多个第一导电凸块52与多个第二导电凸块54,载板90同样包含多个微型组件92,且每个微型组件92都具有金属连接垫94。与图3的实施例不同的是,图7示范的载板90是下凹式的翘曲,也就是载板90的中心部分较远离板体50,而边缘部分较接近板体50。以图7来看,为了使基板5可以更有效地接收载板90上的多个微型组件92,本实施例的第一导电凸块52与第二导电凸块54同样会因为所在位置的不同而设计有不同的体积,且第一导电凸块52的体积(第一体积)会略大于第二导电凸块54的体积(第二体积)。与图6的实施例不同的是,图7假设第一导电凸块52的厚度(第一厚度)与第二导电凸块54的厚度(第二厚度)相同,例如都是厚度h1。此时,第一导电凸块52预定与微型组件92接触的一第一表面52a的面积(第一接触面积)可以是a2,第二导电凸块54预定与微型组件92接触的接触一第二表面54a的面积(第二接触面积)可以是a1,而接触面积a2会大于接触面积a1。In addition, please refer to FIG. 3 and FIG. 7 together. FIG. 7 is a schematic structural diagram of a substrate corresponding to a recessed carrier according to another embodiment of the present application. Similar to the embodiment of FIG. 3 , the
承接上述,由于图7的载板90是下凹式的翘曲,使得接近载板90边缘的微型组件92会比较靠近板体50,而接近载板90中心的微型组件92与板体50之间的距离较大。当外部给载板90施加压力压向基板5时,载板90会越来越靠近板体50。此时,由于本实施例第二导电凸块54的体积更小,纵使外部给载板90施加压力大到足以确保载板90中心位置的微型组件92能被转移,第二导电凸块54更容易用形变(例如溢流于金属连接垫94和板体50之间)来因应外部压力的挤压,可以避免应力造成微型组件92或基板5的损坏,从而提高转移良率。Following the above, since the
此外,图7也示范了第一导电凸块52和第二导电凸块54可以用非等间隔的方式排列。于所属技术领域具有通常知识者应可以明白,由于图7绘示的载板90是下凹式的,载板90边缘位置的微型组件92移位的程度较多,而载板90中心位置的微型组件92移位程度较少。为了使第一导电凸块52和第二导电凸块54能够准确地对准移位后微型组件92上的金属连接垫94,第一导电凸块52和第二导电凸块54也应该各自设置在板体50(或转移区域)相应的位置上。举例来说,相邻的两个第一导电凸块52之间可以间隔有第一距离d1,而相邻的第一导电凸块52和第二导电凸块54之间可以间隔有第二距离d2。于本实施例中,第一距离d1会略小于第二距离d2。换句话说,越远离板体50中心点的导电凸块(例如第二导电凸块54)排列会拉开一些,而远离板体50中心点的导电凸块(例如第一导电凸块52)排列会稍紧密一点。In addition, FIG. 7 also exemplifies that the first
另一方面,导电凸块也有可能具有相同的体积,但会因为所在位置的不同而有不同的剖面形状。请一并参阅图5与图8,图8是绘示依据本申请再一实施例的对应下凹载板的基板的结构示意图。与图5的实施例相同的是,图8示范的载板90同样是下凹式的翘曲,且基板6同样包含板体60、多个第一导电凸块62与多个第二导电凸块64。此外,第二导电凸块64与第一表面60a的接触面积(第二接触面积)同样可以是a1,且第二导电凸块64的厚度(第二厚度)同样可以是h1。与图5的实施例不同的是,第一导电凸块62和第二导电凸块64的体积可以是相同的。举例来说,图8的第一导电凸块62与第一表面60a的接触面积(第一接触面积)是面积a3,且第一导电凸块62的厚度(第一厚度)是h3。此时,面积a3会小于面积a1,且厚度h3会大于厚度h1。本实施例在此不限制第一导电凸块62的形状,但由图8可知,第一导电凸块62会高于第二导电凸块64,且第一导电凸块62会窄于第二导电凸块64。On the other hand, it is also possible that the conductive bumps have the same volume but have different cross-sectional shapes depending on their location. Please refer to FIG. 5 and FIG. 8 together. FIG. 8 is a schematic diagram illustrating a structure of a substrate corresponding to a recessed carrier according to yet another embodiment of the present application. Similar to the embodiment of FIG. 5 , the
上述图6到图8的实施例中,第一导电凸块和第二导电凸块的杨氏模量(Young'smodulus)可以被设计为不相同的数值,而第一导电凸块和第二导电凸块的杨氏模量可以对应载板90不同的翘曲类型。例如载板90是下凹式的翘曲时,则可以设计越远离板体中心点的导电凸块(例如第二导电凸块)的杨氏模量越小。反之,靠近板体中心点的导电凸块(例如第一导电凸块)的杨氏模量可以设计成较大的数值。于一个例子中,由于第二导电凸块的杨氏模量比第一导电凸块的杨氏模量小,意味着第一导电凸块较不容易形变,当外部给载板施加压力时,不容易形变的第一导电凸块可以用来分散集中于板体边缘的应力,使得第一导电凸块和第二导电凸块承受的应力大致相同。In the above embodiments of FIGS. 6 to 8 , the Young's modulus of the first conductive bump and the second conductive bump can be designed to be different values, and the first conductive bump and the second conductive bump The Young's modulus of the conductive bumps may correspond to different warpage types of the
综上所述,本申请提供的基板可以用于显示设备中,且基板于不同位置的导电凸块可以有不同的设计,以对应不同翘曲形状的载板。当载板是上凹式的翘曲时,基板上边缘位置的导电凸块可以有更大的体积或更大的杨氏模量。反之,当载板是下凹式的翘曲时,基板上边缘位置的导电凸块则可以对应较小的体积或较小的杨氏模量。因此,基板上承受的应力可以较为均匀,且每个微型组件上的金属连接垫与对应导电凸块的接触面积可以大致相同,从而可以更有效率地接收发生翘曲的载板上的微型组件,并提高转移良率。To sum up, the substrate provided by the present application can be used in a display device, and the conductive bumps at different positions of the substrate can have different designs to correspond to carriers with different warped shapes. When the carrier is concavely warped, the conductive bumps at the upper edge of the substrate can have a larger volume or a larger Young's modulus. On the contrary, when the carrier board is concavely warped, the conductive bumps on the edge of the substrate can correspond to a smaller volume or a smaller Young's modulus. Therefore, the stress on the substrate can be relatively uniform, and the contact area of the metal connection pads on each micro-component and the corresponding conductive bumps can be approximately the same, so that the micro-components on the warped carrier can be received more efficiently , and improve the transfer yield.
以上所述的实施例及/或实施方式,仅是用以说明实现本申请技术的较佳实施例及/或实施方式,并非对本申请技术的实施方式作任何形式上的限制,任何本领域技术人员,在不脱离本申请内容所公开的技术手段的范围,当可作些许的更动或修改为其它等效的实施例,但仍应视为与本申请实质相同的技术或实施例。The above-mentioned embodiments and/or implementations are only used to illustrate the preferred embodiments and/or implementations of the technology of the present application, and are not intended to limit the implementation of the technology of the present application in any form. Personnel, without departing from the scope of the technical means disclosed in the content of this application, may make some changes or modifications to other equivalent embodiments, but they should still be regarded as substantially the same technology or embodiment as this application.
Claims (21)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010017483.1A CN111192869B (en) | 2020-01-08 | 2020-01-08 | Substrate and display device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202010017483.1A CN111192869B (en) | 2020-01-08 | 2020-01-08 | Substrate and display device |
Publications (2)
Publication Number | Publication Date |
---|---|
CN111192869A CN111192869A (en) | 2020-05-22 |
CN111192869B true CN111192869B (en) | 2022-08-02 |
Family
ID=70710721
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202010017483.1A Active CN111192869B (en) | 2020-01-08 | 2020-01-08 | Substrate and display device |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN111192869B (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113224218B (en) * | 2020-12-30 | 2023-01-20 | 湖北长江新型显示产业创新中心有限公司 | Display panel, manufacturing method and display device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1532931A (en) * | 2003-03-24 | 2004-09-29 | 精工爱普生株式会社 | Semiconductor devices and manufacturing methods, semiconductor packaging, electronic equipment and manufacturing methods, electronic instruments |
CN101339942A (en) * | 2007-07-03 | 2009-01-07 | 力成科技股份有限公司 | Semiconductor package joint structure for avoiding welding defect caused by substrate warping |
CN110100309A (en) * | 2016-12-23 | 2019-08-06 | 株式会社流明斯 | Miniature LED module and its manufacturing method |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001168239A (en) * | 2000-12-20 | 2001-06-22 | Hitachi Ltd | Ball grid array semiconductor device and its mounting method |
KR101096039B1 (en) * | 2009-11-09 | 2011-12-19 | 주식회사 하이닉스반도체 | Printed Circuit Boards and Semiconductor Packages Using the Same |
TWI590498B (en) * | 2013-06-03 | 2017-07-01 | 財團法人工業技術研究院 | Electronic device array and method of transfer-bonding electronic devices |
TWI589031B (en) * | 2014-10-20 | 2017-06-21 | Playnitride Inc | Light-emitting device transfer method |
-
2020
- 2020-01-08 CN CN202010017483.1A patent/CN111192869B/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1532931A (en) * | 2003-03-24 | 2004-09-29 | 精工爱普生株式会社 | Semiconductor devices and manufacturing methods, semiconductor packaging, electronic equipment and manufacturing methods, electronic instruments |
CN101339942A (en) * | 2007-07-03 | 2009-01-07 | 力成科技股份有限公司 | Semiconductor package joint structure for avoiding welding defect caused by substrate warping |
CN110100309A (en) * | 2016-12-23 | 2019-08-06 | 株式会社流明斯 | Miniature LED module and its manufacturing method |
Also Published As
Publication number | Publication date |
---|---|
CN111192869A (en) | 2020-05-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI720772B (en) | Substrate and display device | |
TWI550821B (en) | Method for maintaining alignment in a multi- chip module usinga compressible structure and multi-chip module and system with the same | |
US7459781B2 (en) | Fan out type wafer level package structure and method of the same | |
US11177154B2 (en) | Carrier structure and micro device structure | |
EP1443559B1 (en) | Integrated circuit assembly module | |
CN102110678B (en) | Semiconductor package and manufacturing method thereof | |
CN104037136A (en) | Reinforcement Structure And Method For Controlling Warpage Of Chip Mounted On Substrate | |
CN111613632A (en) | Display panel and method of making the same | |
CN110391165B (en) | Transfer carrier and die carrier | |
TW201322397A (en) | Lead frame and flip-chip type semiconductor packaging structure using the same | |
KR20130046117A (en) | Semiconductor package and method for manufacturing the same and semiconductor package module having the same | |
CN111192869B (en) | Substrate and display device | |
US11302547B2 (en) | Carrier structure and micro device structure | |
TW200810050A (en) | Package structure and heat sink module thereof | |
JP4348696B2 (en) | Conductive ball array mask and array device using the same | |
CN112531091A (en) | Light emitting device | |
TW202145604A (en) | Light-emitting device and manufacturing metho thereof | |
KR20000019563U (en) | A heat radiating apparatus for package mounting on printed circuit board | |
TWI777435B (en) | Micro led carrier board | |
TWI724378B (en) | Micro led carrier board | |
CN112768399A (en) | Transfer substrate and transfer device | |
CN114335058A (en) | Method for manufacturing micro display device | |
CN101552249B (en) | Semiconductor package structure | |
CN111628053A (en) | Miniature LED carrier plate | |
CN111276506B (en) | Carrier board structure and micro component structure |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |