CN111145809A - A radiation-resistant SRAM cell based on FinFET process - Google Patents

Abstract

The present invention is an SRAM radiation-resistant unit based on FinFET process, including a DICE radiation-resistant unit formed based on FinFET process, wherein the DICE radiation-resistant unit includes a read word line RWL and a write word line WL, wherein the read word line RWL and the write word line WL are connected to corresponding electrical levels to control a PMOS transmission tube switch to separate read and write operations. The radiation-resistant unit of the present invention can improve the radiation-resistant effect, improve the read stability, and eliminate the write failure problem caused by the process deviation of a small-size pull-up tube.

Description

A radiation-resistant SRAM cell based on FinFET process

technical field

The invention relates to the technical field of memory, in particular to an SRAM radiation-resistant unit based on a FinFET process.

Background technique

High-energy particles bombard semiconductor devices, interact with device materials during the incident process, and generate a large number of electron-hole pairs through direct ionization and indirect ionization. As charges are collected, the circuit experiences a single event flipping effect when the amount of these charges is greater than the "critical charge" required for the circuit to flip. The single event flip effect is a "soft" error caused by a change in the state of a latch or memory cell. It is mainly caused by excessive transient currents that cause logic level flips, and the wrong logic state is latched.

An existing general-purpose static memory cell (Static Random Access Memory Cell) has a 6T structure in FIG. 1, hereinafter referred to as a 6T SRAM Cell. It is assumed that the Q node stores "1" and the QB node stores "0". At this time, the transistors P1 and N0 are both in the off state, and the drains of these two transistors are sensitive nodes where the single event effect occurs. The bombardment of high-energy particles anywhere in the sensitive area can lead to single-particle flipping.

The built-in electric field in the sensitive area is always present in the SRAM memory cell in the hold or read and write states, so the transistor is collecting charges when electron-hole pairs are generated. Taking the particle bombarding the sensitive node Q point as an example, when the high-energy particle bombards the sensitive node Q point, the charge is collected to form an instantaneous current pulse at the drain of the N0 tube, and the N0 tube is turned on. The voltage at the Q point decreases with the increase in the number of collected charges. When the voltage at the Q point is low to a certain value, the transistor P0 is turned off and causes the logic state at Q to change to achieve a stable state. During this process, the voltages of the Q and QB storage nodes are mainly affected by two aspects: the gate of transistor N1 is continuously charged to keep N1 in the on state, and the QB point is discharged to restore the SRAM cell to the correct logic state. But on the other hand, due to the generation of pulse current in the drain of transistor N0, the potential of Q point decreases, causing the state of the two transistors P1 and N1 to change, P0 is gradually turned off and P1 is turned on, and the storage node QB is charged. The voltage of the QB point increases and is fed back to the gates of the left inverters P0 and N0, causing P0 to be turned off and N0 to be turned on, finally keeping the voltage of the storage node Q at a low potential, and the logic state stored in the SRAM cell is changed from "1". " is flipped to "0". It can be seen that the anti-single event effect of 6T SRAM Cell is invalid.

In the traditional planar structure transistor process, the ratio of the driving capability (Idsatp) of the PMOS to the driving capability (Idsatn) of the NMOS is about 2.5-2. In order to achieve the same drive capability, SRAM Cell area must be sacrificed. At the same time, there will be some error models in the process of reading and writing SRAM Cell. One of the read operation error mechanisms is that the read current of the memory cell is too small, resulting in the read data speed being too slow or even impossible to read at all. One of the error mechanisms of write operation is that the write margin is too small, resulting in the inability to write within a certain period of time. The specific performance is that the state before and after writing is the same. As the operating frequency becomes higher and higher in the future, the challenge for write operations will become greater and greater, because the clock cycle is very short, and it is relatively difficult to write data smoothly in a very short period of time.

There are many reinforcement methods for Single Event Upset (Single Event Upset), such as process reinforcement, system-level reinforcement, and circuit-level reinforcement, so that the circuit can obtain better SEU resistance. Process reinforcement, that is, the use of special processes to suppress single-particle inversion, such as SOI technology and epitaxy process. System-level reinforcement technology, which corrects and detects erroneous information through logical decision, such as EDAC error correction coding technology. Circuit-level reinforcement adopts the method of increasing redundancy, such as DICE technology and three-mode redundancy technology.

The basic idea of DICE technology is to add redundant storage states in the storage unit, and use the state recovery feedback circuit to restore the inverted data. It has strong anti-SEU capability and is widely used. However, the traditional DICE cell structure still has the following disadvantages: 1) The anti-radiation effect of the read and write state is easy to fail; 2) The read operation time is not fixed and becomes longer; 3) The ability of the write operation is poor; 4) The layout of the storage unit Design is very difficult to do, and area tradeoffs are very difficult.

SUMMARY OF THE INVENTION

The purpose of the present invention is to overcome the problems existing in the prior art, and to provide an SRAM radiation-resistant cell based on a FinFET process, which can not only resist single-event flipping, but also improve the data read stability and write data capability of the memory cell.

In order to realize the above-mentioned technical purpose and achieve the above-mentioned technical effect, the present invention is realized through the following technical solutions:

An SRAM radiation-resistant unit based on a FinFET process, comprising a DICE radiation-resistant unit based on a FinFET process, the DICE radiation-resistant unit comprising a read word line RWL and a write word line WL, the read word line RWL and the write word line WL Connect to the corresponding level to control the switch of the PMOS transmission tube, separate read and write operations.

Further, the DICE anti-irradiation unit further includes a first PMOS transistor P0 to an eighth PMOS transistor P7, and a first NMOS transistor N0 to a sixth NMOS transistor N5; wherein,

The gates of the fifth PMOS transistor P4 to the eighth PMOS transistor P7 are connected to the write word line WL;

The drain of the fifth PMOS transistor P4 is connected to the drains of the first PMOS transistor P0 and the first NMOS transistor N0, and the gates of the second PMOS transistor P1 and the fourth NMOS transistor N3, respectively, and the drain of the sixth PMOS transistor P5 is respectively The drains of the second PMOS transistor P1 and the second NMOS transistor N1 are connected, as well as the gates of the third PMOS transistor P2 and the first NMOS transistor N0, and the drains of the seventh PMOS transistor P6 are respectively connected to the third PMOS transistor P2 and the third PMOS transistor P2. The drain of the NMOS transistor N2, the gates of the fourth PMOS transistor P3 and the second NMOS transistor N1, and the drain of the eighth PMOS transistor P7 are connected to the drains of the fourth PMOS transistor P3 and the fourth NMOS transistor N3, and the drain of the fourth PMOS transistor P3 and the fourth NMOS transistor N3, respectively. gates of a PMOS transistor P0, a third NMOS transistor N2 and a fifth NMOS transistor N4;

The drain of the fifth NMOS transistor N4 is connected to the drain of the sixth NMOS transistor N6, and the gate of the sixth NMOS transistor N5 is connected to the read word line RWL.

Further, the sources of the first NMOS transistor N0 to the fourth NMOS transistor N3 and the sixth NMOS transistor N5 are grounded, and the source of the fifth NMOS transistor N4 is connected to the read bit line RBL.

Further, the sources of the first PMOS transistors P0 to the fourth PMOS transistors P3 are commonly connected to the power supply voltage terminal.

Further, the sources of the fifth PMOS transistor P4 and the seventh PMOS transistor P6 are commonly connected to the first bit line BL, and the sources of the sixth PMOS transistor P5 and the eighth PMOS transistor P7 are commonly connected to the second bit line BLB. .

The beneficial effects of the present invention are:

(1) The anti-radiation unit of the present invention can improve the anti-radiation effect;

(2) The anti-radiation unit of the present invention can improve reading stability;

(3) The anti-irradiation unit of the present invention can eliminate the problem of write failure caused by the process deviation of the small-sized pull-up tube.

Description of drawings

Figure 1 is a general-purpose 6T static storage unit;

2 is a circuit diagram of a DICE anti-radiation unit of the present invention;

FIG. 3 is a diagram illustrating the writing operation of the DICE anti-irradiation unit of the present invention.

Detailed ways

The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

An SRAM radiation-resistant unit based on a FinFET process, comprising a DICE radiation-resistant unit based on a FinFET process, the DICE radiation-resistant unit comprising a read word line RWL and a write word line WL, the read word line RWL and the write word line WL Connect to the corresponding level to control the switch of the PMOS transmission tube, separate read and write operations.

As shown in FIG. 2, the DICE anti-irradiation unit further includes a first PMOS transistor P0 to an eighth PMOS transistor P7, and a first NMOS transistor N0 to a sixth NMOS transistor N5; wherein,

The gates of the fifth PMOS transistor P4 to the eighth PMOS transistor P7 are connected to the write word line WL for performing a write operation;

The drain of the fifth PMOS transistor P4 is connected to the drains of the first PMOS transistor P0 and the first NMOS transistor N0, and the gates of the second PMOS transistor P1 and the fourth NMOS transistor N3, respectively, and the drain of the sixth PMOS transistor P5 is respectively The drains of the second PMOS transistor P1 and the second NMOS transistor N1 are connected, as well as the gates of the third PMOS transistor P2 and the first NMOS transistor N0, and the drains of the seventh PMOS transistor P6 are respectively connected to the third PMOS transistor P2 and the third PMOS transistor P2. The drain of the NMOS transistor N2, the gates of the fourth PMOS transistor P3 and the second NMOS transistor N1, and the drain of the eighth PMOS transistor P7 are connected to the drains of the fourth PMOS transistor P3 and the fourth NMOS transistor N3, and the drain of the fourth PMOS transistor P3 and the fourth NMOS transistor N3, respectively. gates of a PMOS transistor P0, a third NMOS transistor N2 and a fifth NMOS transistor N4;

The drain of the fifth NMOS transistor N4 is connected to the drain of the sixth NMOS transistor N6, and the gate of the sixth NMOS transistor N5 is connected to the read word line RWL for performing a read operation.

The sources of the first NMOS transistor N0 to the fourth NMOS transistor N3 and the sixth NMOS transistor N5 are grounded, and the source of the fifth NMOS transistor N4 is connected to the read bit line RBL.

The sources of the first PMOS transistors P0 to the fourth PMOS transistors P3 are commonly connected to the power supply voltage terminal.

The sources of the fifth PMOS transistor P4 and the seventh PMOS transistor P6 are commonly connected to the first bit line BL, and the sources of the sixth PMOS transistor P5 and the eighth PMOS transistor P7 are commonly connected to the second bit line BLB. The voltage values of the bit line BL and the second bit line BLB are opposite.

The working process and principle of the present invention

In the present invention, as shown in Figure 2, the nodes X0, X1, X2 and X3 are marked in the circuit on the figure, and it is assumed that the stored value of the nodes X0, X1, X2 and X3 is "0101", the following MOS tube names are shown in Figure 2 The device symbols in are marked with abbreviations.

During the read operation, the voltage of the read word line RWL is pulled to a high level, and the voltage of the write word line WL is pulled to a low level, so the read and write operations are separated, and the read bit line RBL is precharged to a high level; since the node X3 is stored as "1" , N4 and N5 form a pull-down path with the read bit line RBL, and pull down the read bit line RBL to a low level to complete the read operation; take the use of negative current pulse to bombard the storage point X1 as an example, at this time, the X1 node becomes "" 0", N0 is turned off, and P2 is turned on. At this time, the pull-up transistor P2 pulls up the storage node X2 to "1", so P3 and N0 are turned off, and the storage nodes X0 and X3 remain unchanged. They are fed back to P0 and N2, respectively. Pull X1 and X2 back to "1", "0", and after the irradiation reaction ends, restore the original value; Strong interference, the anti-radiation effect is obvious during the read operation, and the single-end read and write improves the read stability.

During the writing operation, due to the particularity of the MOS tube, the traditional DICE anti-irradiation unit can only perform the writing "0" operation, while the present invention combines the process characteristics of the FFiFET, as shown in Figure 3, using PMOS as the transmission tube to write "1" " operation; generally in the design, the data write driver (write driver) can be designed to be relatively large; when writing data, the first bit line BL is driven to "1", and the second bit line BLB is pulled down to "0" , due to the strong driving ability of the data driver, the transmission tube adopts PMOS design, which can quickly charge the storage nodes X0 and X2 to "1", when the nodes X0 and X2 are charged to "1", the pull-down transistors N1 and N3 are in a strong state. In the on state, the nodes X1 and X3 can be quickly discharged to "0", the time for the memory cell to establish positive feedback is relatively short, and it is not easy to fail to write new data. The performance is relatively small with process deviation, and the ability of the new DICE anti-irradiation unit to write data is relatively stable.

In addition, the new DICE anti-irradiation unit of the present invention uses PMOS for the transmission tube, and the size ratio of PMOS to NMOS is about 1:1, so PMOS and NMOS are more balanced than before, and the layout design of memory cells is easier to achieve The area is smaller.

In addition, it should be noted that unless otherwise specified or pointed out, the terms "first", "second", "third" and other descriptions in the specification are only used to distinguish various components, elements, steps, etc. in the specification, and It is not used to represent the logical relationship or sequence relationship between various components, elements, steps, etc.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (5)

1. a SRAM anti-radiation unit based on FinFET technology, comprising the DICE anti-radiation unit formed based on FinFET technology, it is characterized in that, described DICE anti-radiation unit comprises read word line RWL and write word line WL, and described read word The line RWL and the write word line WL are connected to the corresponding level to control the switch of the PMOS transfer transistor, and separate read and write operations. 2. The SRAM anti-irradiation unit based on the FinFET process according to claim 1, wherein the DICE anti-irradiation unit further comprises a first PMOS transistor P0 to an eighth PMOS transistor P7, and a first NMOS transistor N0 to The sixth NMOS transistor N5; among them, The gates of the fifth PMOS transistor P4 to the eighth PMOS transistor P7 are connected to the write word line WL; The drain of the fifth PMOS transistor P4 is connected to the drains of the first PMOS transistor P0 and the first NMOS transistor N0, and the gates of the second PMOS transistor P1 and the fourth NMOS transistor N3, respectively, and the drain of the sixth PMOS transistor P5 is respectively The drains of the second PMOS transistor P1 and the second NMOS transistor N1 are connected, as well as the gates of the third PMOS transistor P2 and the first NMOS transistor N0, and the drains of the seventh PMOS transistor P6 are respectively connected to the third PMOS transistor P2 and the third PMOS transistor P2. The drain of the NMOS transistor N2, the gates of the fourth PMOS transistor P3 and the second NMOS transistor N1, and the drain of the eighth PMOS transistor P7 are connected to the drains of the fourth PMOS transistor P3 and the fourth NMOS transistor N3, and the drain of the fourth PMOS transistor P3 and the fourth NMOS transistor N3, respectively. gates of a PMOS transistor P0, a third NMOS transistor N2 and a fifth NMOS transistor N4; The drain of the fifth NMOS transistor N4 is connected to the drain of the sixth NMOS transistor N6, and the gate of the sixth NMOS transistor N5 is connected to the read word line RWL. 3 . The SRAM anti-irradiation unit based on the FinFET process according to claim 2 , wherein the sources of the first NMOS transistor N0 to the fourth NMOS transistor N3 and the sixth NMOS transistor N5 are grounded, and the fifth NMOS transistor N5 . The source of the tube N4 is connected to the read bit line RBL. 4 . The SRAM anti-irradiation unit based on the FinFET process according to claim 2 , wherein the sources of the first PMOS transistors P0 to the fourth PMOS transistors P3 are commonly connected to a power supply voltage terminal. 5 . 5. The SRAM anti-irradiation unit based on the FinFET process according to claim 2 or 4, wherein the sources of the fifth PMOS transistor P4 and the seventh PMOS transistor P6 are commonly connected to the first bit line BL, and the The source electrodes of the sixth PMOS transistor P5 and the eighth PMOS transistor P7 are commonly connected to the second bit line BLB.

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