CN111129123B - Combined etch stop layer for contact field plate etching, integrated chip and forming method thereof - Google Patents

Abstract

The present invention relates to integrated chips. In some embodiments, the integrated chip has a gate structure disposed over the substrate between the source region and the drain region and a dielectric layer extending laterally from over the gate structure to between the gate structure and the drain region. A combined etch stop layer having a plurality of different dielectric materials is stacked over the dielectric layer. The contact etch stop layer directly contacts the upper surface and sidewalls of the combined etch stop layer. The field plate is laterally surrounded by a first inter-layer dielectric (ILD) layer, and extends from the top of the first ILD layer, through the contact etch stop layer, and into the combined etch stop layer. The embodiment of the invention also provides a method for forming the combined etching stop layer and the integrated chip by etching the contact field plate.

Description

Combined etch stop layer for contact field plate etching, integrated chip and method of forming same

Technical field

Embodiments of the present invention generally relate to the field of semiconductor technology, and more specifically, to a combined etch stop layer for contact field plate etching, an integrated chip, and a method of forming the same.

Background technique

Modern integrated chips include millions or billions of semiconductor devices formed on a semiconductor substrate (eg, silicon). Integrated chips (ICs) can use many different types of transistor devices depending on the IC's application. In recent years, the growing market for cellular and RF (radio frequency) devices has led to a significant increase in the use of high-voltage transistor devices. For example, high voltage transistor devices are commonly used in power amplifiers in RF transmit/receive chains due to their ability to handle high breakdown voltages (eg, greater than about 50 V) and high frequencies.

Contents of the invention

According to an aspect of the present invention, an integrated chip is provided, including: a gate structure disposed between a source region and a drain region above a substrate; and a dielectric layer laterally extending from above the gate structure to between the gate structure and the drain region; a combined etch stop layer including a plurality of different dielectric materials stacked over the dielectric layer; a contact etch stop layer with the combined etch stop layer and a field plate laterally surrounded by a first interlayer dielectric (ILD) layer and extending vertically from the top of the first interlayer dielectric layer through the contact etch stop layer, and into the combined etch stop layer.

According to another aspect of the present invention, an integrated chip is provided, including: a gate structure disposed above a substrate; a resist protective oxide extending laterally across the gate structure from above the gate structure an outermost wall; a combined etch stop layer including a first dielectric material located above the resist protective oxide and a second dielectric material contacting an upper surface of the first dielectric material; a plurality of conductive contacts, Surrounded laterally by a first interlayer dielectric (ILD) layer over the substrate; and a field plate extending from the top of the first interlayer dielectric layer to the combined etch stop layer and including the A plurality of conductive contacts are of the same material, wherein the combined etch stop layer laterally contacts sidewalls of the field plate and vertically separates the field plate from the resist protective oxide.

According to yet another aspect of the present invention, a method for forming an integrated chip is provided, including: forming a gate structure above the substrate between a source region and a drain region within the substrate; A dielectric layer is formed over the structure and between the gate structure and the drain region; a combined etch stop layer is formed over the dielectric layer, wherein the combined etch stop layer includes a plurality of stacked dielectric materials ; forming a first interlayer dielectric (ILD) layer over the combined etch stop layer; selectively etching the first interlayer dielectric layer to simultaneously define contact openings and extensions extending to the substrate a field plate opening to the combined etch stop layer; and filling the contact opening and the field plate opening with one or more conductive materials.

Description of drawings

Aspects of the invention are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or decreased for clarity of discussion.

Figure 1 shows a cross-sectional view of some embodiments of the disclosed high voltage transistor device with a field plate.

2-4 illustrate cross-sectional views of some additional embodiments of the disclosed high voltage laterally diffused MOSFET (LDMOS) devices with field plates.

5-6 illustrate cross-sectional views of some embodiments of field plate biasing configurations of high voltage LDMOS devices implemented through metal interconnect routing.

7A-7C illustrate cross-sectional views of some embodiments of high voltage LDMOS devices in different switch isolation configurations.

Figure 8 shows a cross-sectional view of a high-voltage transistor device with a field plate source-down (ie, the source is underneath).

9A-9B illustrate some embodiments of the disclosed high voltage LDMOS with field plates on metal line layers.

Figure 10 shows some embodiments of high voltage LDMOS devices with self-aligned drift regions.

Figure 11 illustrates a flowchart of some embodiments of a method of forming a high voltage transistor device with a field plate.

12-19 illustrate cross-sectional views of some embodiments of methods of forming high voltage transistor devices with field plates.

20-24 illustrate some embodiments of the disclosed high voltage transistor device having a combined etch stop layer defining a field plate.

25-32 illustrate cross-sectional views of some embodiments of a method of forming a high voltage transistor device having a combined etch stop layer defining a field plate.

33 illustrates a flowchart of some embodiments of a method of forming a high voltage transistor device with a combined etch stop layer defining a field plate.

Detailed ways

The following disclosure provides many different embodiments or examples for implementing different features of the presented subject matter. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are examples only and are not limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which the first component and the second component may be formed in direct contact. Additional components enable embodiments in which the first component and the second component may not be in direct contact. Additionally, the present invention may repeat reference numbers and/or letters in various examples. This repetition is for purposes of simplicity and clarity and does not per se indicate a relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms may be used herein, such as “below,” “beneath,” “lower,” “above,” “upper,” etc., for convenience of description to describe what is illustrated in the figures. The relationship of one element or component to another element or components. The spatially relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation illustrated in the figures. The device is used or operated. may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

High voltage transistor devices are typically constructed with field plates. Field plates are conductive elements placed over the channel region to enhance the performance of high voltage transistor devices by controlling the electric field generated by the gate electrode (eg, reducing the peak electric field). By controlling the electric field generated by the gate electrode, high voltage transistor devices can achieve higher breakdown voltages. For example, LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistor devices typically include a field plate extending from a channel region to an adjacent drift region disposed between the channel region and the drain region.

Field plates can be formed in many different ways. For example, the field plate may be formed by a conductive gate material (eg, polysilicon) extending from the gate electrode toward the drift region. However, in this configuration, the field plate is aligned with the gate bias (also known as offset), which increases the gate-to-drain capacitance (Cgd) and worsens the switching losses of the device. Alternatively, the conductive gate material can be patterned to form individual field plates. This configuration reduces the gate-to-drain capacitance (Cgd), but field plate placement is often limited by design rules. In yet another alternative embodiment, non-gate materials may be used for field plate formation. However, this solution uses additional processing steps, which increases the manufacturing cost of the resulting integrated chip.

Accordingly, the present invention relates to a high voltage transistor device having a field plate made of a non-gate material, wherein the field plate is formed simultaneously with the formation of a back-end-of-line (BEOL) metal layer to enable a low-cost manufacturing method. In some embodiments, a high voltage transistor device has a gate electrode disposed on the substrate between a source region and a drain region within the substrate. The dielectric layer extends laterally from above the gate electrode to a drift region disposed between the gate electrode and the drain region. The field plate is located within a first interlayer dielectric (ILD) layer covering the substrate. The field plate extends laterally from above the gate electrode to above the drift region, and vertically from the dielectric layer to the top surface of the first ILD layer. A plurality of metal contacts of the same material as the field plate extend vertically from the bottom surface of the first ILD layer to the top surface of the first ILD layer.

FIG. 1 illustrates a cross-sectional view of some embodiments of the disclosed high voltage transistor device 100 having a field plate 122 .

High voltage transistor device 100 includes source region 104 and drain region 106 disposed in a semiconductor substrate. The semiconductor substrate 102 has a first doping type, and the source region 104 and the drain region 106 have a second doping type, with a higher doping concentration than the semiconductor substrate 102 . In some embodiments, the first doping type is n-type doping and the second doping is p-type doping.

Gate structure 116 is disposed over semiconductor substrate 102 at a location laterally disposed between source region 104 and drain region 106 . Gate structure 116 includes gate electrode 108 separated from semiconductor substrate 102 by gate dielectric layer 110 . Upon receiving a bias voltage, gate electrode 108 is configured to generate an electric field to control the movement of charge carriers within channel region 112 laterally disposed between source region 104 and drain region 106 . For example, during operation, a gate-source voltage (V _GS ) may be selectively applied to gate electrode 108 relative to source region 104 to form a conductive channel in channel region 112 . When V _GS is applied to form a conductive channel, a drain-source voltage (V _DS ) is applied to move charge carriers between source region 104 and drain region 106 (eg, as indicated by arrow 105 ).

Channel region 112 extends laterally from source region 104 to adjacent drift region 114 (eg, drain extension region). Drift region 114 includes a second doping type with a relatively low doping concentration, thereby providing higher resistance at high operating voltages. Gate structure 116 is disposed over channel region 112 . In some embodiments, gate structure 116 may extend from over channel region 112 to a location over a portion of drift region 114 .

A first interlayer dielectric (ILD) layer 118 is disposed over the semiconductor substrate 102 . One or more conductive metal structures are disposed within ILD layer 118 . In some embodiments, the one or more conductive metal structures include a plurality of contacts 120 configured to provide source region 104, drain region 106, or gate electrode 108 with first back-end-of-line (BEOL) metal lines Vertical connections between layers 128 , where a first back-end-of-line (BEOL) metal line layer 128 is disposed within the second ILD layer 126 above the first ILD layer 118 .

The one or more conductive metal structures may further include a field plate 122 disposed within the first ILD layer 118 at a location over the gate electrode 108 and portions of the drift region 114 . Field plate 122 includes the same conductive material as plurality of contacts 120 . Field plate 122 may be disposed over dielectric layer 124 , where dielectric layer 124 is configured to separate field plate 122 from drift region 114 and gate electrode 108 . In some embodiments, dielectric layer 124 extends laterally across field plate 122 in one or more directions.

During operation, field plate 122 is configured to act on the electric field generated by gate electrode 108 . Field plate 122 may be configured to change the distribution of the electric field generated by gate electrode 108 in drift region 114 , thereby enhancing the internal electric field of drift region 114 and increasing the drift doping concentration of drift region 114 , thereby enhancing the performance of high voltage transistor device 100 . Breakthrough voltage capability.

2 illustrates a cross-sectional view of some additional embodiments of the disclosed high-voltage transistor device, including a high-voltage laterally diffused MOSFET (LDMOS) device 200 having a field plate 214.

LDMOS device 200 includes source region 104 and drain region 106 disposed in semiconductor substrate 102 . The semiconductor substrate 102 has a first doping type, and the source region 104 and the drain region 106 include highly doped regions of a second doping type different from the first doping type. In some embodiments, the first doping type is p-type and the second doping type is n-type. In some embodiments, the doping concentration of source region 104 and drain region 106 may range between approximately 10 ¹⁹ cm ⁻³ and approximately 10 ²⁰ cm ⁻³ .

Contact region 208 (eg, p-type tap or n-type tap) having a first doping type (eg, P+ doping) laterally adjoins source region 104 . Contact region 208 provides an ohmic connection to semiconductor substrate 102 . In some embodiments, the doping concentration of contact region 208 may range between approximately 10 ¹⁸ cm ⁻³ and approximately 10 ²⁰ cm ⁻³ . Contact area 208 and source area 104 are disposed within body area 202 . The body region 202 has a first doping type and a doping concentration higher than that of the semiconductor substrate 102 . For example, the doping concentration of the semiconductor substrate 102 may range between about 10 ¹⁴ cm ⁻³ and about 10 ¹⁶ cm ⁻³ , while the doping concentration of the body region 202 may range between about 10 ¹⁶ cm ⁻³ and about 10 ¹⁸ Within the range between cm ^-3 .

Drain region 106 is disposed within drift region 204 , which is disposed within semiconductor substrate 102 laterally adjacent body region 202 . The drift region 204 includes a second doping type with a relatively lower doping concentration, wherein the drift region 204 provides higher resistance when the LDMOS device 200 is operated at high voltage. In some embodiments, the doping concentration of drift region 204 may range between approximately 10 ¹⁵ cm ⁻³ and approximately 10 ¹⁷ cm ⁻³ .

Gate structure 210 is disposed over semiconductor substrate 102 at a location laterally disposed between source region 104 and drain region 106 . In some embodiments, gate structure 210 may extend laterally from over body region 202 to a position over a portion of drift region 204 . Gate structure 210 includes gate electrode 108 separated from semiconductor substrate 102 by gate dielectric layer 110 . In some embodiments, gate dielectric layer 110 may include silicon dioxide (SiO ₂ ) or a high-k gate dielectric material, and gate electrode 108 may include polysilicon or a metal gate material (eg, aluminum). In some embodiments, gate structure 210 may also include sidewall spacers 212 disposed on opposite sides of gate electrode 108 . In some embodiments, sidewall spacers 212 may include nitride-based sidewall spacers (eg, including SiN) or oxide-based sidewall spacers (eg, SiO ₂ , SiOC, etc.).

One or more dielectric layers 124 are disposed over the gate electrode 108 and the drift region 204 . In some embodiments, one or more dielectric layers 124 extend continuously from over a portion of the gate electrode 108 to over a portion of the drift region 204 . In some embodiments, one or more dielectric layers 124 may be conformally disposed over drift region 204 , gate electrode 108 , and sidewall spacers 212 .

Field plate 214 is disposed over one or more dielectric layers 124 and is laterally surrounded by first ILD layer 118 . Field plate 214 extends from over gate electrode 108 to over drift region 204 . The size of field plate 214 may vary depending on the size and characteristics of LDMOS device 200. In some embodiments, field plate 214 may have dimensions between about 50 nanometers and about 1 micron. In other embodiments, field plate 214 may be larger or smaller. In some embodiments, the first ILD layer 118 may include a dielectric material with a relatively low dielectric constant (eg, less than or equal to about 3.9) that provides a connection between the plurality of contacts 120 and/or the field plate 122 Electrical isolation. In some embodiments, first ILD layer 118 may include an ultra-low-k dielectric material or a low-k dielectric material (eg, SiCO).

Field plate 214 extends vertically from dielectric layer 124 to the top surface of first ILD layer 118 . In some embodiments, field plate 214 may extend vertically to a height greater than or equal to the height of contacts 120 and the top surface of first ILD layer 118 . Field plate 122 has a non-planar surface adjacent one or more dielectric layers 124 . The non-flat surface causes the field plate 122 to have a first thickness t ₁ in the area above the gate electrode 108 and a second thickness t ₂ that is greater than the first thickness t ₁ in the area covering the drift region 204 .

The plurality of contacts 120 is also surrounded by the first ILD layer 118 . The plurality of contacts 120 may include a first contact 120a coupled to the contact region 208, a second contact 120b coupled to the drain region 106, and a third contact 120c coupled to the gate electrode 108. In some embodiments, first contact 120a may include a butt contact (not shown) in contact with contact region 208 and source region 104 . In some embodiments, multiple contacts 120 and field plate 122 may include the same metallic material. For example, the plurality of contacts 120 and the field plate 122 may include one of tungsten (W), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), aluminum copper (AlCu), copper (Cu). one or more and/or other similar conductive materials.

3 shows a cross-sectional view of some additional embodiments of the disclosed high voltage LDMOS device 300 having a field plate 214.

LDMOS device 300 includes an isolation region 302 disposed within drift region 204 at a location laterally disposed between gate structure 214 and drain region 106 . Isolation region 302 improves the isolation between gate structure 210 and drain region 106 to prevent dielectric breakdown between gate structure 210 and drift region 204 when LDMOS device 300 is operated at large operating voltages. For example, isolation region 302 may be introduced into drift region 204 of an LDMOS device designed to operate at a first breakdown voltage to increase the breakdown voltage of LDMOS device 300 without significantly changing the LDMOS device's Manufacturing process. In some embodiments, isolation region 302 may include a shallow trench isolation (STI). In other embodiments, isolation region 302 may include field oxide.

4 shows a cross-sectional view of some additional embodiments of the disclosed high voltage LDMOS device 400 having a field plate 408.

LDMOS device 400 includes a plurality of dielectric layers 402 - 404 disposed between field plate 408 and gate structure 210 and/or drift region 204 . A plurality of dielectric layers 402 - 404 are configured to electrically isolate field plate 408 from gate structure 210 and/or drift region 204 . In embodiments, the plurality of dielectric layers 402-404 may include two or more different dielectric materials. In some embodiments, the plurality of dielectric layers 402 - 404 may include one or more dielectric layers used during typical CMOS manufacturing processes to limit the use of field plate 408 with gate structure 210 and/or drift. Additional manufacturing step for electrical isolation of region 204.

For example, the plurality of dielectric layers 402 - 404 may include a suicide barrier layer 402 . In some embodiments, suicide barrier layer 402 may include a resist protective oxide (RPO) layer configured to prevent suicide formation. A suicide barrier layer 402 may be disposed over gate electrode 108 and portions of drift region 204 . In some embodiments, suicide barrier layer 402 may extend continuously from over gate electrode 108 to over drift region 204 .

In some embodiments, the plurality of dielectric layers 402 - 404 may also include a field plate etch stop layer (ESL) 404 . Field plate ESL 404 may be disposed over suicide barrier layer 402 and configured to control etching of the openings of field plate 408 . Field plate ESL 404 may account for differences in etch depth and/or differences in etch rates between contacts 120 and field plate 408 (eg, due to etch loading effects). In some embodiments, field plate ESL 404 may include, for example, a silicon nitride (SiN) layer.

In some alternative embodiments (not shown), the plurality of dielectric layers 402-404 may additionally or alternatively include a gate dielectric layer. In such embodiments, a gate dielectric layer may be disposed laterally adjacent gate structure 210 at a location covering drift region 204 . In some embodiments, the dielectric layer of oxide may include silicon dioxide (eg, SiO ₂ ) or a high-k gate dielectric material. In other embodiments, the plurality of dielectric layers 402 - 404 may additionally or alternatively include an ILD layer (eg, first ILD layer 118 ).

Contact etch stop layer (CESL) 406 is disposed over semiconductor substrate 102 and field plate ESL 404 . In some embodiments, CESL 406 extends over semiconductor substrate 102 at a location between plurality of contacts 120 and field plate 408 such that CESL 406 abuts the sidewalls of plurality of contacts 120 and field plate 408 . CESL 406 covers gate structure 210. In some embodiments, CESL 406 may also cover multiple dielectric layers 402-404. In other embodiments, one or more of the plurality of dielectric layers 402-404 (eg, field plate ESL 404) may cover CESL 406. In some embodiments, CESL 406 may include a nitride layer. For example, CESL 406 may include silicon nitride (SiN).

Field plate 408 is disposed within first ILD layer 118 adjacent CESL 406 and adjacent one or more of the plurality of dielectric layers 402-404. In some embodiments, the field plate 408 extends through the CESL 406 to adjoin one or more of the plurality of dielectric layers 402 - 404 . In such embodiments, one or more of the plurality of dielectric layers 402 - 404 separate the field plate 408 from the gate structure 210 and the drift region 204 .

In some embodiments, field plate 408 may include first metallic material 410 and second metallic material 412 . The first metal material 410 may include a glue layer disposed along the outer edge of the field plate 408, and the second metal material 412 is embedded within the first metal material 410 in an interior area of the field plate 408 (i.e., the second metal material 412 passes through the A metallic material 410 is separated from the CESL 406). In some embodiments, liner layer 414 may be disposed between first ILD layer 118 and first metallic material 410 .

In some embodiments, the first metallic material 410 disposed along the outer edge of the field plate 408 has a top surface disposed along a substantially planar surface 420 (ie, a planar surface formed by a planarization process). Flat surface 420 may be aligned with the top surface of plurality of contacts 120 . In some embodiments, the first metal material 410 includes the same material as the plurality of contacts 120 and the second metal material 412 includes the same material as the first metal line layer 418 covering the plurality of contacts 120 . For example, in some embodiments, the first metal material 410 may include tungsten (W), titanium (Ti), tantalum nitride (TaN), or titanium nitride (TiN). In some embodiments, the second metal material 412 may include copper (Cu) or aluminum copper (AlCu).

It should be appreciated that due to its integration with BEOL (back end of line) metallization layers, the disclosed field plates allow for various field plate biasing configurations that are easily implemented for different design considerations. For example, the field plate bias may be changed by changing the metal wiring layers rather than by changing the design of the disclosed high voltage device. Furthermore, it should be understood that biasing high voltage transistor devices via BEOL metal interconnect routing allows various field plate biasing configurations to be integrated on the same chip using a single manufacturing process flow.

5-6 illustrate cross-sectional views of some embodiments of field plate biasing configurations of high voltage transistor devices implemented with BEOL metal interconnect routing. Although FIGS. 5-6 illustrate connections between field plate 214 and contact region 208 or gate electrode 108 through a first metal line layer (eg, 504 or 604), BEOL metal interconnect wiring is not limited thereto. Rather, it is understood that the field plate 214 may be connected to the source region through any combination of BEOL metal interconnect layers (eg, a first metal line layer, a first metal via layer, a second metal line layer, etc.), Gate electrode, drain area or body contact.

FIG. 5 shows a cross-sectional view of high voltage LDMOS device 500 with field plate 214 electrically coupled to contact region 208 along conductive path 506 . Field plate 214 is connected to first metal line layer 504 disposed within second ILD layer 502 . The first metal line layer 504 is coupled to the contact 120a adjacent the contact area 208. By electrically coupling field plate 214 to contact region 208, field plate 214 is biased by a source voltage. The high voltage LDMOS device 500 is provided with low on-resistance Rds(on) and low dynamic power consumption (eg, low Rds(on)*Qgd and BV (ie, breakdown voltage)) by the source voltage bias field plate 214 . Low dynamic power consumption provides good performance during high frequency switching applications.

FIG. 6 shows a cross-sectional view of a high voltage LDMOS device 600 in which field plate 214 is electrically coupled to gate electrode 108 along conductive path 606 . Field plate 214 is connected to first metal line layer 604 disposed within second ILD layer 602 . The first metal line layer 604 is connected to the contact 120b adjacent the gate electrode 108. By electrically coupling field plate 214 to gate electrode 108, field plate 214 is biased by the gate voltage. The high voltage LDMOS device 600 is provided with low Rds(on) and breakdown voltage by gate voltage biasing the field plate 214 .

Various field plate biasing configurations allow the disclosed field plates to form versatile high voltage transistor devices that can be used in different applications. For example, the on-state resistance Rds(on) of a high-voltage transistor device with a gate-biased field plate is lower than the Rds(on) of a high-voltage transistor device with a source-biased field plate. However, the Rds(on)*Qgd of a high-voltage transistor device with a source-biased field plate is lower than that of a high-voltage transistor device with a gate-source biased field plate. Therefore, high-voltage transistor devices with gate-biased field plates (eg, high-voltage LDMOS device 500 ) may be used in low-frequency switching applications (eg, below 10 MHz), while high-voltage transistor devices with source-biased field plates (eg, high-voltage LDMOS device 600) may be used in high frequency switching applications (eg, above 10 MHz).

Figures 7A-7C illustrate cross-sectional views of some embodiments of high voltage LDMOS devices 700a-700c in different switch isolation configurations.

As shown in Figure 7A, high voltage LDMOS device 700a is configured as a low side switch (eg, a switch connected to ground in an inverter). In such a configuration, high voltage LDMOS device 700a has a floating source region 104 such that the voltage on source region 104 can change during the conversion cycle.

As shown in Figure 7B, high voltage LDMOS device 700b is configured as a high side switch (eg, a switch connected to VDD in a converter). In such a configuration, high voltage LDMOS device 700b has source region 104 connected to the source voltage. High voltage LDMOS device 700b has a drift region 702 extending beneath body region 202 to prevent the source voltage from rising to high by preventing charge carriers from being transferred from contact region 208 into semiconductor substrate 102 (eg, by tunneling). to the substrate voltage.

As shown in Figure 7C, high voltage LDMOS device 700c is fully isolated from the substrate to allow independent biasing. High voltage transistor device 700c includes a deep well 704 and an oppositely doped underlying buried layer 706 configured to provide vertical isolation. In some embodiments, deep well 704 may have a first doping type (eg, the same doping type as body region 202 ), and buried layer 706 may have a second doping type.

High voltage LDMOS device 700c also includes one or more additional STI regions 206 that laterally separate the drain region from the body region 708 and the buried layer 710, wherein the buried layer 710 has a second doping type. Body region 708 covers deep well 704 and buried layer 710 covers well region 712 having the second doping type and adjacent buried layer 706 . Contact 120 is configured to provide a bias voltage to body region 708 and buried layer 710 to form junction isolation between deep well 704 and buried layer 706 and well region 712 . Junction isolation allows the fully isolated high voltage LDMOS device 700c to operate over a range of bias voltages.

FIG. 8 shows a cross-sectional view of a high voltage transistor device 800 having a field plate 214 with source down.

High voltage transistor device 800 includes a substrate 802 having a high doping concentration of a first doping type (eg, a p+ doping type). Source region 804 is disposed along the backside 802b of substrate 802. In various embodiments, source region 804 may include a highly doped region or metal layer. An epitaxial layer 806 having a first conductivity type is disposed on the front side surface 802f of the substrate 802. The dopant concentration of epitaxial layer 806 is less than the dopant concentration of substrate 802 . Source contact region 810 , drain region 106 , body region 808 and drift region 204 are disposed within the top surface of epitaxial layer 806 .

Conductive material 812 extends from the top surface of epitaxial layer 806 into substrate 802 . Conductive material 812 may include highly doped deep well regions. Conductive material 812 allows source connections to be made from the backside of substrate 802, thereby reducing metal routing complexity and enabling various package compatibility. In some embodiments, field plate 214 may be biased by the source voltage through electrical path 818 that extends through contact 814 adjacent conductive material 812 and overlying metal line layer 816 coupled to field plate 214 .

Figures 9A-9B illustrate some embodiments of the disclosed high voltage LDMOS devices with field plates 902 in metal line layers. Although FIGS. 9A-9B illustrate the field plate on the first metal line layer, it should be understood that the disclosed field plate is not limited to the first metal line layer, but may be on optional layers of the BEOL metallization stack. implementation.

As shown in cross-sectional view 900 of FIG. 9A , a field plate 902 is disposed in a first metal line layer within a second ILD layer 904 covering the first ILD layer 118 . In some embodiments, field plate 902 has substantially flat top and bottom surfaces to provide field plate 902 with a planar topology. Field plate 902 is vertically separated from gate structure 210 and drift region 204 by first ILD layer 118 . Field plate 902 covers portions of gate electrode 108 and drift region 204 and is laterally separated from source region 104 and drain region 106 . For example, field plate 902 may be laterally separated from drain region 106 by a distance d. In some embodiments, field plate 902 may extend laterally from over gate electrode 108 to over drift region 204 .

As shown in top view 906 of FIG. 9B , field plate 902 includes a metal structure covering portions of gate electrode 108 and drift region 204 . The metal structure is not connected via contacts 120 to an underlying component or to another metal structure on the first metal line layer. Rather, the metal structure will be connected to overlying vias (not shown) configured to connect the field plate to the overlying metal line layer so that the field plate 902 can be biased.

Figure 10 illustrates some embodiments of the disclosed high voltage LDMOS device 1000 having a self-aligned drift region 1002.

Self-aligned drift region 1002 has sidewalls 1002s that are substantially aligned with the sidewalls of gate electrode 108 and gate dielectric layer 110 . In some alternative embodiments, self-aligned drift region 1002 may be formed with sidewalls 1002s substantially aligned with edges of sidewall spacers 212 . By aligning the self-aligned drift region 1002 with the sidewalls of the gate electrode 108 and the gate dielectric layer 110, the self-aligned drift region 1002 and the space s are laterally separated from the body region 202, thereby minimizing the gate and drain overlap and achieve low gate-drain charge (Qgd) and good high-frequency performance. Field plate 214 covering self-aligned drift region 1002 can further reduce gate-drain charge (Qgd).

11 illustrates a flow diagram of some embodiments of a method 1100 of forming a high voltage transistor device with a field plate. This method can use process steps already used during standard CMOS manufacturing processes to form field plates, thus providing a low-cost, universal field plate.

Although the disclosed methods (eg, methods 1100 and 3300) are shown and described herein as a series of actions or events, it should be understood that the illustrated order of these actions or events should not be interpreted in a limiting sense. For example, some actions may occur in a different order and/or concurrently with other actions or events in addition to those shown and/or described herein. Additionally, not all illustrated acts may be required to implement one or more aspects or embodiments described herein. Additionally, one or more actions depicted herein may be performed in one or more separate actions and/or stages.

At act 1102, a substrate is provided having source and drain regions separated by a channel region. In some embodiments, the substrate may further include a drift region between the source region and the drain region adjacent the channel region.

At act 1104, a gate structure is formed on the substrate at a location disposed between the source region and the drain region. The gate structure may include a gate dielectric layer and an overlying gate electrode.

At act 1106, the drift region may be formed using a self-aligned process that, in some embodiments, selectively implants the semiconductor substrate according to the gate structure to form the drift region.

At act 1108, one or more dielectric layers are selectively formed over the gate electrode and a portion of the drift region.

At act 1110, a contact etch stop layer (CESL) and a first interlayer dielectric (ILD) layer are formed over the substrate.

At act 1112, the first ILD layer is selectively etched to define contact openings and field plate openings.

At act 1114, the contact openings and field plate openings are filled with the first metallic material.

At act 1116, a planarization process may be performed to remove excess first metal material covering the first ILD layer.

At act 1118, a second metal material corresponding to the first metal line layer is deposited. In some embodiments, the second metallic material may further fill the field plate openings. In such embodiments, the second metallic material is embedded within the first metallic material within the field plate opening.

At act 1120, a second interlayer dielectric (ILD) layer is formed over the first ILD layer and over the first metal line layer structure.

12-19 illustrate cross-sectional views of some embodiments of methods of forming MOSFET devices with field plates. Although FIGS. 12 to 19 are described with respect to method 1100, it should be understood that the structures shown in FIGS. 12 to 19 are not limited to this method, but may stand alone as structures independent of this method.

FIG. 12 shows some embodiments of a cross-sectional view 1200 corresponding to act 1102.

As shown in cross-sectional view 1200, a semiconductor substrate 102 is provided. Semiconductor substrate 102 may be inherently doped with the first doping type. In various embodiments, semiconductor substrate 102 may include any type of semiconductor body (eg, silicon, SOI) including, but not limited to, a semiconductor die or wafer or one or more dies on a wafer, and Any other type of semiconductor and/or epitaxial layer formed thereon and/or otherwise associated therewith.

Semiconductor substrate 102 may be selectively implanted using various implantation steps to form multiple implanted regions (eg, well regions, contact regions, etc.). For example, semiconductor substrate 102 may be selectively implanted to form body region 202, drift region 204, source region 104, drain region 106, and contact region 208. The high energy dopant 1204 (eg, a p-type dopant species such as boron or an n-type dopant species such as phosphorus) can be removed by selectively masking the semiconductor substrate 102 (eg, using a photoresist mask). Exposed areas of the semiconductor substrate 102 are introduced to form a plurality of implanted areas. For example, as shown in cross-sectional view 1200, mask layer 1202 is selectively patterned to expose portions of semiconductor substrate 102, and high energy dopants 1204 are subsequently implanted therein to form source region 104 and drain region 106.

It should be understood that the implanted region shown in cross-sectional view 1200 is one example of possible implanted regions and that the semiconductor substrate 102 may include other configurations of implanted regions, such as any of the configurations shown in FIGS. 1-10 .

FIG. 13 shows some embodiments of a cross-sectional view 1300 corresponding to act 1104.

As shown in cross-sectional view 1300 , gate structure 210 is formed over semiconductor substrate 102 at a location disposed between source region 104 and drain region 106 . Gate structure 210 may be formed by forming gate dielectric layer 110 over semiconductor substrate 102 and by forming gate electrode material 108 over gate dielectric layer 110 . In some embodiments, gate dielectric layer 110 and gate electrode material 108 may be deposited by vapor deposition techniques. Gate dielectric layer 110 and gate electrode material 108 may then be patterned and etched (eg, according to a photoresist mask) to define gate structure 210 . In some embodiments, sidewall spacers 112 may be formed on opposite sides of gate electrode 108 by depositing a nitride-based material or an oxide-based material onto semiconductor substrate 102 and selectively etching the nitride. base material or oxide-based material to form the sidewall spacers 112 .

FIG. 14 shows some embodiments of a cross-sectional view 1400 corresponding to act 1108.

As shown in cross-sectional view 1400, one or more dielectric layers 124 are selectively formed over the gate electrode 108 and the drift region 204. In some embodiments, one or more dielectric layers 124 may be deposited by vapor deposition techniques and subsequently patterned and etched (eg, according to a photoresist mask). In some embodiments, one or more dielectric layers 124 may be etched to expose a portion of gate electrode 108 and be laterally spaced apart from drain region 106 .

In some embodiments, one or more dielectric layers 124 may include a suicide barrier layer, such as a resist protective oxide (RPO) layer. In other embodiments, one or more dielectric layers 124 may further and/or alternatively include a field plate etch stop layer (ESL). In some embodiments, the field plate ESL may be a silicon nitride (SiN) layer formed by vapor deposition techniques. In other embodiments, one or more dielectric layers 124 may further and/or alternatively include a gate dielectric layer or an interlayer dielectric (ILD) layer.

Figure 15 shows some embodiments of a cross-sectional view 1500 corresponding to act 1110.

As shown in cross-sectional view 1500 , a contact etch stop layer (CESL) 1502 is formed on the semiconductor substrate 102 . In some embodiments, CESL 1502 may be formed through a vapor deposition process. A first interlayer dielectric (ILD) layer 1504 is then formed over CESL 1502 . In some embodiments, first ILD layer 1504 may include an ultra-low-k dielectric material or a low-k dielectric material (eg, SiCO). In some embodiments, the first ILD layer 1504 may also be formed through a vapor deposition process. In other embodiments, the first ILD layer 1504 may be formed by a spin coating process. It should be understood that the term "interlayer dielectric (ILD) layer" as used herein may also refer to an intermetal dielectric (IMD) layer.

FIG. 16 shows some embodiments of a cross-sectional view 1600 corresponding to act 1112.

As shown in cross-sectional view 1600 , first ILD layer 1504 is selectively exposed to first etchant 1602 , wherein first etchant 1602 is configured to form contact openings 1606 and field plate openings 1608 . In some embodiments, contact openings 1606 may be smaller than field plate openings 1608 . In some embodiments, first ILD layer 1504 is selectively exposed to first etchant 1602 based on mask layer 1604 (eg, a photoresist layer or a hard mask layer). In some embodiments, the first etchant 1602 may have a large etch selectivity between the first ILD layer 1504 and the field plate ESL within the one or more dielectric layers 124 . In some embodiments, first etchant 1602 may include a dry etchant. In some embodiments, the dry etchant may contain oxygen (O ₂ ), nitrogen (N ₂ ), hydrogen (H ₂ ), argon (Ar), and/or fluorine species (e.g., CF ₄ , CHF ₃ , C ₄ F ₈ , etc.) one or more etching chemicals. In other embodiments, first etchant 1602 may include a wet etchant containing dilute hydrofluoric acid (BHF).

Figure 17 shows some embodiments of a cross-sectional view 1700 corresponding to actions 1114-1116.

As shown in cross-sectional view 1700, contact openings 1606 and field plate openings 1608 are filled with a first metallic material 1702. In some embodiments, the first metal material 1702 may be deposited by a vapor deposition technique (eg, CVD, PVD, PE-CVD, etc.). In some embodiments, the first metal material 1702 may be formed by depositing a seed layer by physical vapor deposition and then performing a plating process (eg, electroplating or electroless plating process). A planarization process (eg, chemical mechanical planarization) may then be performed to remove excess first metal material 1702 and form a planar surface along line 1704 .

In some embodiments, first metal material 1702 may include tungsten (W), titanium (Ti), titanium nitride (TiN), or tantalum nitride (TaN). In some embodiments, a diffusion barrier layer and/or a liner layer may be deposited into contact openings 1606 and field plate openings 1608 prior to depositing first metallic material 1702 .

Figure 18 shows some embodiments of a cross-sectional view 1800 corresponding to act 1118.

As shown in cross-sectional view 1800, a second metallic material 1802 is deposited. A second metal material 1802 is formed within the remaining openings in the field plate openings and over the first ILD layer 118 . In some embodiments, the second metallic material 1802 may be deposited by a vapor deposition technique (eg, CVD, PVD, PE-CVD, etc.). In some embodiments, the second metal material 1802 may be formed by depositing a seed layer by physical vapor deposition and then performing a plating process. In some embodiments, the second metallic material 1802 may include copper (Cu) or aluminum copper (AlCu) alloy.

After formation, the second metal material 1802 may be selectively patterned to define one or more metal structures covering the first metal line layer 418 of the first ILD layer 118 . In some embodiments, the method may be achieved by forming a patterned mask layer (eg, a photoresist layer or a hard mask layer) (not shown) on the second metal material 1802 and then masking the The second metal material 1802 is etched in the exposed areas of the layer to selectively pattern the second metal material 1802 .

FIG. 19 shows some embodiments of a cross-sectional view 1900 corresponding to act 1120.

As shown in cross-sectional view 1900 , a second ILD layer 416 is formed over the first ILD layer 118 and one or more metal structures of the first metal line layer 418 . In various embodiments, second ILD layer 416 may be formed by depositing a second ILD material on one or more metal structures of first ILD layer 118 and first metal line layer 418 . After the second ILD layer 416 is formed, a planarization process (eg, CMP) is performed to remove excess second ILD layer 416 and expose the top surface of one or more metal structures of the first metal line layer 418 . In various embodiments, the second ILD layer 416 may include an ultra-low-k dielectric material or a low-k dielectric material (eg, SiCO) formed by a vapor deposition process or a spin coating process.

It should be appreciated that height differences among the multiple contacts (eg, 120) and field plates (eg, 122) may cause difficulties during fabrication of the disclosed transistor devices. For example, because the field plate (eg, 122) is formed over dielectric layer 124 (eg, resist protection oxide), the field plate (eg, 122) has a smaller height than the plurality of contacts (eg, 120). However, the same etching process is used to form the field plate (eg, 122) and the plurality of contacts (eg, 120). The height difference can result in over-etching of field plate openings (eg, 1608 in FIG. 16) or under-etching of contact openings (eg, 1606 in FIG. 16), where over-etching of field plate openings can result in field plate (eg, 122) and the conductive channel of the transistor device, while insufficient etching of the contact openings can result in multiple contacts (e.g., 120) to the source region (e.g., 104), drain region (e.g., 106), and/or or poor connections between gate structures (e.g., 210).

To prevent over-etching of field plate openings or under-etching of contact openings, in some embodiments, a combined etch stop layer may be used to control the etch depth of the field plate openings. The combined etch stop layer allows multiple contacts (eg, 120) and field plates (eg, 122) to be precisely formed to different heights by controlling the etch depth of the field plate openings.

Figure 20 shows a cross-sectional view of some embodiments of the disclosed high voltage transistor device 200 having a combined etch stop layer defining a field plate.

High voltage transistor device 2000 includes gate structure 116 disposed over semiconductor substrate 102 . Gate structure 116 includes gate dielectric layer 110 and an overlying gate electrode 108 . In some embodiments, gate structure 116 may have a first thickness th ₁ in a range between about 1000 angstroms and about 2000 angstroms. Source region 104 and drain region 106 are provided in semiconductor substrate 102 on opposite sides of gate structure 116 .

Resist protective oxide (RPO) 2002 is disposed over gate structure 116 . RPO 2002 extends laterally across the outermost sidewalls of gate structure 116 from directly above gate structure 116 . In some embodiments, RPO 2002 may extend vertically from the upper surface of the gate structure to the upper surface of semiconductor substrate 102 and laterally from directly above gate structure 116 to gate structure 116 and drain region 106 between. In some embodiments, RPO 2002 may include silicon dioxide, silicon nitride, and the like. In some embodiments, RPO 2002 can have a second thickness _th2 in a range between about 100 Angstroms and about 1000 Angstroms.

A combined etch stop layer 2004 is disposed over RPO 2002 . In some embodiments, combined etch stop layer 2044 directly contacts one or more upper surfaces of RPO 2002. A first interlayer dielectric (ILD) layer 118 and a field plate 122 are disposed over the combined etch stop layer 2004 . The first ILD layer 118 surrounds the field plate 122 and a plurality of contacts 120 coupled to the source region 104 , the drain region 106 and the gate structure 116 . In some embodiments, field plate 122 and plurality of contacts 120 may include a diffusion barrier layer (not shown) surrounding a conductive core including one or more metals.

Combined etch stop layer 2004 includes a plurality of different dielectric layer materials 2006 - 2008 stacked over RPO 2002 . In some embodiments, the plurality of different dielectric materials 2006 - 2008 may have outermost sidewalls that are substantially aligned along a line perpendicular to the upper surface of the semiconductor substrate 102 . In some embodiments, the plurality of different dielectric materials 2006 - 2008 may have outermost walls that are substantially aligned with the outermost walls of RPO 2002 . In such embodiments, the first width of RPO 2002 has a second width that is substantially equal to the combined etch stop layer 2004 . The plurality of different dielectric materials 2006-2008 have different etch properties, thereby providing respective ones of the plurality of different dielectric materials 2006-2008 with different etch selectivities relative to the etchants. Different etch selectivities allow the combined etch stop layer 2004 to slowly etch the field plate openings (eg, defining the openings of the field plate 122 ) and, therefore, tightly control the height of the field plate and enable multiple contacts 120 and the height between the field plate 122 differences (eg, such that plurality of contacts 120 have a higher height than field plate 122).

For example, in some embodiments, the bottom of field plate 122 is located vertically between the bottom surfaces of one or more of plurality of contacts 120 (eg, contacts coupled to source region 104 and drain region 106 ). Etch stop layer 2004 on the interface contact combination. In such an embodiment, during fabrication of high voltage transistor device 2000, combined etch stop layer 2004 reduces the etch rate of the etchant used to form the field plate openings (ie, the openings that define field plate 122). The reduced etch rate causes the bottom surface of field plate 122 to be higher than the bottom surface of one or more contacts 120 .

In some embodiments, the combined etch stop layer 2004 may include a first dielectric material 2006 directly contacting the upper surface of the RPO 2002 and a second dielectric material 2008 directly contacting the upper surface of the first dielectric material 2006 . In some embodiments, the first dielectric material 2006 may have a third thickness th ₃ and the second dielectric material 2008 may have a fourth thickness th ₄ . In some embodiments, RPO 2002 and combined etch stop layer 2004 may each have a substantially constant thickness between the outermost sidewalls. If the third thickness th ₃ and the fourth thickness th ₄ are too small (eg, less than the minimum values set forth below), the combined etch stop layer 2004 cannot effectively stop the etch forming the field plate openings. If the third thickness th ₃ and the fourth thickness th ₄ are too large (eg, greater than the maximum value explained below), the effectiveness of the field plate 122 on the high voltage transistor device 2000 is reduced, thereby negatively affecting device performance.

In some embodiments, first dielectric material 2006 may include silicon nitride ( _{SixNy )} and second dielectric material 2008 may include silicon dioxide ( _SiO2 ). In such embodiments, the first thickness th ₁ may be in a first range between about 50 angstroms and about 400 angstroms, and the second thickness th ₂ may be in a second range between about 150 angstroms and about 700 angstroms. In other embodiments, the first dielectric material 2006 may include or be silicon dioxide (SiO ₂ ) and the second dielectric material 2008 may include or be silicon nitride ( _Six N _y ) or silicon oxynitride (SiO _x N _y ). In such embodiments, the first thickness th ₁ may be within a first range between about 600 Angstroms and about 900 Angstroms. In some embodiments, the second thickness th ₂ may be in a second range between about 100 angstroms and about 500 angstroms.

21A-21B illustrate some additional embodiments of the disclosed high voltage transistor device having a combined etch stop layer defining a field plate.

As shown in cross-sectional view 2100 of FIG. 21A , a high voltage transistor device includes a semiconductor substrate 102 having a body region 2106 disposed within a drift region 2104 above the substrate 2102 . Source region 104 is disposed within body region 2106 and drain region 106 is disposed within drift region 2104 . In some embodiments, source region 104 , drain region 106 , and drift region 2104 can have a first doping type (eg, n-type), while body region 2106 and substrate 2102 have a doping type opposite to the first doping type. Second doping type (eg, p-type). In some embodiments, source region 104 and drain region 106 may include highly doped regions (ie, n+ regions) with a doping concentration higher than that of drift region 2104 .

Gate structure 116 is disposed over semiconductor substrate 102 between source region 104 and drain region 106 . RPO 2002 is disposed over gate structure 116 and extends laterally across the outermost sidewalls of gate structure 116 . Combined etch stop layer 2004 is disposed between RPO 2002 and field plate 122 . In some embodiments, the RPO 2002 may enclose the field plate 122 (ie, extend beyond the outermost sidewalls of the field plate 122 ) by one or more lateral distances 2108 , where the one or more lateral distances are between about 0 micron to about 2 micron.

In some embodiments, field plate 122 may extend to a non-zero depth 2110 in combined etch stop layer 2004 . In such embodiments, field plate 122 contacts the sidewalls of combined etch stop layer 2004 . In various embodiments, field plate 122 may also contact a horizontally extending surface of combined etch stop layer 2004 or a horizontally extending surface of RPO 2002 . In some embodiments, non-zero depth 2110 may range between about 400 Angstroms and about 700 Angstroms. Because the field plate 122 extends into the combined etch stop layer 2004, the combined etch stop layer 2004 has a first thickness 2112 directly under the field plate 122 and a second thickness outside the field plate 122, where the second thickness is greater than the A thickness of 2112. In some embodiments, first thickness 2112 ranges between about 0 angstroms and about 10,000 angstroms. In some additional embodiments, first thickness 2112 ranges between about 600 Angstroms and about 3000 Angstroms.

As shown in cross-sectional view 2120 of FIG. 21B (along cross-section line A-A' of FIG. 21A ), the width 2114 of the field plate 122 extending in the first direction has a distance in the range between approximately 150 nanometers and 2000 nanometers. The field plate 122 also has a length 2122 extending in a second direction (perpendicular to the first direction) a distance of less than about 1000 μm.

Referring again to the cross-sectional view of Figure 21A, in some embodiments, field plate 122 may be laterally separated from gate structure 116 by a distance 2116. For example, field plate 122 may be laterally separated from gate structure 116 by a distance in a range between about 0 nm and about 200 nm. In other embodiments (not shown), field plate 122 may laterally overlap gate structure 116 (ie, extend directly above gate structure 116). For example, the field plate 122 laterally overlaps the gate structure 116 by a distance of between about 0 nm and about 200 nm.

In some embodiments, a suicide layer 2118 is disposed over the source region 104 , the drain region 106 , and portions of the gate structure 116 not covered by the RPO 2002 . In various embodiments, suicide layer 2118 may include compounds having silicon and metals, such as nickel, platinum, titanium, tungsten, magnesium, and the like. In some embodiments, suicide layer 2118 has a thickness ranging between about 150 Angstroms and about 400 Angstroms.

22 illustrates a cross-sectional view of some additional embodiments of the disclosed high voltage transistor device 2200 having a combined etch stop layer defining a field plate.

High voltage transistor device 2200 includes gate structure 108 disposed over semiconductor substrate 102 . RPO 2002 and combined etch stop layer 2004 are located over gate electrode 108 and semiconductor substrate 102 . A contact etch stop layer (CESL) 406 is disposed over the combined etch stop layer 2004 . In some embodiments, the bottom surface of combined etch stop layer 2004 may directly contact RPO 2002 and the top surface of combined etch stop layer 2004 may directly contact CESL 406 . CESL 406 extends laterally beyond the outermost sidewalls of combined etch stop layer 2004 and contacts semiconductor substrate 102 . In some embodiments, CESL 406 may have a thickness th ₅ in a range between about 100 angstroms and about 1000 angstroms. In some embodiments, CESL 406 may include silicon nitride, silicon carbide, or the like.

Field plate 408 is disposed within first ILD layer 118 above CESL 406 . In some embodiments, field plate 408 may include first metallic material 410 and second metallic material 412 . Combined etch stop layer 2004 is disposed laterally between field plate 408 and gate structure 116 and vertically between field plate 122 and semiconductor substrate 102 . RPO 2002 and combined etch stop layer 2004 have sidewalls contacting CESL 406 . The combined etch stop layer 2004 further has a horizontally extending surface (eg, an upper surface) that contacts the CESL 406 .

In some embodiments, field plate 122 may extend into one or more of a plurality of different dielectric materials 2006 - 2008 within combined etch stop layer 2004 . For example, in some embodiments, the combined etch stop layer 2004 may include a first dielectric material 2006 and a second dielectric material 2008 contacting an upper surface of the first dielectric material 2006 . Field plate 122 may extend through second dielectric material 2008 (eg, silicon oxide) and have a bottom surface contacting first dielectric material 2006 (eg, silicon nitride). In such embodiments, first dielectric material 2006 may vertically separate the bottommost point of field plate 122 from RPO 2002 . In other embodiments, field plate 122 may extend further through first dielectric material 2006 and have a bottom surface and/or sidewalls contacting RPO 2002 . In some embodiments, field plate 122 may extend vertically through second dielectric material 2008 and also be laterally separated from gate structure 116 by second dielectric material 2008 .

Although the disclosed combined etch stop layer 2004 is shown in FIGS. 20-22 with two different dielectric materials 2006-2008 stacked over the RPO 2002. It should be understood, however, that the disclosed combined etch stop layer 2004 is not limited to this configuration. Rather, in various embodiments, combined etch stop layer 2004 may include additional layers of dielectric material. 23-24 illustrate some non-limiting examples of alternative embodiments of the disclosed combined etch stop layer 2004.

23 illustrates a cross-sectional view of some additional embodiments of the disclosed high voltage transistor device 2300 having a combined etch stop layer defining a field plate.

High voltage transistor device 2300 includes a combined etch stop layer 2004 disposed over RPO 2002 . Combined etch stop layer 2004 includes a first dielectric material 2302 , a second dielectric material 2304 contacting an upper surface of first dielectric material 2302 , and a third dielectric material 2306 contacting an upper surface of second dielectric material 2304 . In some embodiments, the first dielectric material 2302 may include or be silicon dioxide (SiO ₂ ) and the second dielectric material 2304 may include or be silicon nitride ( _Six N _y ) or silicon oxynitride (SiO _x N _y ) and the third dielectric material 2306 may include or be silicon dioxide (SiO ₂ ).

In some embodiments, first dielectric material 2302 can have a first thickness, second dielectric material 2304 can have a second thickness, and third dielectric material 2306 can have a third thickness. In some embodiments, the first thickness can be in a first range between about 300 angstroms and about 900 angstroms, the second thickness can be in a second range between about 50 angstroms and about 200 angstroms, and the third thickness can be in in a third range between about 200 Angstroms and about 600 Angstroms.

24 illustrates a cross-sectional view of some additional embodiments of the disclosed high voltage transistor device 2400 having a combined etch stop layer defining a field plate.

High voltage transistor device 2400 includes a combined etch stop layer 2400 disposed over RPO 2002 . Combined etch stop layer 2400 includes a first dielectric material 2402, a second dielectric material 2404 contacting an upper surface of the first dielectric material 2402, a third dielectric material 2406 contacting an upper surface of the second dielectric material 2404, and a contact Fourth dielectric material 2408 on the upper surface of third dielectric material 2406 . In some embodiments, the first dielectric material 2402 may include or be silicon dioxide (SiO ₂ ) and the second dielectric material 2404 may include or be silicon nitride ( _Six N _y ) or silicon oxynitride (SiO _x N _y ) and the third dielectric material 2406 may comprise or be silicon dioxide (SiO ₂ ) and the fourth dielectric material 2408 may comprise or be silicon nitride ( _Six N _y ) or silicon oxynitride (SiO _x N _y ).

In some embodiments, first dielectric material 2402 can have a first thickness, second dielectric material 2404 can have a second thickness, third dielectric material 2406 can have a third thickness and fourth dielectric material 2408 can have Fourth thickness. In some embodiments, the first thickness can be in a first range between about 300 angstroms and about 900 angstroms, the second thickness can be in a second range between about 50 angstroms and about 200 angstroms, and the third thickness can be in about A third range is between 200 Angstroms and about 600 Angstroms and a fourth thickness is within a fourth range between about 50 Angstroms and about 200 Angstroms.

25-32 illustrate cross-sectional views of some embodiments of a method of forming a high voltage transistor device having a combined etch stop layer defining a field plate. Although the cross-sectional views 2500 to 3200 shown in Figures 25 to 32 are described with reference to a method, it should be understood that the structures shown in Figures 25 to 32 are not limited to this method but may exist independently of this method.

As shown in the cross-sectional view of FIG. 25, the semiconductor substrate 102 is selectively implanted to form a plurality of implanted regions (eg, well regions, contact regions, etc.). In some embodiments, semiconductor substrate 102 may be selectively implanted to form body region 2106, drift region 2104, source region 104, and drain region 106. In other embodiments, the semiconductor substrate 102 may be selectively implanted to form different implanted regions (eg, such as any of the implanted regions shown in FIGS. 1-10 ). In some embodiments, multiple implant regions may be formed by selectively masking the semiconductor substrate 102 (eg, using a photoresist mask) and then adding high energy dopants (eg, p-type dopants such as boron). Dopants (or n-type dopants such as phosphorus) are introduced into the exposed areas of the semiconductor substrate 102 .

Gate structure 116 is formed over semiconductor substrate 102 between source region 104 and drain region 106 . Gate structure 116 may be formed by depositing gate dielectric layer 110 over semiconductor substrate 102 and depositing gate electrode 108 over gate dielectric layer 110 . Gate dielectric layer 110 and gate electrode material 108 may then be patterned (etched according to a photoresist mask and/or hard mask) to define gate structure 116 .

As shown in the cross-sectional view of FIG. 26 , a resist protective oxide (RPO) 2002 is formed over the gate structure 116 . RPO 2002 extends laterally across the outermost sidewalls of gate structure 116 from directly above gate structure 116 . RPO 2002 is configured to block silicide formation on underlying layers. In some embodiments, RPO 2002 may be deposited by vapor deposition techniques (eg, CVD). In some embodiments, RPO 2002 may include silicon dioxide (SiO ₂ ), silicon nitride, and the like.

As shown in cross-sectional view 2700 of FIG. 27 , a combined etch stop layer 2004 including a plurality of different dielectric materials 2600 - 2800 is selectively formed over the RPO 2002 . In some embodiments, a plurality of different dielectric materials 2006-2008 may be deposited sequentially via vapor deposition techniques. In some embodiments, the combined etch stop layer 2004 may include a stack of layers, wherein the stack of layers includes a silicon nitride ( _SixNy ) layer, a silicon oxynitride ( _SiOxNy ) layer, and/or a silicon dioxide ( _{SiOxNy )} layer. SiO ₂ ) two or more middle layers.

In some embodiments, the same masking layer 2702 (eg, photoresist layer) and etching process may be used to pattern multiple different dielectric materials 2006-2008 and RPO 2002. Patterning multiple different dielectric materials 2006-2008 and RPO 2002 using the same masking layer 2702 alleviates the cost of combining the etch stop layer 2004. In such embodiments, the plurality of different dielectric materials 2006-2008 and RPO 2002 may have substantially aligned sidewalls.

As shown in the cross-sectional view of FIG. 28 , a contact etch stop layer (CESL) 406 is formed over the semiconductor substrate 102 and the combined etch stop layer 2004 . In some examples, CESL 406 may be formed through a vapor deposition process. CESL may include a nitride layer (eg, Si ₃ N ₄ ), a carbide layer (SiC), or the like.

As shown in cross-section 2900 of FIG. 29 , a first interlayer dielectric (ILD) is formed over CESL 406 . In some embodiments, first ILD layer 118 may include an oxide (eg, _SiO2 ), an ultra-low-k dielectric material, a low-k dielectric material (eg, SiCO), or the like. In some embodiments, first ILD layer 118 may be formed through a vapor deposition process.

As shown in the cross-sectional view of FIG. 30 , first ILD layer 118 may be selectively exposed to etchant 3002 (eg, in accordance with masking layer 3003 ) to form contact openings 1606 and field plate openings 1608 in first ILD layer 118 . Contact opening 1606 and field plate opening 1608 have an etch depth offset of non-zero distance 3004. In some embodiments, non-zero distance 3004 may range between about 400 Angstroms and about 2000 Angstroms. In some embodiments, the field plate opening 1608 extends into the combined etch stop layer 2004 such that the sidewalls of the combined etch stop layer 2004 define the field plate opening 1608 . In various embodiments, combined etch stop layer 2004 or PRO 2002 may define the bottom of field plate opening 1608 .

In some embodiments, etchant 3002 may reduce the thickness of combined etch stop layer 2004 by an amount ranging between about 400 Angstroms and about 700 Angstroms. In some embodiments, the thickness of combined etch stop layer 2004 directly beneath field plate opening 1608 ranges between approximately 0 angstroms and 1000 angstroms. In some additional embodiments, the thickness of the combined etch stop layer 2004 directly beneath the field plate opening 1608 ranges between about 300 angstroms and about 900 angstroms.

The etchant 3002 used to form the contact openings 1606 and the field plate openings 1608 is selected to etch through the material of the CESL 406 . However, because the combined etch stop layer 2004 is formed from a variety of different materials, the combined etch stop layer 2004 is able to resist etching by the etchant 3002 to a higher degree. The combined etch stop layer 2004 thereby allows the contact openings 1606 to extend to the semiconductor substrate 102 while preventing the field plate openings 1608 from extending to the semiconductor substrate 102 . The combined etch stop layer 2004 also allows for a higher degree of uniformity in etch depth at different locations on the substrates with respect to the same batch of substrates and/or with respect to different batches of substrates. For example, the combined etch stop layer 2004 allows the etch depth of the field plate openings 1608 on different substrates to vary within approximately 2% or less. This etch depth uniformity allows for improved device uniformity and performance compared to devices without the integrated etch stop layer 2004.

As shown in the cross-sectional view of Figure 31, contact openings 1606 and field plate openings 1608 are filled with one or more conductive materials. In some embodiments, one or more conductive materials may be deposited by vapor deposition techniques (eg, CVD, PVD, PE-CVD, etc.) and/or plating processes (eg, electroplating or electroless plating). A planarization process (eg, chemical mechanical planarization) may then be performed to remove excess conductive material(s) and form a planar surface along line 3102. In some embodiments, the one or more conductive materials may include tungsten (W), titanium (Ti), titanium nitride (TiN), and/or tantalum nitride (TaN). In some embodiments, during deposition Different barrier and/or liner layers may be deposited in contact openings 1606 and field plate openings 1608 prior to one or more conductive materials.

As shown in the cross-sectional view of FIG. 32 , a second ILD layer 126 is formed over the first ILD layer 118 and a first back-end-of-line (BEOL) metal line layer 128 is formed within the second ILD layer 126 . In such embodiments, second ILD layer 126 may be formed by depositing a second ILD layer material over first ILD layer 118 . The second ILD layer 126 is then etched to form trenches extending into the second ILD layer 126 . The trenches are filled with conductive material and a planarization process (eg, CMP) is performed to remove excess conductive material from above the second ILD layer 126 .

33 illustrates a flow diagram of some embodiments of a method 3300 of forming a high voltage transistor device having a combined etch stop layer defining a field plate.

At act 3302, a gate structure is formed over the substrate. 25 illustrates a cross-sectional view 2500 corresponding to some embodiments of act 3302.

At act 3304, source and drain regions are formed on opposite sides of the gate structure within the substrate. In some additional embodiments, one or more additional doped regions (eg, body regions, drift regions, etc.) may also be formed within the substrate. Figure 25 shows a cross-sectional view corresponding to some embodiments of act 3304.

At act 3306, a resist protection oxide (RPO) is formed over the gate structure and laterally between the gate structure and the drain region. 26 illustrates a cross-sectional view 2600 corresponding to some embodiments of act 3306.

At act 3308, a combined etch stop layer is formed over the RPO. Figure 27 shows a cross-sectional view corresponding to some embodiments of act 3308.

At act 3310, a contact etch stop layer (CESL) is formed on the combined etch stop layer. 28 illustrates a cross-sectional view 2800 corresponding to some embodiments of act 3310.

At act 3312, a first interlayer dielectric (ILD) layer is formed over the CESL. 29 illustrates a cross-sectional view 2900 corresponding to some embodiments of act 3312.

At act 3314, the first ILD layer is selectively etched to define a plurality of contact openings and field plate openings. The plurality of contact openings and field plate openings have different depths. 30 illustrates a cross-sectional view 3000 corresponding to some embodiments of act 3314.

At act 3316, the plurality of contact openings and field plate openings are filled with one or more conductive materials. 31 illustrates a cross-sectional view 3100 corresponding to some embodiments of act 3316.

At act 3318, conductive interconnect lines are formed within the second ILD layer over the first ILD layer. 32 illustrates a cross-sectional view 3200 corresponding to some embodiments of act 3318.

Accordingly, the present invention relates to a high voltage transistor device having a field plate, wherein the field plate is formed simultaneously with the formation of the conductive contacts. The device has a combined etch stop layer used to enable height differences of the field plate and conductive contacts.

In some embodiments, the invention relates to integrated chips. The integrated chip includes: a gate structure disposed between a source region and a drain region above a substrate; and a dielectric layer laterally extending from above the gate structure to the gate structure and the drain region between; a combined etch stop layer including a plurality of different dielectric materials stacked above the dielectric layer; a contact etch stop layer in direct contact with the upper surface and sidewalls of the combined etch stop layer; a field plate, Surrounded laterally by the first ILD layer and extending vertically from the top of the first ILD layer through the contact etch stop layer and into the combined etch stop layer. In some embodiments, the combined etch stop layer has a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material. In some embodiments, the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material. In some embodiments, the first dielectric material includes silicon nitride and the second dielectric material includes silicon dioxide. In some embodiments, the first dielectric material includes silicon dioxide and the second dielectric material includes silicon nitride or silicon oxynitride. In some embodiments, the field plate extends vertically through the second dielectric material and is vertically separated from the gate structure by the first dielectric material. In some embodiments, the combined etch stop layer has a first thickness directly under the field plate and a second thickness outside the field plate. In some embodiments, the combined etch stop layer laterally contacts sidewalls of the field plate. In some embodiments, the bottom of the field plate is separated from the dielectric layer by the combined etch stop layer. In some embodiments, the dielectric layer includes a resist protection oxide, wherein the resist protection oxide has a lower surface contacting the gate structure and an upper surface contacting the combined etch stop layer.

In an embodiment, the combined etch stop layer includes a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material.

In an embodiment, the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material.

In an embodiment, the first dielectric material includes silicon nitride and the second dielectric material includes silicon dioxide.

In an embodiment, the first dielectric material includes silicon dioxide and the second dielectric material includes silicon nitride or silicon oxynitride.

In an embodiment, the field plate extends vertically through the second dielectric material and is vertically separated from the gate structure by the first dielectric material.

In an embodiment, the combined etch stop layer has a first thickness directly under the field plate and a second thickness outside the field plate.

In embodiments, the combined etch stop layer laterally contacts sidewalls of the field plate.

In an embodiment, the bottom of the field plate is vertically separated from the dielectric layer by the combined etch stop layer.

In an embodiment, the dielectric layer includes a resist protection oxide, wherein the resist protection oxide has a lower surface contacting the gate structure and an upper surface contacting the combined etch stop layer.

In other embodiments, the invention relates to integrated chips. The integrated chip includes: a gate structure disposed above the substrate; a resist protective oxide extending laterally from above the gate structure through the outermost side wall of the gate structure; a combined etching stop layer including a first dielectric material above the corrosion protection oxide and a second dielectric material contacting the upper surface of the first dielectric material; a plurality of conductive contacts through the first interlayer dielectric above the substrate an electrical (ILD) layer laterally surrounding; and a field plate extending from a top of the first ILD layer to the combined etch stop layer and including the same material as the plurality of conductive contacts, wherein the combined etch stop A stop layer laterally contacts the sidewalls of the field plate and vertically separates the bottom of the field plate from the resist protective oxide. In some embodiments, the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material. In some embodiments, the first dielectric material is an oxide and the second dielectric material is a nitride. In some embodiments, the combined etch stop layer further includes: a third dielectric material in contact with the upper surface of the second dielectric material, wherein the first dielectric material and the third dielectric material Materials have the same material. In some embodiments, the integrated chip further includes: a contact etch stop layer in direct contact with the upper surface and sidewalls of the combined etch stop layer, wherein the field plate extends through the contact etch stop layer. In some embodiments, the resist protective oxide has a first width that is equal to a second width of the combined etch stop layer.

In an embodiment, the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material.

In an embodiment, the first dielectric material is an oxide and the second dielectric material is a nitride.

In an embodiment, the combined etch stop layer further includes: a third dielectric material in contact with the upper surface of the second dielectric material, wherein the first dielectric material and the third dielectric material It's the same material.

In an embodiment, the integrated chip further includes a contact etch stop layer in direct contact with the upper surface and sidewalls of the combined etch stop layer, wherein the field plate extends through the contact etch stop layer.

In an embodiment, the resist protective oxide has a first width equal to a second width of the combined etch stop layer.

In yet another embodiment, the invention relates to a method of forming an integrated chip. The method includes forming a gate structure over the substrate between a source region and a drain region within the substrate; forming a dielectric layer; forming a combined etch stop layer over the dielectric layer, wherein the combined etch stop layer includes a plurality of stacked dielectric materials; forming a first interlayer dielectric over the combined etch stop layer (ILD) layer; selectively etching the first ILD layer to simultaneously define contact openings extending to the substrate and field plate openings extending to the combined etch stop layer; and by one or more Conductive material fills the contact openings and the field plate openings. In some embodiments, the combined etch stop layer includes a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material. In some embodiments, the field plate opening extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material. In some embodiments, the method further includes: forming a masking layer over the combined etch stop layer; and etching the combined etch stop layer and the dielectric layer according to the masking layer.

In an embodiment, the combined etch stop layer includes a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material.

In an embodiment, the field plate opening extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material.

In an embodiment, the method further includes: forming a masking layer over the combined etch stop layer; and etching the combined etch stop layer and the dielectric layer according to the masking layer.

The features of several embodiments are summarized above to enable those skilled in the art to better understand various aspects of the invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the present invention. .

Claims (20)

1. An integrated chip, comprising:

A gate structure disposed between the source region and the drain region over the substrate;

a resist protective oxide layer extending laterally from above the gate structure to between the gate structure and the drain region;

combining an etch stop layer comprising a plurality of dielectric materials stacked over the etch resistant protective oxide layer having different etch selectivities to an etchant;

a conductive contact laterally surrounded by a first interlayer dielectric layer over the substrate; and

a contact etch stop layer in direct contact with the upper surface and sidewalls of the combined etch stop layer; and

a field plate laterally surrounded by and extending from the top of the first interlayer dielectric layer, vertically through the contact etch stop layer, and into the combined etch stop layer, the height of the field plate below the top surface of the first interlayer dielectric layer being less than the height of the conductive contact, the combined etch stop layer laterally contacting the side wall of the field plate and vertically separating the field plate from the resist protective oxide layer.

2. The integrated chip of claim 1, wherein the combined etch stop layer comprises a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material.

3. The integrated chip of claim 2, wherein the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material.

4. The integrated chip of claim 2, wherein the first dielectric material comprises silicon nitride and the second dielectric material comprises silicon dioxide.

5. The integrated chip of claim 2, wherein the first dielectric material comprises silicon dioxide and the second dielectric material comprises silicon nitride or silicon oxynitride.

6. The integrated chip of claim 2, wherein the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the first dielectric material.

7. The integrated chip of claim 1, wherein the combined etch stop layer has a first thickness directly below the field plate and a second thickness outside the field plate.

8. The integrated chip of claim 1, wherein the combined etch stop layer is in lateral contact with a sidewall of the field plate.

9. The integrated chip of claim 1, wherein a bottom of the field plate is separated from the resist protection oxide layer vertically by the combined etch stop layer.

10. The integrated chip of claim 1, wherein the resist protection oxide layer has a lower surface that contacts the gate structure and an upper surface that contacts the combined etch stop layer.

11. An integrated chip, comprising:

a gate structure disposed over the substrate;

a resist protection oxide extending laterally from above the gate structure beyond an outermost sidewall of the gate structure;

a combined etch stop layer comprising a first dielectric material over the etch-resistant protective oxide and a second dielectric material contacting an upper surface of the first dielectric material, the first dielectric material and the second dielectric material having different etch selectivities to an etchant;

a plurality of conductive contacts laterally surrounded by a first interlayer dielectric layer over the substrate; and

a field plate extending from a top of the first interlayer dielectric layer into the combined etch stop layer and comprising the same material as the plurality of conductive contacts, wherein a height of the field plate below a top surface of the first interlayer dielectric layer is less than a height of at least one of the conductive contacts, the combined etch stop layer laterally contacting sidewalls of the field plate and vertically separating the field plate from the resist protection oxide.

12. The integrated chip of claim 11, wherein the field plate extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material.

13. The integrated chip of claim 11, wherein the first dielectric material is an oxide and the second dielectric material is a nitride.

14. The integrated chip of claim 11, wherein the combined etch stop layer further comprises:

and a third dielectric material in contact with an upper surface of the second dielectric material, wherein the first dielectric material and the third dielectric material are the same material.

15. The integrated chip of claim 11, further comprising:

a contact etch stop layer in direct contact with an upper surface and sidewalls of the combined etch stop layer, wherein the field plate extends through the contact etch stop layer.

16. The integrated chip of claim 11, wherein the resist protection oxide has a first width equal to a second width of the combined etch stop layer.

17. A method of forming an integrated chip, comprising:

forming a gate structure over a substrate between a source region and a drain region within the substrate;

Forming a resist protection oxide layer over the gate structure and between the gate structure and the drain region;

forming a combined etch stop layer over the etch resistant protective oxide layer, wherein the combined etch stop layer comprises a plurality of stacked dielectric materials, the plurality of dielectric materials having different etch selectivities to etchants;

forming a first interlayer dielectric layer over the combined etch stop layer;

selectively etching the first interlayer dielectric layer to simultaneously define a contact opening extending to the substrate and a field plate opening extending into the combined etch stop layer, the field plate opening having a height less than a height of the contact opening, and the combined etch stop layer vertically separating the field plate opening from the resist protection oxide layer; and

the contact openings and the field plate openings are filled with one or more conductive materials.

18. The method of claim 17, wherein the combined etch stop layer comprises a first dielectric material and a second dielectric material in contact with an upper surface of the first dielectric material.

19. The method of claim 18, wherein the field plate opening extends vertically through the second dielectric material and is laterally separated from the gate structure by the second dielectric material.

20. The method of claim 17, further comprising:

forming a masking layer over the combined etch stop layer; and

the combined etch stop layer and the etch resistant protective oxide layer are etched in accordance with the masking layer.