CN111083075B - Method for processing message by multi-core SoC and SoC applying same - Google Patents
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Abstract
The invention provides a method for processing messages by a multi-core SoC and the SoC applying the method, which solve the problem that the messages sent to a protocol stack are out of order when the SoC shares the messages to a plurality of cores for processing in a round training mode based on weight in the prior art. The method for processing the message by the multi-core SoC comprises the following steps: the network card controller records the serial number of the received message and sends the message to a first core and a second core in the SoC core in a polling mode based on the weight; the first core and the second core insert the received messages into the global linked list according to the corresponding serial numbers and inform the network card controller; and the network card controller determines whether to update the serial number of the message to be processed for processing by a third core in the SoC core according to the serial number of the message inserted into the global linked list.
Description
Technical Field
The invention relates to the technical field of embedded SoC network cards, in particular to a method for processing messages by a multi-core SoC and the SoC using the same.
Background
In a multi-core SoC, a built-in network card controller also generally supports multiple cores. From the receiving direction, the network card supporting multiple cores generally implements multiple packet receiving queues, each packet receiving queue can be bound to a core, and the binding method generally connects the packet receiving interruption of one packet receiving queue to the corresponding core. And once a packet enters a certain packet receiving queue, triggering packet receiving interruption, wherein the packet receiving interruption informs the bound core to process the packet of the packet receiving queue by the core. If the message coming from the network card is distributed to a plurality of packet receiving queues, the message coming from the network card can be processed by a plurality of cores together, and therefore load sharing among the cores is achieved.
There are many schemes for distributing the incoming message from the network card to multiple packet receiving queues, and a general network card controller supports that the same type of message is distributed to the same packet receiving queue according to some characteristics of the message, and this way does not have the problem of disorder, but the load sharing effect of the incoming message from the network card among multiple cores is not good, and in an extreme case, if only one type of message is incoming from the network card, the message is processed on only one core, and the efficiency is low.
In another common scheme, the network card supports that the same type of message is distributed to a plurality of packet receiving queues in a round-robin manner based on weights, which can realize that the same type of message is processed by a plurality of cores, but introduces the problem of disorder at the same time. For example, TCP packets in the same connection are distributed to a plurality of packet receiving queues, but the time for each core to process the packets is uncertain, and packets coming from the network card in sequence are easily sent to the protocol stack out of order, which may cause unnecessary retransmission.
Disclosure of Invention
In view of this, the present invention provides a method for processing a packet by a multi-core SoC and an SoC applying the same.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
a method for processing messages by a multi-core SoC comprises the following steps:
the network card controller records the serial number of a received message and sends the message to a first core and a second core in the SoC core in a polling mode based on weight;
the first core and the second core insert the received messages into the global linked list according to the corresponding serial numbers and inform the network card controller;
and the network card controller determines whether to update the serial number of the message to be processed for processing by a third core in the SoC core according to the serial number of the message inserted into the global linked list.
In an embodiment, the recording, by the network card controller, the sequence number of the received packet specifically includes:
and the network card controller updates a corresponding packet receiving descriptor according to the received message, wherein the packet receiving descriptor comprises a serial number for recording the message serial number.
In one embodiment, the method further comprises:
and if the message serial number recorded by the network card controller reaches the maximum serial number which can be distributed by the global linked list, reversely recording the serial number of the received message from the set initial value.
In one embodiment, the method further comprises:
and if the first core and the second core receive the messages of the reverse recording sequence numbers, inserting the messages of the reverse recording sequence numbers into a reverse global linked list according to the corresponding reverse sequence numbers.
In one embodiment, the method further comprises:
and the network card controller determines whether to reversely update the sequence number of the message to be processed for processing by a third core in the SoC core according to the reverse sequence number of the message inserted into the reverse global linked list.
In one embodiment, the method further comprises:
the first core and the second core determine whether the currently received message is the message with the reverse recorded sequence number or not by comparing the sequence number of the currently received message with the sequence number of the previous message in the packet receiving queue; and/or the presence of a gas in the gas,
and the network card controller determines whether the message serial number inserted in the current global linked list is the reversely recorded message serial number or not according to the serial number of the inserted message in the current global linked list and the serial number of the inserted message in the previous global linked list.
In one embodiment, the first core, the second core and the third core have mutually exclusive access to the global linked list; and/or the presence of a gas in the gas,
the first core and the second core are specifically configured to:
confirming that the message enters a packet receiving queue;
encapsulating the message into skb and finishing the two-layer processing of a network protocol;
inserting the messages encapsulated into skb into a global linked list according to the corresponding sequence numbers;
and informing the network card controller to insert the message of the global linked list.
In an embodiment, the determining, by the network card controller, whether to update the sequence number of the message to be processed according to the sequence number of the message inserted in the global linked list specifically includes:
the network card controller judges whether the sequence number of the message inserted into the global linked list is the minimum sequence number of the message in the global linked list; if so,
the message sequence number to be processed is updated.
In one embodiment, the method further comprises:
the third core takes out the message from the head of the global linked list and judges whether the serial number of the taken out message is smaller than the serial number of the message to be processed; if so,
processing the extracted message; if not, the user can not select the specific application,
returning the extracted message.
The application also provides a multi-core SoC, which at least comprises three cores, and the multi-core SoC applies the method to process messages.
In the implementation mode of the application, the SoC records the serial number of the received message through the network card controller, the multiple cores in the SoC can insert the received message into a global linked list according to the serial number of the received message, and then the network card controller can determine whether to update the serial number of the message to be processed for further processing of the cores according to the serial number of the message inserted into the global linked list, even if the same type of message processing is distributed into the multiple cores in the SoC based on a round-robin training mode, the problem of message disorder sent to a protocol stack caused by the fact that the message processing sequence is inconsistent with the sequence of the message entering the network card controller can not be generated, the processing of the message by the multiple cores in the SoC is called more efficiently, and the efficiency of processing the message in the SoC is guaranteed.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart of a method for processing a message by a multi-core SoC according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a module of the SoC network card controller and a plurality of cores cooperatively processing a message according to an embodiment of the present invention;
fig. 3 is a logic diagram illustrating a network card controller of the SoC and a plurality of cores cooperatively processing a message according to an embodiment of the present invention.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present invention, the technical solution in the embodiment of the present invention will be clearly and completely described below with reference to the drawings in the embodiment of the present invention, and it is obvious that the described embodiment is only a part of the embodiment of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, a specific embodiment of a method for processing a message by a multi-core SoC according to the present application is described. In this embodiment, the method comprises:
s11, the network card controller records the serial number of the received message and sends the message to a first core and a second core in the SoC core in a polling mode based on the weight.
In the SoC based on the technical solution of the present application, the number of cores included in the SoC may be selected according to different specific applications, in a typical embodiment, the number of cores included in the SoC is set to be at least three, and in some more embodiments, the number of cores included in the SoC may also be set to be four, eight, and the like. For simplicity of description, the following description will be made in a manner that three cores in the SoC cooperate to process a packet, but such an implementation should not be construed as limiting the scope of the present application.
In this embodiment, the network card controller updates the corresponding packet receiving descriptor according to the received packet, where the packet receiving descriptor includes a sequence number for recording a sequence number of the packet. Specifically, in the packet receiving descriptor generated by the network card, for example, a 64-bit field is added to record the sequence number of the received packet.
When the network card controller allocates the serial number to the received message, if the allocable maximum value is reached, the network card controller needs to record the serial number of the received message in a reverse way from the set initial value again. The maximum assignable value is associated with a global linked list mentioned below, and when the message sequence number recorded by the network card controller reaches the maximum assignable sequence number of the global linked list, it is considered that the sequence number of the received message needs to be recorded in a reversed manner.
In an embodiment, the sequence numbers assigned to the messages may all start from 0, that is, the initial value is set to 0.
And S12, the first core and the second core insert the received messages into the global linked list according to the corresponding sequence numbers and inform the network card controller.
As a global linked list, all cores in the SoC are visible to the global linked list, and all cores in the SoC have exclusive access to the global linked list so as to ensure the order of inserting and reading messages. Specifically, the first core and the second core are configured to: firstly, confirming that a message enters a packet receiving queue, then encapsulating the message into skb (Structsk _ buffer, a buffer area for receiving and sending packets in a TCP/IP stack), and finishing the two-layer processing of a network protocol; and then inserting the messages encapsulated into the skb into the global linked list according to the corresponding sequence numbers, and finally informing the network card controller of inserting the messages of the global linked list.
Correspondingly, if the first core and the second core receive the message of the reverse recording sequence number, the message of the reverse recording sequence number is inserted into the reverse global linked list according to the corresponding reverse sequence number.
In the specific determination, the first core and the second core determine whether the currently received packet is the packet with the reverse recorded sequence number by comparing the sequence number of the currently received packet with the sequence number of the previous packet in the packet receiving queue. For example, the maximum assignable sequence number of the global linked list is 10000, the sequence number of the previous message in the packet receiving queue is 9950, and the sequence number of the currently received message is 10, then the core of the SoC may determine that the sequence number of the message is inverted, process and encapsulate the sequence number, and then insert the inverted global linked list. Of course, when the sequence number of the message is inverted again, the SoC core will insert the received message into the initial global linked list again.
In this embodiment, the first core and the second core may also perform some driving bottom layer processing on the received packet, so as to reduce the burden of a subsequent third core on processing the packet.
And S13, the network card controller determines whether to update the serial number of the next message to be processed for processing by a third core in the SoC core according to the serial number of the inserted message in the global linked list.
Specifically, the network card controller judges whether the sequence number of the message inserted into the global linked list is the minimum sequence number of the message in the global linked list; if yes, updating the message serial number to be processed and informing the third core. Therefore, the network card controller can inform the third core of the message with the minimum sequence number updated in the global linked list in real time, so that the third core can process the message with the minimum sequence number at the current moment, and the orderliness of the processed message sent into the protocol stack is ensured.
Correspondingly, the network card controller also determines whether the message serial number inserted in the current global linked list is the reversely recorded message serial number according to the serial number of the inserted message in the current global linked list and the serial number of the inserted message in the previous global linked list. If so, the network card controller determines whether to reversely update the sequence number of the message to be processed for processing by a third core in the SoC core according to the reverse sequence number of the inserted message in the reverse global linked list. The method for determining the sequence number of the message to be processed by reverse updating is similar to the above, and whether the sequence number of the message to be processed by reverse updating inserted in the reverse global linked list is the minimum sequence number of the message in the reverse global linked list is also determined by comparing, and if yes, corresponding reverse updating is carried out.
The third core is responsible for taking out the message from the head of the global linked list and judging whether the serial number of the taken out message is smaller than the serial number of the message to be processed; if so, processing the taken message; if not, returning the taken message. Similarly, when the third core reverses the head of the global linked list to take out the packet, the above determination process is also required to be performed, so as to determine the processing policy for the packet.
The scheme of the above embodiment is decomposed into two layers of SoC network card controller and software adaptation of each core and network card controller in SoC, so as to further describe the scheme of the present application.
The SoC network card controller layer, refer to fig. 2.
And a sequence number is added to the packet receiving descriptor of the SoC network card controller and used for recording the sequence number of the message, wherein the sequence number is a global sequence number. The packet receiving descriptor is used for describing information of the received packet, such as the address of the stored packet, the length of the packet, and the like.
After receiving the message, the network card controller records the serial number of the message and writes the serial number into a packet receiving descriptor corresponding to the message. And then distributing the messages to each message receiving queue by a weight-based round-robin scheme, and informing the corresponding core to process the messages.
In addition, the network card also needs to maintain the minimum sequence number of the message to be processed according to the sequence number of the message which is notified by each core and is already put into the global linked list.
② a software adaptation layer (taking a four-core SoC: core0-core3 as an example), refer to FIG. 3.
First, the processing logic of each core is as follows:
1) the Core0 processing logic is as follows:
c0-1: a message enters a packet receiving queue of core 0;
c0-2: core0 processes a message and encapsulates it into a skb;
c0-3: the message is inserted into a global _ skb _ list linked list, the global _ skb _ list linked list is a global linked list, the core0 to the core3 are visible, and the core0-core3 have exclusive access to the linked list. The storage sequence of the skb in the linked list is consistent with the serial number of the message, and the smaller the serial number of the message is, the closer the serial number is to the head of the linked list;
c0-4: and informing the network card controller that the linked list is inserted into the message of the sequence number.
2) The Core1 processing logic is as follows:
c1-1: a message enters a packet receiving queue of core 1;
c1-2: core1 processes a message and encapsulates it into a skb;
c1-3: the message is inserted into a global _ skb _ list linked list, the global _ skb _ list linked list is a global linked list, the core0 to the core3 are visible, and the core0-core3 have exclusive access to the linked list. The storage sequence of the skb in the linked list is consistent with the serial number of the message, and the smaller the serial number of the message is, the closer the serial number is to the head of the linked list;
c1-4: and informing the network card controller that the linked list is inserted into the message of the sequence number.
3) The Core2 processing logic is as follows:
c2-1: a message enters a packet receiving queue of core 2;
c2-2: core2 processes a message and encapsulates it into a skb;
c2-3: the message is inserted into a global _ skb _ list linked list, the global _ skb _ list linked list is a global linked list, the core0 to the core3 are visible, and the core0-core3 have exclusive access to the linked list. The storage sequence of the skb in the linked list is consistent with the serial number of the message, and the smaller the serial number of the message is, the closer the serial number is to the head of the linked list;
c2-4: and informing the network card controller that the linked list is inserted into the message of the sequence number.
4) The network card controller processing logic is as follows:
n-0: and updating the sequence number of the next message to be processed according to the message sequence numbers which are notified by the Core0, the Core1 and the Core2 and are inserted into the linked list.
N-1: if the sequence number of the message to be processed is updated, Core3 is notified.
5) The Core3 processing logic is as follows:
c3-0: one skb process is fetched from the global _ skb _ list header.
C3-1: and judging whether the sequence number of the skb message is smaller than the sequence number of the message to be processed, if so, immediately processing the message, and if not, directly returning (C3-2).
In the above process, for the inverted global linked list, the linked list global _ skb _ list2 is added to handle the packet inversion. Adding the message into a global _ skb _ list linked list at the beginning, adding the corresponding message into the global _ skb _ list2 once the software judges that the message serial number is reversed, and adding the message into the global _ skb _ list linked list again once the message serial number is reversed again.
The present application also provides a multi-core SoC, which at least includes three cores, and the multi-core SoC applies the method described in the above embodiment to process a packet. Since the improvement of other parts of the SoC is not related here, the above embodiments may be partially or fully referred to with respect to the manner in which the message processing function is implemented, and thus, the details are not described here.
In the implementation mode of the application, the SoC records the serial number of the received message through the network card controller, the multiple cores in the SoC can insert the received message into a global linked list according to the serial number of the received message, and then the network card controller can determine whether to update the serial number of the message to be processed for further processing of the cores according to the serial number of the message inserted into the global linked list, even if the same type of message processing is distributed into the multiple cores in the SoC based on a round-robin training mode, the problem of message disorder sent to a protocol stack caused by the fact that the message processing sequence is inconsistent with the sequence of the message entering the network card controller can not be generated, the processing of the message by the multiple cores in the SoC is called more efficiently, and the efficiency of processing the message in the SoC is guaranteed.
The systems, devices, modules or units illustrated in the above embodiments may be implemented by a computer chip or an entity, or by a product with certain functions.
For convenience of description, the above devices are described as being divided into various modules by functions, and are described separately. Of course, the functionality of the modules may be implemented in the same one or more software and/or hardware implementations in implementing one or more embodiments of the present description.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
As will be appreciated by one skilled in the art, embodiments of one or more embodiments of the present description may be provided as a method, system, or computer program product. Accordingly, one or more embodiments of the present description may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, one or more embodiments of the present description may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
One or more embodiments of the present description may be described in the general context of computer-executable instructions, such as program modules, being executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types. One or more embodiments of the specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices that are linked through a communications network. In a distributed computing environment, program modules may be located in both local and remote computer storage media including memory storage devices.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.
Claims (7)
1. A method for processing a message by a multi-core SoC is characterized by comprising the following steps:
the network card controller records the serial number of a received message and sends the message to a first core and a second core in the SoC core in a polling mode based on weight;
the first core and the second core insert the received messages into the global linked list according to the corresponding serial numbers and inform the network card controller;
the network card controller determines whether to update the serial number of the message to be processed for processing by a third core in the SoC core according to the serial number of the message inserted into the global linked list;
if the message serial number recorded by the network card controller reaches the maximum serial number which can be distributed by the global linked list, reversely recording the serial number of the received message from the set initial value;
if the first core and the second core receive the messages of the reverse recording sequence numbers, inserting the messages of the reverse recording sequence numbers into a reverse global linked list according to the corresponding reverse sequence numbers;
and the network card controller determines whether to reversely update the sequence number of the message to be processed for processing by a third core in the SoC core according to the reverse sequence number of the message inserted into the reverse global linked list.
2. The method for processing a message by a multi-core SoC according to claim 1, wherein the recording, by the network card controller, the sequence number of the received message specifically comprises:
and the network card controller updates a corresponding packet receiving descriptor according to the received message, wherein the packet receiving descriptor comprises a serial number for recording the message serial number.
3. The method for processing packets in a multi-core SoC of claim 1, wherein the method further comprises:
the first core and the second core determine whether the currently received message is the message with the reverse recorded sequence number or not by comparing the sequence number of the currently received message with the sequence number of the previous message in the packet receiving queue; and/or the presence of a gas in the gas,
and the network card controller determines whether the message serial number inserted in the current global linked list is the reversely recorded message serial number or not according to the serial number of the inserted message in the current global linked list and the serial number of the inserted message in the previous global linked list.
4. The method for processing packets by a multi-core SoC of claim 1, wherein the first core, the second core and the third core have mutually exclusive access to the global linked list; and/or the presence of a gas in the gas,
the first core and the second core are specifically configured to:
confirming that the message enters a packet receiving queue;
encapsulating the message into skb and finishing the two-layer processing of a network protocol;
inserting the messages encapsulated into skb into a global linked list according to the corresponding sequence numbers;
and informing the network card controller to insert the message of the global linked list.
5. The method for processing a packet in a multi-core SoC according to claim 1, wherein the network card controller determines whether to update the serial number of the packet to be processed according to the serial number of the packet inserted into the global linked list, and specifically includes:
the network card controller judges whether the sequence number of the message inserted into the global linked list is the minimum sequence number of the message in the global linked list; if so,
the message sequence number to be processed is updated.
6. The method for processing packets in the multi-core SoC of claim 5, wherein the method further comprises:
the third core takes out the message from the head of the global linked list and judges whether the serial number of the taken out message is smaller than the serial number of the message to be processed; if so,
processing the extracted message; if not, the user can not select the specific application,
returning the extracted message.
7. A multi-core SoC comprising at least three cores, wherein the multi-core SoC applies the method of any of claims 1 to 6 to process a message.
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Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101013383A (en) * | 2007-02-13 | 2007-08-08 | 杭州华为三康技术有限公司 | System and method for implementing packet combined treatment by multi-core CPU |
| CN101072176A (en) * | 2007-04-02 | 2007-11-14 | 华为技术有限公司 | Report processing method and system |
| CN101771595A (en) * | 2008-12-29 | 2010-07-07 | 华为技术有限公司 | Method and device for preserving order of message |
| CN101795236A (en) * | 2010-03-31 | 2010-08-04 | 成都市华为赛门铁克科技有限公司 | Report sequence preservation method and device |
| CN102055649A (en) * | 2009-10-29 | 2011-05-11 | 成都市华为赛门铁克科技有限公司 | Method, device and system for treating messages of multi-core system |
| CN103888449A (en) * | 2014-03-05 | 2014-06-25 | 亿赞普(北京)科技有限公司 | Method and device for packet reassembly |
| CN105337896A (en) * | 2014-07-25 | 2016-02-17 | 华为技术有限公司 | Message processing method and device |
| CN105630731A (en) * | 2015-12-24 | 2016-06-01 | 曙光信息产业(北京)有限公司 | Network card data processing method and device in multi-CPU (Central Processing Unit) environment |
| CN105871739A (en) * | 2016-06-17 | 2016-08-17 | 华为技术有限公司 | Method for processing messages and computing equipment |
| CN105939297A (en) * | 2015-10-26 | 2016-09-14 | 杭州迪普科技有限公司 | TCP message reassembling method and TCP message reassembling device |
| CN107733813A (en) * | 2016-08-12 | 2018-02-23 | 中兴通讯股份有限公司 | Message forwarding method and device |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7433955B2 (en) * | 2002-11-21 | 2008-10-07 | International Business Machines Corporation | Apparatus and method for processing sequenced records across multiple network connections |
| CN102868635B (en) * | 2012-08-24 | 2016-02-17 | 汉柏科技有限公司 | The message order-preserving method of Multi-core and system |
| US11012367B2 (en) * | 2018-03-30 | 2021-05-18 | Intel IP Corporation | Technologies for managing TCP/IP packet delivery |
| CN109543429A (en) * | 2018-11-21 | 2019-03-29 | 武汉思普崚技术有限公司 | A kind of double linked list guard method and device suitable for it is expected link |
-
2019
- 2019-12-20 CN CN201911327942.XA patent/CN111083075B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101013383A (en) * | 2007-02-13 | 2007-08-08 | 杭州华为三康技术有限公司 | System and method for implementing packet combined treatment by multi-core CPU |
| CN101072176A (en) * | 2007-04-02 | 2007-11-14 | 华为技术有限公司 | Report processing method and system |
| CN101771595A (en) * | 2008-12-29 | 2010-07-07 | 华为技术有限公司 | Method and device for preserving order of message |
| CN102055649A (en) * | 2009-10-29 | 2011-05-11 | 成都市华为赛门铁克科技有限公司 | Method, device and system for treating messages of multi-core system |
| CN101795236A (en) * | 2010-03-31 | 2010-08-04 | 成都市华为赛门铁克科技有限公司 | Report sequence preservation method and device |
| CN103888449A (en) * | 2014-03-05 | 2014-06-25 | 亿赞普(北京)科技有限公司 | Method and device for packet reassembly |
| CN105337896A (en) * | 2014-07-25 | 2016-02-17 | 华为技术有限公司 | Message processing method and device |
| CN105939297A (en) * | 2015-10-26 | 2016-09-14 | 杭州迪普科技有限公司 | TCP message reassembling method and TCP message reassembling device |
| CN105630731A (en) * | 2015-12-24 | 2016-06-01 | 曙光信息产业(北京)有限公司 | Network card data processing method and device in multi-CPU (Central Processing Unit) environment |
| CN105871739A (en) * | 2016-06-17 | 2016-08-17 | 华为技术有限公司 | Method for processing messages and computing equipment |
| CN107733813A (en) * | 2016-08-12 | 2018-02-23 | 中兴通讯股份有限公司 | Message forwarding method and device |
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