CN111082783A

CN111082783A - Fully-differential static logic ultra-high-speed D trigger

Info

Publication number: CN111082783A
Application number: CN201911354499.5A
Authority: CN
Inventors: 唐枋; 黄天聪; 李志鹏; 李润林
Original assignee: Chongqing University
Current assignee: Chongqing University
Priority date: 2019-12-25
Filing date: 2019-12-25
Publication date: 2020-04-28

Abstract

The invention discloses a fully-differential static logic ultra-high-speed D trigger in the technical field of integrated circuit design, which comprises a dip differential signal input module and a ckop differential signal output module which are correspondingly arranged, and a din differential signal input module and a ckon differential signal output module which are correspondingly arranged, wherein the connecting ends of the dip differential signal input module and the ckop differential signal output module and the connecting ends of the din differential signal input module and the ckon differential signal output module are sequentially connected with a transmission gate module, a first reverser module and a second reverser module, and the transmission gate module is connected with a differential clock signal module.

Description

Fully-differential static logic ultra-high-speed D trigger

Technical Field

The invention relates to the technical field of integrated circuit design, in particular to a fully differential static logic ultra-high-speed D trigger.

Background

The traditional flip-flop has only one clock terminal, one signal input terminal, one reset terminal and one output terminal. As shown in fig. 1. It is composed of three inverters and two transmission gates. When the pulse input ckn is high, the lower transmission gate is turned on, so the flip-flop is transparent and the input d is copied to the output q. At this stage, the feedback loop is open because the upper transmission gate is open. The size of the transistor is therefore not important for achieving correct function. But from a power perspective, the number of transistors driven by the clock is an important metric because the activity factor of the clock is 1. From this point of view, the flip-flop is not efficient, and the circuit structure is implemented with a smic40nm process, with parameters both at minimum L and W. And then carrying out frequency simulation on the FO4 load, comparing the simulated output waveform with 5G when the frequency is 4G, and showing that when the frequency goes to 5G, the waveform has serious errors and almost disappears when the level is low, namely, the frequency of the traditional structure can only realize 4G, and the speed is very limited.

The main defects of the existing trigger device are that the output wave bounce frequency is too low, the speed is too slow, and the trigger can still normally operate under ultrahigh frequency, which is inconvenient to realize.

Based on this, the present invention designs a fully differential static logic ultra high speed D flip-flop to solve the above problems.

Disclosure of Invention

The present invention is directed to a fully differential static logic super high speed D flip-flop, so as to solve the problem of the prior art subject name + technical problem mentioned in the background above.

In order to achieve the purpose, the invention provides the following technical scheme: a fully-differential static logic ultra-high-speed D trigger comprises a dip differential signal input module and a ckop differential signal output module which are correspondingly arranged, and a din differential signal input module and a ckon differential signal output module which are correspondingly arranged, wherein the connecting ends of the dip differential signal input module and the ckop differential signal output module and the connecting ends of the din differential signal input module and the ckon differential signal output module are sequentially connected with a transmission gate module, a first reverser module and a second reverser module, and the transmission gate module is connected with a differential clock signal module;

the dip differential signal input module and the din differential signal input module are used for inputting signals;

the differential clock signal module is used for controlling the signal input of the dip differential signal input module or the din differential signal input module;

the transmission gate module is used for transmitting an input signal to a first node;

the first inverter module is used for transmitting a transmission signal to a second node;

the second inverter module is used for transmitting the signal obtained by the transmission gate module to the ckop differential signal output module or the ckon differential signal output module;

and the ckop differential signal output module and the ckon differential signal output module are used for outputting the shaped waveform signal from the second node.

Preferably, the differential clock signal module includes ckn differential clock signal module and ckp differential clock signal module which are arranged corresponding to each other.

Preferably, the ckn differential clock signal block and the ckp differential clock signal block are both level triggered, and the ckn differential clock signal block and the ckp differential clock signal block are high and low level with each other.

Preferably, the signal frequency of the dip differential signal input module and the din differential signal input module is half of the signal frequency of the ckn differential clock signal module and the ckp differential clock signal module.

Preferably, a first node corresponding to the dip differential signal input module is connected to a second node corresponding to the din differential signal input module, and the second node corresponding to the dip differential signal input module is connected to the first node corresponding to the din differential signal input module.

Compared with the prior art, the invention has the beneficial effects that: compared with the traditional home, the simulation platform of the circuit is realized by the smic40nm process, so that the trigger can still normally run under ultrahigh frequency, and the speed of the circuit is greatly improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a prior art flip-flop circuit;

FIG. 2 is a schematic diagram of a flip-flop circuit of the present invention;

FIG. 3 is a simulation platform diagram of the circuit of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 2-3, the present invention provides a technical solution: a fully-differential static logic ultra-high-speed D trigger comprises a dip differential signal input module and a ckop differential signal output module which are correspondingly arranged, and a din differential signal input module and a ckon differential signal output module which are correspondingly arranged, wherein the connecting ends of the dip differential signal input module and the ckop differential signal output module and the connecting ends of the din differential signal input module and the ckon differential signal output module are sequentially connected with a transmission gate module, a first reverser module and a second reverser module, and the transmission gate module is connected with a differential clock signal module; the dip differential signal input module and the din differential signal input module are used for inputting signals; the differential clock signal module is used for controlling the signal input of the dip differential signal input module or the din differential signal input module; the transmission gate module is used for transmitting an input signal to a first node; the first inverter module is used for transmitting a transmission signal to a second node; the second inverter module is used for transmitting the signal obtained by the transmission gate module to the ckop differential signal output module or the ckon differential signal output module; and the ckop differential signal output module and the ckon differential signal output module are used for outputting the shaped waveform signal from the second node.

The differential clock signal module comprises an ckn differential clock signal module and a ckp differential clock signal module which are arranged correspondingly; it should be explained that, as shown in fig. 2, the dip differential signal input module and the din differential signal input module are a pair of differential signal input ends, and according to the nyquist sampling theorem, when the ckn differential clock signal module is at a high level and the ckp differential clock signal module is at a low level, the dip differential signal input module will send signals to the first node N1 through the first transmission gate module formed by NM1 and PM1, and then send signals of the first node N1 to the second node N2 through the first inverter module formed by PM2 and NM2, at this time, the din differential signal input module will send signals to the second node N2 through the corresponding transmission gate, and the two signal lines are connected together, so that the waveform can be shaped, the rising edge and the falling edge are steeper, and the phases of the differential output signals can be kept consistent; the signal at the second node N2 is further transmitted to the output terminal ckop differential signal output module through a second inverter formed by PM3 and NM 3. Similarly, the din differential signal input module can also transmit to the ckon differential signal output module under the control of ckn and ckp clocks when serving as input signals.

In a further embodiment, the ckn difference clock signal module and the ckp difference clock signal module are both level triggered, and the ckn difference clock signal module and the ckp difference clock signal module are high and low each other; as shown in fig. 2, ckn differential clock signal module and ckp differential clock signal module are respectively connected to two ends of the pass gate formed by NM1 and PM1 to realize level triggering.

In a further embodiment, the signal frequency of the dip differential signal input module and the din differential signal input module is half of the signal frequency of the ckn differential clock signal module and the ckp differential clock signal module, and the frequency of the differential signals is set to be half of the intermediate frequency, so that the rapid transmission of the simulation signals can be facilitated.

In a further embodiment, a first node corresponding to the dip differential signal input module is connected to a second node corresponding to the din differential signal input module, and the second node corresponding to the dip differential signal input module is connected to the first node corresponding to the din differential signal input module; signals can be conveniently input at any end of the dip differential signal input module or the din differential signal input module, and signal output is obtained at the connecting end of the corresponding ckon differential signal output module or the corresponding ckop differential signal output module.

It should be noted that, as shown in fig. 3, the circuit is realized by a smic40nm process, the parameters of the circuit are frequently and repeatedly debugged, and the circuit can realize super high speed under the action of the width-length ratio of 40nm for all L. The circuit of the present invention is greatly improved in speed over the conventional configuration in the case of a simulated waveform with the flip-flop band FO4 loaded at a frequency of 26G.

In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The preferred embodiments of the invention disclosed above are intended to be illustrative only. The preferred embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. a fully differential static logic ultra-high-speed D flip-flop, is characterized in that: comprise the dip differential signal input module and the ckop differential signal output module of the corresponding setting and the din differential signal input module and the ckon differential signal output module of the corresponding setting, so The connection terminals of the dip differential signal input module and the ckop differential signal output module and the connection terminals of the din differential signal input module and the ckon differential signal output module are sequentially connected with a transmission gate module, a first inverter module and a second inverter. a module, a differential clock signal module is connected to the transmission gate module;

The dip differential signal input module and the din differential signal input module are used for signal input;

The differential clock signal module is used to control the signal input of the dip differential signal input module or the din differential signal input module;

The transmission gate module is used to transmit the input signal to the first node;

the first inverter module, for transmitting the transmission signal to the second node;

The second inverter module is used to transmit the signal obtained by the transmission gate module to the ckop differential signal output module or the ckon differential signal output module;

The ckop differential signal output module and the ckon differential signal output module are used for outputting the shaped waveform signal from the second node.

2 . The fully differential static logic ultra-high-speed D flip-flop according to claim 1 , wherein the differential clock signal module comprises a ckn differential clock signal module and a ckp differential clock signal module which are arranged corresponding to each other. 3 .

3. The fully differential static logic ultra-high-speed D flip-flop according to claim 2, wherein the ckn differential clock signal module and the ckp differential clock signal module are both level-triggered, and the ckn differential clock The signal module and the ckp differential clock signal module are mutually high and low levels.

4. a kind of fully differential static logic ultra-high-speed D flip-flop according to claim 1, is characterized in that: the signal frequency of described dip differential signal input module and din differential signal input module are ckn differential clock signal module and ckp Half of the signal frequency of the differential clock signal block.

5. A fully differential static logic ultra-high-speed D flip-flop according to claim 1, wherein the first node corresponding to the dip differential signal input module and the first node corresponding to the din differential signal input module The two nodes are connected, and the second node corresponding to the dip differential signal input module is connected to the first node corresponding to the din differential signal input module.