CN111081633A - Preparation method of array substrate and array substrate - Google Patents
Preparation method of array substrate and array substrate Download PDFInfo
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- CN111081633A CN111081633A CN202010015182.5A CN202010015182A CN111081633A CN 111081633 A CN111081633 A CN 111081633A CN 202010015182 A CN202010015182 A CN 202010015182A CN 111081633 A CN111081633 A CN 111081633A
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- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
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- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
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- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/421—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
- H10D86/423—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
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- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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Abstract
本申请提供一种阵列基板的制备方法及阵列基板，该制备方法包括依次在基板上形成图案化的第一金属层、绝缘层、第一半导体层、第二半导体层和第二金属层，所述第一半导体层的材料为非晶硅或低温多晶硅，所述第二半导体层的材料为金属氧化物或低温多晶硅；其中，位于所述非显示区的所述图案化的第一金属层、所述绝缘层和所述图案化的第二金属层，以及所述图案化的第一半导体层形成GOA驱动电路；位于所述显示区的所述图案化的第一金属层、所述绝缘层和所述图案化的第二金属层，以及所述图案化的第二半导体层形成像素电路。本申请在提高8K 120Hz显示面板像素充电率的同时，提高了GOA驱动电路中薄膜晶体管器件的稳定性。
The present application provides a method for preparing an array substrate and an array substrate. The preparation method includes sequentially forming a patterned first metal layer, an insulating layer, a first semiconductor layer, a second semiconductor layer and a second metal layer on the substrate, so that the The material of the first semiconductor layer is amorphous silicon or low temperature polysilicon, and the material of the second semiconductor layer is metal oxide or low temperature polysilicon; wherein, the patterned first metal layer, The insulating layer, the patterned second metal layer, and the patterned first semiconductor layer form a GOA driving circuit; the patterned first metal layer, the insulating layer located in the display area A pixel circuit is formed with the patterned second metal layer and the patterned second semiconductor layer. The present application improves the stability of the thin film transistor device in the GOA drive circuit while improving the pixel charging rate of the 8K 120Hz display panel.
Description
Technical Field
The application relates to the technical field of display, in particular to a preparation method of an array substrate and the array substrate.
Background
The GOA (Gate Driver on Array) technology integrates a Gate driving circuit on an Array substrate of a display panel, so that a Gate driving integrated circuit part can be omitted to reduce product cost from both material cost and manufacturing process. With the improvement of the performance of thin film transistors, the GOA technology has been commonly applied to display panels.
At present, in the manufacturing process of an 8K120Hz display panel, a semiconductor layer in a pixel circuit of an array substrate is made of a-Si, and the pixel charging rate of the display panel is low due to low mobility of the a-Si. In addition, when IGZO is used as a material of the semiconductor layer of the GOA driver circuit, the stability of the thin film transistor device in the GOA driver circuit is greatly reduced, which results in a reduction in product yield. Therefore, how to improve the charging rate of the pixel of the 8K120Hz display panel and improve the stability of the thin film transistor device in the GOA driving circuit is an urgent technical problem to be solved.
Disclosure of Invention
The application provides a preparation method of an array substrate and the array substrate, which are used for solving the technical problems that the charging rate of pixels of an existing 8K120Hz display panel is low and the stability of a thin film transistor device in a GOA driving circuit is poor.
The application provides a preparation method of an array substrate, which comprises the following steps:
providing a substrate, wherein the substrate comprises a display area and a non-display area;
forming a patterned first metal layer on the substrate;
forming an insulating layer on the patterned first metal layer;
forming a patterned first semiconductor layer on the part of the insulating layer, which is positioned in the non-display area, wherein the material of the first semiconductor layer is amorphous silicon or low-temperature polycrystalline silicon;
forming a second patterned semiconductor layer on the part of the insulating layer, which is positioned in the display area, wherein the second semiconductor layer is made of metal oxide or low-temperature polysilicon;
forming a patterned second metal layer on the patterned first semiconductor layer and the patterned second semiconductor layer;
the patterned first metal layer, the insulating layer, the patterned second metal layer and the patterned first semiconductor layer which are positioned in the non-display area form a GOA driving circuit; the patterned first metal layer, the insulating layer, the patterned second metal layer and the patterned second semiconductor layer which are positioned in the display area form a pixel circuit.
In the preparation method of the array substrate, the first semiconductor layer is made of amorphous silicon.
In the preparation method of the array substrate, the material of the second semiconductor layer is a metal oxide.
In the method for manufacturing an array substrate of the present application, the step of forming a patterned first semiconductor layer on the portion of the insulating layer located in the non-display area includes:
forming a first semiconductor layer on the insulating layer at the non-display area by using a vapor deposition process;
and etching the first semiconductor layer to form the patterned first semiconductor layer.
In the method for manufacturing an array substrate of the present application, the step of forming a patterned second semiconductor layer on a portion of the insulating layer located in the display region includes:
forming a second semiconductor layer on the part of the insulating layer, which is positioned in the display area, by adopting a vapor deposition process;
and etching the second semiconductor layer to form the patterned second semiconductor layer.
In the method for manufacturing an array substrate of the present application, the step of forming a patterned first metal layer on the substrate includes:
forming a first metal layer on the substrate by adopting a vapor deposition process;
and etching the first metal layer to form a patterned first metal layer, wherein the patterned first metal layer comprises a grid electrode.
In the method for manufacturing an array substrate of the present application, the step of forming a patterned second metal layer on the patterned first semiconductor layer and the patterned second semiconductor layer includes:
forming a second metal layer on the patterned first semiconductor layer and the patterned second semiconductor layer by using a vapor deposition process;
and etching the second metal layer to form a patterned second metal layer, wherein the patterned second metal layer comprises a source electrode and a drain electrode.
In the method for manufacturing an array substrate of the present application, after the step of forming a patterned second metal layer on the patterned first semiconductor layer and the patterned second semiconductor layer, the method further includes:
forming a protective layer on the patterned second metal layer, the protective layer covering the first semiconductor layer and the second semiconductor layer.
The present application further provides an array substrate applied to a display panel, which includes:
a substrate including a display region and a non-display region;
a first metal layer disposed on the substrate;
an insulating layer disposed on the first metal layer;
the first semiconductor layer is arranged on the part, located in the non-display area, of the insulating layer, and the first semiconductor layer is made of amorphous silicon or low-temperature polycrystalline silicon;
the second semiconductor layer is arranged on the part, located in the display area, of the insulating layer, and the material of the second semiconductor layer is metal oxide or low-temperature polycrystalline silicon;
a second metal layer disposed on the first semiconductor layer and the second semiconductor layer;
a protective layer disposed on the second metal layer and covering the first semiconductor layer and the second semiconductor layer;
the first metal layer, the insulating layer, the second metal layer and the first semiconductor layer which are positioned in the non-display area form a GOA driving circuit; the first metal layer, the insulating layer and the second metal layer located in the display area, and the second semiconductor layer form a pixel circuit.
In the array substrate of the present application, the first semiconductor layer is made of amorphous silicon;
the material of the second semiconductor layer is metal oxide.
Compared with the preparation method of the array substrate in the prior art, the preparation method of the array substrate provided by the application improves the stability of a thin film transistor device in the GOA drive circuit by forming the first semiconductor layer in the GOA drive circuit, wherein the first semiconductor layer is made of amorphous silicon or low-temperature polycrystalline silicon; and forming a second semiconductor layer in the pixel circuit, wherein the second semiconductor layer is made of metal oxide or low-temperature polysilicon, so that the pixel charging rate of the 8K120Hz display panel is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 2A to 2G are schematic structural diagrams sequentially obtained in steps S101 to S107 in the method for manufacturing an array substrate according to the embodiment of the present application;
fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
In the embodiments of the present application, the first semiconductor layer in the GOA driver circuit is fabricated first, and the second semiconductor layer in the pixel circuit is fabricated later, but the present application is not limited thereto.
Referring to fig. 1, fig. 1 is a schematic flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the present disclosure.
The embodiment of the application provides a preparation method of an array substrate, which comprises the following steps:
step S101: providing a substrate, wherein the substrate comprises a display area and a non-display area;
step S102: forming a patterned first metal layer on the substrate;
step S103: forming an insulating layer on the patterned first metal layer;
step S104: forming a patterned first semiconductor layer on the part of the insulating layer, which is positioned in the non-display area, wherein the material of the first semiconductor layer is amorphous silicon or low-temperature polycrystalline silicon;
step S105: forming a second patterned semiconductor layer on the part of the insulating layer, which is positioned in the display area, wherein the second semiconductor layer is made of metal oxide or low-temperature polysilicon;
step S106: forming a patterned second metal layer on the patterned first semiconductor layer and the patterned second semiconductor layer; the patterned first metal layer, the insulating layer, the patterned second metal layer and the patterned first semiconductor layer which are positioned in the non-display area form a GOA driving circuit; the patterned first metal layer, the insulating layer and the patterned second metal layer which are positioned in the display area, and the patterned second semiconductor layer form a pixel circuit;
step S107: forming a protective layer on the patterned second metal layer, the protective layer covering the first semiconductor layer and the second semiconductor layer.
Therefore, the preparation method of the array substrate improves the stability of a thin film transistor device in the GOA driving circuit by forming the first semiconductor layer in the GOA driving circuit, wherein the first semiconductor layer is made of amorphous silicon or low-temperature polycrystalline silicon; and forming a second semiconductor layer in the pixel circuit, wherein the second semiconductor layer is made of metal oxide or low-temperature polysilicon, so that the pixel charging rate of the 8K120Hz display panel is improved.
The method for manufacturing the array substrate 100 according to the embodiment of the present application will be described in detail below.
Referring to fig. 2A to 2G, fig. 2A to 2G are schematic structural diagrams sequentially obtained from step S101 to step S107 in the method for manufacturing an array substrate according to the embodiment of the present disclosure.
Step S101: a substrate 10 is provided. The substrate 10 includes a display region 10a and a non-display region 10 b.
Please refer to fig. 2A. The substrate 11 may be a rigid substrate, such as a glass substrate. Subsequently, the process proceeds to step S102.
Step S102: a patterned first metal layer 11 is formed on a substrate 10.
Please refer to fig. 2B. It is understood that before the patterned first metal layer 11 is formed, a buffer layer (not shown) may be formed on the substrate 10, and then the first metal layer 11 is formed on the buffer layer.
Further, a first metal layer 11 is formed on the substrate 10 using a vapor deposition process. Specifically, the first metal layer 11 is deposited on the buffer layer by using a physical vapor deposition method.
Next, the first metal layer is etched to form a patterned first metal layer 11. Wherein the patterned first metal layer 11 comprises a gate.
Specifically, the first metal layer 11 is etched by a wet etching process to form the patterned first metal layer 11. In the embodiment of the present application, the patterned first metal layer 11 further includes metal traces (not shown), which are not described herein again. Subsequently, the process proceeds to step S103.
Step S103: an insulating layer 12 is formed on the patterned first metal layer 11.
Please refer to fig. 2C. Specifically, an inorganic material is deposited on the patterned first metal layer 11 using a chemical vapor deposition method to form the insulating layer 12. Subsequently, the process proceeds to step S104.
Step S104: a patterned first semiconductor layer 13 is formed on a portion of the insulating layer 12 located in the non-display region 10 b.
Please refer to fig. 2D. Specifically, the first semiconductor layer 13 is formed on the portion of the insulating layer 12 located in the non-display region 10b using a vapor deposition process.
Further, a first semiconductor layer 13 is formed on a portion of the insulating layer 12 located in the non-display region 10b by using a chemical vapor deposition method, and then, the first semiconductor layer 13 is subjected to an etching process to form the patterned first semiconductor layer 13.
Optionally, the material of the first semiconductor layer 13 is amorphous silicon or low temperature polysilicon.
In the embodiment of the present application, the material of the first semiconductor layer 13 is amorphous silicon. Subsequently, the process proceeds to step S105.
Step S105: a patterned second semiconductor layer 14 is formed on the portion of the insulating layer 12 located in the display region 10 a.
Please refer to fig. 2E. Specifically, the second semiconductor layer 14 is formed on a portion of the insulating layer 12 located in the display region 10a using a vapor deposition process.
Further, a second semiconductor layer 14 is formed on the portion of the insulating layer 12 in the display region 10a by using a chemical vapor deposition method, and then, the second semiconductor layer 14 is etched to form a patterned second semiconductor layer 14.
Optionally, the material of the second semiconductor layer 14 is metal oxide or low temperature polysilicon.
In the embodiment of the present application, the material of the second semiconductor layer 14 is a metal oxide. Specifically, the metal oxide is indium gallium zinc oxide.
In some embodiments, the metal oxide is indium tin zinc oxide, indium gallium tin zinc oxide, or the like. Subsequently, the process proceeds to step S106.
Step S106: a patterned second metal layer 15 is formed on the patterned first semiconductor layer 13 and the patterned second semiconductor layer 14.
Please refer to fig. 2F. Wherein a second metal layer 15 is formed on the patterned first semiconductor layer 13 and the patterned second semiconductor layer 14 using a vapor deposition process. Specifically, the second metal layer 15 is formed on the patterned first semiconductor layer 13 and the patterned second semiconductor layer 14 using a physical vapor deposition method.
Next, the second metal layer 15 is etched to form a patterned second metal layer 15, and the patterned second metal layer 15 includes a source electrode 15a and a drain electrode 15 b.
Specifically, the second metal layer 15 is etched by a wet etching process to form the patterned second metal layer 15. In the embodiment of the present application, the patterned second metal layer 12 further includes a metal trace (not shown), which is not described herein again.
Further, in the embodiment of the present application, the patterned first metal layer 11, the insulating layer 12, the patterned second metal layer 15, and the patterned first semiconductor layer 13 in the non-display area 10b form a GOA driving circuit. The patterned first metal layer 11, the insulating layer 12, and the patterned second metal layer 15, and the patterned second semiconductor layer 14 at the display region 10a form a pixel circuit.
It can be understood that, since the driving voltage required by the GOA driving circuit is relatively complex, when amorphous silicon is used as the material of the first semiconductor layer 13 in the GOA driving circuit, the stability of the thin film transistor device in the GOA driving circuit can be improved. In addition, since the mobility of the metal oxide semiconductor is high, when the indium gallium zinc oxide is used as the material of the second semiconductor layer 14 in the pixel circuit, the stability of the thin film transistor device is high, which is favorable for improving the pixel charging rate of the display panel. Subsequently, the process proceeds to step S107.
Step S107: a protective layer 16 is formed on the patterned second metal layer 15, and the protective layer 16 covers the first semiconductor layer 13 and the second semiconductor layer 14.
Please refer to fig. 2G. Specifically, an inorganic material is deposited on the second metal layer 15 using a chemical vapor deposition method to form the protective layer 16.
In addition, in some embodiments, a pixel electrode layer may also be formed on the protective layer 16.
Specifically, a portion of the protection layer 16 above the drain electrode 15b is patterned by a photolithography process to form a via hole corresponding to the drain electrode 15b, which exposes the drain electrode 15 b.
Next, a conductive material is deposited on the surface of the protective layer 16 by a vapor deposition method to form a pixel electrode layer. Then, a patterned pixel electrode layer is formed through a photolithography process to form at least a pixel electrode. The pixel electrode is electrically connected to the drain electrode 15b through a via hole in the protective layer 16.
Thus, the method for manufacturing the array substrate 100 according to the embodiment of the present application is completed.
According to the preparation method of the array substrate 100 provided by the embodiment of the application, the first semiconductor layer 13 is formed in the GOA driving circuit, and the material of the first semiconductor layer 13 is amorphous silicon or low-temperature polycrystalline silicon, so that the stability of a thin film transistor device in the GOA driving circuit is improved; and forming the second semiconductor layer 14 in the pixel circuit, wherein the material of the second semiconductor layer 14 is metal oxide or low-temperature polysilicon, thereby improving the pixel charging rate of the 8K120Hz display panel.
Referring to fig. 3, fig. 3 is a schematic structural diagram of an array substrate 200 according to an embodiment of the present disclosure.
The embodiment of the present application provides an array substrate 200, which includes a substrate 20, a first metal layer 21, an insulating layer 22, a first semiconductor layer 23, a second semiconductor layer 24, a second metal layer 25, and a protective layer 26. A buffer layer (not shown) is further included between the substrate 20 and the first metal layer 21.
Specifically, the substrate 20 includes a display region 20a and a non-display region 20 b. The first metal layer 21 is disposed on the substrate 20.
The insulating layer 22 is disposed on the first metal layer 21.
The first semiconductor layer 23 is disposed on a portion of the insulating layer 22 located in the non-display region 20 b. The material of the first semiconductor layer 23 is amorphous silicon or low temperature polysilicon.
The second semiconductor layer 24 is disposed on a portion of the insulating layer 22 located at the display region 20 a. The material of the second semiconductor layer 24 is metal oxide or low temperature polysilicon.
The second metal layer 25 is disposed on the first semiconductor layer 23 and the second semiconductor layer 24.
The protective layer 26 is disposed on the second metal layer 25 and covers the first semiconductor layer 23 and the second semiconductor layer 24.
The first metal layer 21, the insulating layer 22, the second metal layer 25 and the first semiconductor layer 23 in the non-display area 20b form a GOA driving circuit. The first metal layer 21, the insulating layer 22, and the second metal layer 25 located in the display region 20a, and the second semiconductor layer 24 form a pixel circuit.
Therefore, the first semiconductor layer 23 is arranged in the GOA driver circuit, and the material of the first semiconductor layer 23 is amorphous silicon or low-temperature polysilicon, so that the stability of the thin film transistor device in the GOA driver circuit is improved; and the second semiconductor layer 24 is arranged in the pixel circuit, and the material of the second semiconductor layer 24 is metal oxide or low-temperature polysilicon, so that the pixel charging rate of the 8K120Hz display panel is improved.
Optionally, the material of the first semiconductor layer 23 is amorphous silicon, and the material of the second semiconductor layer 24 is metal oxide.
Further, in the embodiment of the present application, the material of the second semiconductor layer 24 is indium gallium zinc oxide.
It is understood that in some embodiments, a pixel electrode layer is also disposed on the protective layer 26. The pixel electrode layer includes a pixel electrode. The pixel electrode is electrically connected to the drain electrode 25b through a via hole in the protective layer 26.
Compared with the preparation method of the array substrate in the prior art, the preparation method of the array substrate provided by the application improves the stability of a thin film transistor device in the GOA drive circuit by forming the first semiconductor layer in the GOA drive circuit, wherein the first semiconductor layer is made of amorphous silicon or low-temperature polycrystalline silicon; and forming a second semiconductor layer in the pixel circuit, wherein the second semiconductor layer is made of metal oxide or low-temperature polysilicon, so that the pixel charging rate of the 8K120Hz display panel is improved.
The foregoing provides a detailed description of embodiments of the present application, and the principles and embodiments of the present application have been described herein using specific examples, which are presented solely to aid in the understanding of the present application. Meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
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| CN115312543A (en) * | 2022-08-31 | 2022-11-08 | 北海惠科光电技术有限公司 | Array substrate, manufacturing method and display panel |
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