CN109887968A - A display panel and method of making the same - Google Patents
A display panel and method of making the same Download PDFInfo
- Publication number
- CN109887968A CN109887968A CN201910136685.5A CN201910136685A CN109887968A CN 109887968 A CN109887968 A CN 109887968A CN 201910136685 A CN201910136685 A CN 201910136685A CN 109887968 A CN109887968 A CN 109887968A
- Authority
- CN
- China
- Prior art keywords
- layer
- display panel
- semiconductor layer
- gate
- drain electrode
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 74
- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- 239000002184 metal Substances 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 22
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 19
- 150000004706 metal oxides Chemical group 0.000 claims abstract description 19
- 239000000463 material Substances 0.000 claims abstract description 17
- 238000002161 passivation Methods 0.000 claims description 16
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 8
- 239000004973 liquid crystal related substance Substances 0.000 claims description 7
- 238000000059 patterning Methods 0.000 abstract 1
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 12
- 238000010586 diagram Methods 0.000 description 7
- 238000002360 preparation method Methods 0.000 description 6
- 239000011787 zinc oxide Substances 0.000 description 6
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 229910052733 gallium Inorganic materials 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- 229910052738 indium Inorganic materials 0.000 description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- NJWNEWQMQCGRDO-UHFFFAOYSA-N indium zinc Chemical compound [Zn].[In] NJWNEWQMQCGRDO-UHFFFAOYSA-N 0.000 description 1
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
- TYHJXGDMRRJCRY-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) tin(4+) Chemical compound [O-2].[Zn+2].[Sn+4].[In+3] TYHJXGDMRRJCRY-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
Landscapes
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
本发明提供一种显示面板及其制作方法，该方法包括：在衬底基板上制作第一栅极和第二栅极；在所述第一栅极、所述第二栅极以及未被所述第一栅极和所述第二栅极覆盖的衬底基板上制作绝缘层；在位于所述显示区域的绝缘层上形成第一半导体层以及在位于所述栅极驱动区域的绝缘层上形成第二半导体层；所述第二半导体层的材料为金属氧化物；在所述第一半导体层和所述第二半导体层上制作第二金属层，对所述第二金属层进行图案化处理，以使位于所述显示区域的第二金属层形成第一源极和第一漏极以及位于所述栅极驱动区域的第二金属层形成第二源极和第二漏极。本发明的显示面板及其制作方法，能够减小显示面板的边框。
The present invention provides a display panel and a manufacturing method thereof. The method includes: fabricating a first gate and a second gate on a base substrate; forming an insulating layer on the base substrate covered by the first gate and the second gate; forming a first semiconductor layer on the insulating layer in the display region and on the insulating layer in the gate driving region forming a second semiconductor layer; the material of the second semiconductor layer is metal oxide; making a second metal layer on the first semiconductor layer and the second semiconductor layer, and patterning the second metal layer processing, so that the second metal layer located in the display area forms the first source electrode and the first drain electrode and the second metal layer located in the gate driving area forms the second source electrode and the second drain electrode. The display panel and the manufacturing method thereof of the present invention can reduce the frame of the display panel.
Description
[technical field]
The present invention relates to field of display technology, more particularly to a kind of display panel and preparation method thereof.
[background technique]
Due to the electrical high stability of amorphous silicon, and it is widely used in TV and mobile device manufacture.It is existing non-
The display panel of crystal silicon material production generally includes display area and gate driving circuit region, and gate driving circuit region is provided with grid drive
Dynamic circuit, gate driving circuit include driving thin film transistor (TFT).
However, the electron mobility due to amorphous silicon is smaller, required to meet driving, it usually needs by driving circuit
Size makes larger, thus causes the frame of display panel larger, cannot achieve narrow frame.
Therefore, it is necessary to a kind of display panel and preparation method thereof be provided, to solve the problems of prior art.
[summary of the invention]
The purpose of the present invention is to provide a kind of display panels and preparation method thereof, can reduce the frame of display panel.
In order to solve the above technical problems, the present invention provides a kind of production method of display panel comprising:
The first metal layer is made on underlay substrate, patterned process is carried out to the first metal layer, so as to be located at aobvious
Show that the first metal layer in region forms first grid and the first metal layer positioned at gate driving circuit region forms second grid；Wherein
The display panel includes the display area and the gate driving circuit region；
In the first grid, the second grid and the lining not covered by the first grid and the second grid
Insulating layer is made on substrate；
The first semiconductor layer is formed on the insulating layer for being located at the display area and is being located at the gate driving area
The second semiconductor layer is formed on the insulating layer in domain；The material of second semiconductor layer is metal oxide；
Second metal layer is made on first semiconductor layer and second semiconductor layer, to the second metal layer
Patterned process is carried out, so that the second metal layer for being located at the display area forms the first source electrode and the first drain electrode and is located at
The second metal layer of the gate driving circuit region forms the second source electrode and the second drain electrode.
The present invention also provides a kind of display panel, wherein the display panel includes display area and gate driving circuit region,
The display panel includes:
Underlay substrate；
The first metal layer is arranged on underlay substrate, and the first metal layer includes positioned at the first of the display area
Grid and second grid positioned at the gate driving circuit region；
Insulating layer is not covered set on the first grid, the second grid and by first grid and the second grid
On the underlay substrate of lid；
First semiconductor layer, on the insulating layer of the display area；
Second semiconductor layer, on the insulating layer of the gate driving circuit region；The material of second semiconductor layer is
Metal oxide；
Second metal layer is set on first semiconductor layer and second semiconductor layer, the second metal layer packet
It includes positioned at the first source electrode of the display area and the first drain electrode and positioned at the second source electrode of the gate driving circuit region and the
Two drain electrodes.
Display panel of the invention and preparation method thereof, by using half in metal oxide production gate driving circuit region
Conductor layer improves the electron mobility of the semiconductor layer, reduces the size of driving circuit, to reduce display panel
Frame.
[Detailed description of the invention]
Fig. 1 is the structural schematic diagram of existing display panel；
Fig. 2 is that the invention shows the structural schematic diagrams of the first step of the production method of panel；
Fig. 3 is that the invention shows the structural schematic diagrams of the second step of the production method of panel；
Fig. 4 is that the invention shows the structural schematic diagrams of the third step of the production method of panel；
Fig. 5 is that the invention shows the structural schematic diagrams of the 4th step of the production method of panel；
Fig. 6 is that the invention shows the structural schematic diagrams of panel.
[specific embodiment]
The explanation of following embodiment is to can be used to the particular implementation of implementation to illustrate the present invention with reference to additional schema
Example.The direction term that the present invention is previously mentioned, such as "upper", "lower", "front", "rear", "left", "right", "inner", "outside", " side "
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand the present invention, rather than to
The limitation present invention.The similar unit of structure is to be given the same reference numerals in the figure.
As shown in Figure 1, existing display panel includes: underlay substrate 11, the first metal layer 12, insulating layer 13, the first half
Conductor layer 141, the second semiconductor layer 142, second metal layer 16.
The first metal layer 12 is arranged on underlay substrate 11, and the first metal layer 12 includes being located at display area 101
First grid 121 and second grid 122 positioned at gate driving circuit region 102.
Insulating layer 13 is set to the first grid 121 and the second grid 122 and not by first grid 121 and described
On the underlay substrate 11 that second grid 122 covers.
First semiconductor layer 141 is set on the insulating layer 13 of the display area 101.
Second semiconductor layer 142 is set on the insulating layer 13 of the gate driving circuit region 102；Second semiconductor layer
The material of 142 material and the first semiconductor layer 141 is identical, for example is amorphous silicon or indium gallium zinc oxide.
Second metal layer 16 is set on first semiconductor layer 141 and second semiconductor layer 142, second gold medal
Belonging to floor 16 includes positioned at the first source electrode 161 of the display area 101 and the first drain electrode 162 and being located at the gate driving area
Second source electrode 163 in domain 102 and the second drain electrode 164.In addition, display panel may also include passivation layer 17 and pixel electrode 18.
Referring to figure 2., Fig. 2 is that the invention shows the structural schematic diagrams of the first step of the production method of panel.
As shown in Fig. 2, the production method of display panel of the invention includes:
S101, the first metal layer is made on underlay substrate, patterned process is carried out to the first metal layer, so that position
The first metal layer in display area forms first grid and the first metal layer positioned at gate driving circuit region forms second grid.
For example, as shown in Fig. 2, the first metal layer 12 is made on underlay substrate 11, to the first metal layer 12 progress
Patterned process, so that the first metal layer 12 for being located at display area 101 forms first grid 121 and is located at gate driving circuit region
102 the first metal layer 12 forms second grid 122.Wherein display panel includes display area 101 and gate driving circuit region
102, gate driving circuit region 102 namely the region GOA (Gate Driver on Array), for gate driving circuit to be arranged,
Under depression angle comprising driving thin film transistor (TFT).
In one embodiment, the underlay substrate 11 can be glass substrate.
S102, insulating layer is made on the first grid and the second grid.
For example, as shown in figure 3, in the first grid 121 and the second grid 122 and not by the first grid
121 and the second grid 122 cover underlay substrate 11 on make insulating layer 13.In one embodiment, the insulating layer
13 material is silicon nitride or silica.
S103, the first semiconductor layer is formed on the insulating layer for being located at the display area and is driven being located at the grid
The second semiconductor layer is formed on the insulating layer in dynamic region.
For example, as shown in figure 4, be located at the display area 101 insulating layer 13 on formed the first semiconductor layer 14 with
And the second semiconductor layer 15 is formed on the insulating layer 13 for being located at the gate driving circuit region 102；Wherein second semiconductor
The material of layer 15 is metal oxide.
Wherein, the metal oxide includes at least one of IGZO, IZO, ITZO, GZO and ZnO.
In one embodiment, the material of first semiconductor layer 14 is amorphous silicon.
In order to improve the electric conductivity of semiconductor, above-mentioned steps S103 namely described it is being located at the gate driving circuit region
Insulating layer on the step of forming the second semiconductor layer can include:
S1031, it is deposited on the insulating layer for being located at the gate driving circuit region or metal oxide, to obtain the
Two semiconductor layers.
For example, deposition or metal oxide on the insulating layer 13 for being located at the gate driving circuit region 102, with
To the second semiconductor layer 15.
It will of course be understood that, the manufacture craft of the second semiconductor layer be not limited to more than mode, can also be its other party
Formula.
S104, second metal layer is made on first semiconductor layer and second semiconductor layer, to described second
Metal layer carry out patterned process so that be located at the display area second metal layer formed the first source electrode and first drain electrode with
And the second metal layer positioned at the gate driving circuit region forms the second source electrode and the second drain electrode.
For example, as shown in figure 5, making the second metal on first semiconductor layer 14 and second semiconductor layer 15
Layer 16 carries out patterned process to the second metal layer 16, so as to be located at 15 shape of second metal layer of the display area 101
The second source is formed at the first source electrode 161 and the first drain electrode 162 and the second metal layer 16 positioned at the gate driving circuit region 102
Pole 163 and the second drain electrode 164.
In one embodiment, the method may also include that
S105, it drains and in first source electrode, first drain electrode, second source electrode, described second not by institute
It states the first semiconductor layer of the first source electrode and the first drain electrode covering and is not covered by second source electrode and second drain electrode
Passivation layer is formed on second semiconductor layer of lid；
For example, as shown in fig. 6, in first source electrode 161 and first drain electrode 162 and second source electrode 163
With second drain electrode 164 and not by the first semiconductor layer 14 of first source electrode 161 and 162 covering of the first drain electrode
Passivation layer 17 is not formed on second source electrode 163 and second semiconductor layer 15 of 164 covering of the second drain electrode.
S106, patterned process is carried out to the passivation layer, so that position corresponding with first drain electrode forms via hole.
For example, patterned process is carried out to the passivation layer 17, so as to be formed with first drain electrode, 162 corresponding positions
Via hole (not shown).
In one embodiment, the display panel is liquid crystal display panel, and the method may also include that
S107, pixel electrode is made on the passivation layer and in the via hole.
For example, making pixel electrode 18 on the passivation layer 17 and in the via hole, the pixel electrode 18 passes through
The via hole is connect with first drain electrode 162.
It should be understood that the above method can be production array substrate when the display panel is liquid crystal display panel, when
So, complete liquid crystal display panel in order to obtain may also include production color membrane substrates and the filling liquid crystal between two substrates
Deng.
In another embodiment, the display panel is organic LED display panel.Above-mentioned steps S107 can be with
Replacement are as follows:
S201, anode is made on the passivation layer and in the via hole.
At this point, the method may also include that
Pixel defining layer, organic function layer, electron transfer layer and cathode etc. are made on the anode.
Wherein, organic function layer includes the hole injection layer, hole transmission layer and organic light emission being sequentially located on anode
Layer.The material of cathode can be indium-zinc oxide (IZO) either Mg/Ag laminated film.
Due to, by using metal oxide production gate driving circuit region semiconductor layer, and metal oxide have compared with
The characteristics of high mobility (about 10 times of amorphous silicon), therefore the electron mobility of the semiconductor layer is improved, reduce grid
The size of thin film transistor (TFT) in drive area to reduce the size of driving circuit, and then reduces the frame of display panel.
But the electrical stability of metal oxide is poorer than amorphous silicon, therefore is not easily applicable to entire panel.
As shown in fig. 6, the present invention also provides a kind of display panels made by the above method comprising: underlay substrate
11, the first metal layer 12, insulating layer 13, the first semiconductor layer 14, the second semiconductor layer 15 and second metal layer 16.
The first metal layer 12 is arranged on underlay substrate 11, and the first metal layer 12 includes being located at display area 101
First grid 121 and second grid 122 positioned at gate driving circuit region 102.
Insulating layer 13 is set to the first grid 121 and the second grid 122 and not by first grid 121 and described
On the underlay substrate 11 that second grid 122 covers.
First semiconductor layer 14 is set on the insulating layer 13 of the display area 101.
Second semiconductor layer 15 is set on the insulating layer 13 of the gate driving circuit region 102；Wherein second semiconductor
The material of layer 15 is metal oxide.Wherein the metal oxide includes IGZO (indium gallium zinc oxide), IZO (indium zinc oxidation
Object), ITZO (indium tin zinc oxide), in GZO (zinc oxide that siliceous tin indium oxide or gallium mix up) and ZnO (zinc oxide) extremely
Few one kind.Wherein the material of first semiconductor layer 14 is amorphous silicon.Namely the electricity of the material of second semiconductor layer 15
Transport factor is greater than the electron mobility of the first semiconductor layer 14.The material of first semiconductor layer 14 and second semiconductor layer
15 material is different.
Second metal layer 16 is set on first semiconductor layer 14 and second semiconductor layer 15, second metal
Layer 16 includes positioned at the first source electrode 161 of the display area 101 and the first drain electrode 162 and being located at the gate driving circuit region
102 the second source electrode 163 and the second drain electrode 164.
The display panel may also include passivation layer 17, and passivation layer 17 is set to first source electrode 161, first drain electrode
162, it second source electrode 163, second drain electrode 164 and 162 is not covered by first source electrode 161 and first drain electrode
First semiconductor layer 14 of lid and second semiconductor not covered by second source electrode 163 and second drain electrode 164
On layer 15.Via hole is provided on passivation layer 17.
In one embodiment, the display panel is liquid crystal display panel, and the display panel may also include pixel electrode
18.Pixel electrode 18 is set on the passivation layer 17 and in the via hole, and the pixel electrode 18 passes through the via hole and institute
State the first drain electrode 162 connection.
In another embodiment, the display panel is organic LED display panel.
Display panel of the invention and preparation method thereof, by using half in metal oxide production gate driving circuit region
Conductor layer improves the electron mobility of the semiconductor layer, reduces the size of driving circuit, to reduce display panel
Frame.
In conclusion although the present invention has been disclosed above in the preferred embodiment, but above preferred embodiment is not to limit
The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention subjects to the scope of the claims.
Claims (10)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910136685.5A CN109887968A (en) | 2019-02-25 | 2019-02-25 | A display panel and method of making the same |
| PCT/CN2019/078216 WO2020172918A1 (en) | 2019-02-25 | 2019-03-15 | Display panel and fabricating method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910136685.5A CN109887968A (en) | 2019-02-25 | 2019-02-25 | A display panel and method of making the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109887968A true CN109887968A (en) | 2019-06-14 |
Family
ID=66929172
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910136685.5A Pending CN109887968A (en) | 2019-02-25 | 2019-02-25 | A display panel and method of making the same |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN109887968A (en) |
| WO (1) | WO2020172918A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111081633A (en) * | 2020-01-07 | 2020-04-28 | Tcl华星光电技术有限公司 | Preparation method of array substrate and array substrate |
| CN113138487A (en) * | 2021-04-13 | 2021-07-20 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN114497079A (en) * | 2021-12-28 | 2022-05-13 | Tcl华星光电技术有限公司 | Thin film transistor, manufacturing method, driving method and display panel |
| CN115312543A (en) * | 2022-08-31 | 2022-11-08 | 北海惠科光电技术有限公司 | Array substrate, manufacturing method and display panel |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012032749A1 (en) * | 2010-09-09 | 2012-03-15 | シャープ株式会社 | Thin-film transistor substrate, method for producing same, and display device |
| CN106057826A (en) * | 2016-08-08 | 2016-10-26 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, and display apparatus |
| CN106449667A (en) * | 2016-12-21 | 2017-02-22 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN106920801A (en) * | 2015-12-24 | 2017-07-04 | 群创光电股份有限公司 | Display device |
| CN107644882A (en) * | 2017-10-25 | 2018-01-30 | 上海中航光电子有限公司 | Array base palte, display panel and display device |
| US20180069126A1 (en) * | 2016-09-05 | 2018-03-08 | Japan Display Inc. | Semiconductor device |
| US20180113564A1 (en) * | 2016-10-21 | 2018-04-26 | Semiconductor Energy Laboratory Co., Ltd. | Display device and operating method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101048965B1 (en) * | 2009-01-22 | 2011-07-12 | 삼성모바일디스플레이주식회사 | Organic electroluminescent display |
| TWI500161B (en) * | 2011-06-02 | 2015-09-11 | Au Optronics Corp | Hybrid thin film transistor, manufacturing method thereof and display panel |
| CN104538352A (en) * | 2014-12-31 | 2015-04-22 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN105870059A (en) * | 2016-06-24 | 2016-08-17 | 京东方科技集团股份有限公司 | Thin film transistor, array substrate and their manufacture methods, and display panel |
| CN106252364A (en) * | 2016-10-09 | 2016-12-21 | 深圳市华星光电技术有限公司 | The manufacture method of a kind of GOA array base palte and GOA array base palte |
| CN106783871B (en) * | 2016-11-18 | 2019-11-08 | 上海天马微电子有限公司 | Array substrate, display panel and manufacturing method |
-
2019
- 2019-02-25 CN CN201910136685.5A patent/CN109887968A/en active Pending
- 2019-03-15 WO PCT/CN2019/078216 patent/WO2020172918A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2012032749A1 (en) * | 2010-09-09 | 2012-03-15 | シャープ株式会社 | Thin-film transistor substrate, method for producing same, and display device |
| CN106920801A (en) * | 2015-12-24 | 2017-07-04 | 群创光电股份有限公司 | Display device |
| CN106057826A (en) * | 2016-08-08 | 2016-10-26 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, and display apparatus |
| US20180069126A1 (en) * | 2016-09-05 | 2018-03-08 | Japan Display Inc. | Semiconductor device |
| US20180113564A1 (en) * | 2016-10-21 | 2018-04-26 | Semiconductor Energy Laboratory Co., Ltd. | Display device and operating method thereof |
| CN106449667A (en) * | 2016-12-21 | 2017-02-22 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method thereof and display device |
| CN107644882A (en) * | 2017-10-25 | 2018-01-30 | 上海中航光电子有限公司 | Array base palte, display panel and display device |
Non-Patent Citations (1)
| Title |
|---|
| 于军胜: "《显示器件技术》", 31 August 2014, 国防工业出版社 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111081633A (en) * | 2020-01-07 | 2020-04-28 | Tcl华星光电技术有限公司 | Preparation method of array substrate and array substrate |
| CN113138487A (en) * | 2021-04-13 | 2021-07-20 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| US12066729B2 (en) | 2021-04-13 | 2024-08-20 | Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel and display device |
| CN114497079A (en) * | 2021-12-28 | 2022-05-13 | Tcl华星光电技术有限公司 | Thin film transistor, manufacturing method, driving method and display panel |
| CN114497079B (en) * | 2021-12-28 | 2024-11-22 | Tcl华星光电技术有限公司 | Thin film transistor, manufacturing method, driving method and display panel |
| CN115312543A (en) * | 2022-08-31 | 2022-11-08 | 北海惠科光电技术有限公司 | Array substrate, manufacturing method and display panel |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2020172918A1 (en) | 2020-09-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107424957B (en) | Manufacturing method of flexible TFT substrate | |
| CN102629621B (en) | A kind of circuit, array base palte and manufacture method, display | |
| CN104078424B (en) | Low-temperature poly-silicon TFT array substrate, manufacturing method thereof and display device | |
| CN103489826B (en) | Array base palte, preparation method and display unit | |
| CN107565049B (en) | AMOLED display panel and preparation method thereof | |
| CN104977764A (en) | Array substrate, manufacturing method thereof and liquid crystal display | |
| WO2015100898A1 (en) | Thin-film transistor, tft array substrate and manufacturing method therefor, and display device | |
| CN108054192A (en) | Flexible AMOLED substrates and preparation method thereof | |
| CN108376688A (en) | A kind of photosensory assembly and preparation method thereof, array substrate, display device | |
| CN104637955B (en) | A kind of array base palte and preparation method thereof, display device | |
| CN103219391A (en) | Thin film transistor, manufacturing method thereof, array substrate and display device | |
| CN106206620B (en) | Thin film transistor array substrate and its preparation method and display device | |
| CN109887968A (en) | A display panel and method of making the same | |
| CN109378326A (en) | Display panel and method of making the same | |
| US9214476B1 (en) | Pixel structure | |
| CN103700669A (en) | Array substrate and preparation method thereof as well as display device | |
| WO2016176881A1 (en) | Manufacturing method for dual-gate tft substrate, and structure of dual-gate tft substrate | |
| CN108766989A (en) | A kind of optical sensor device and preparation method thereof, display device, display equipment | |
| CN102683276B (en) | Pixel driving circuit, preparation method thereof and array substrate | |
| WO2015035832A1 (en) | Array substrate and preparation method therefor, and display device | |
| CN101834200B (en) | Organic RL display and fabricating method thereof | |
| CN107591413A (en) | A kind of preparation method of TFT substrate, TFT substrate and OLED display panel | |
| CN104157609B (en) | The preparation method and its structure of TFT substrate | |
| CN104157608B (en) | Manufacture method for and structure of the TFT substrate | |
| CN108269856A (en) | A kind of oxide semiconductor thin-film transistor and preparation method thereof, array substrate |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20190614 |