CN110995254B - A high performance phase-locked digital frequency synthesis device - Google Patents
A high performance phase-locked digital frequency synthesis device Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
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- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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Abstract
The invention provides a high-performance phase-locked digital frequency synthesizer, which comprises an input end of a DDS device of an output end of a crystal oscillator circuit, wherein the output end of the DSP device is connected with the input end of the DDS device, the output end of the crystal oscillator circuit is connected with the input end of a mixer, the output end of the mixer is connected with the input end of a band-pass filter, the output end of the band-pass filter is connected with the input end of a phase discriminator, the output end of the phase discriminator is connected with the input end of a low-pass filter, the output end of the low-pass filter is connected with the input end of an amplifier, the output end of the amplifier is connected with the input end of a voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected with the input end of a dual-mode pre-divider, the output end of the dual-mode pre-divider is connected with the input end of an N-divider, and the output end of the N-divider is connected with the input end of the phase discriminator.
Description
Technical Field
The invention relates to the technical field of electronic circuits, in particular to a high-performance phase-locked digital frequency synthesizer.
Background
With the development of modern electronic science technology, the frequency synthesis technology is more and more widely applied, and the requirement on frequency synthesis is also higher and higher. The frequency synthesis technology is widely applied to the fields of radars, electronic countermeasure, communication, digital televisions, medical equipment, remote control telemetry, electronic measuring instruments and the like.
Frequency synthesizers are the heart of many modern electronic devices and can to a large extent affect the overall performance of the device. For example, in radar and communication systems, a frequency synthesizer is used as an excitation signal source of a transmitter and a local oscillation source of a receiver, and directly related to modulation and demodulation of a transmission signal and a reception signal, in electronic countermeasure systems, the frequency synthesizer can be used in an interference annunciator or a frequency detection device, and directly related to the overall performance of the electronic countermeasure device, and in electronic measuring instruments and other devices, the frequency synthesizer can be used as a standard signal source, and the like. The performance of the frequency synthesizer is directly related to the overall performance index of the device.
The DDS technology can realize frequency resolution of mu Hz magnitude, but the output frequency is lower and is generally lower than 1GHz, so that a wider-band signal is required to be generated in a matching way. The DDS direct drive phase-locked loop mode can be adopted, and the mode is simple to realize and low in cost. However, the spurious of the DDS is worse, and the spurious is further deteriorated after the frequency multiplication of the phase-locked loop, and the deterioration degree is not effectively restrained, so that the direct driving of the phase-locked loop by the DDS cannot meet the index requirement. If fractional frequency division is adopted, frequency stepping of the Hz magnitude can be realized, but more spurious signals can be generated by the fractional frequency division, the spurious signals generated by the fractional frequency division are modulated at present, and the spurious signals are modulated to a far end so as to achieve the effect of reducing spurious signals, but the low spurious index requirement cannot be met finally.
Disclosure of Invention
The object of the present invention is to solve at least one of the technical drawbacks.
Therefore, the present invention is directed to a high-performance phase-locked digital frequency synthesizer.
In order to achieve the above object, the embodiment of the invention provides a high-performance phase-locked digital frequency synthesizer, which comprises a crystal oscillator circuit, a DSP device, a DDS device, a mixer, a band-pass filter, a phase discriminator, a low-pass filter, an amplifier, a voltage-controlled oscillator, a dual-mode prescaler and an N frequency divider, wherein the input end of the DDS device at the output end of the crystal oscillator circuit is connected with the input end of the DDS device, the output end of the crystal oscillator circuit is connected with the input end of the mixer, the output end of the mixer is connected with the input end of the band-pass filter, the output end of the band-pass filter is connected with the input end of the phase discriminator, the output end of the low-pass filter is connected with the input end of the amplifier, the output end of the amplifier is connected with the input end of the voltage-controlled oscillator, the output end of the voltage-controlled oscillator is connected with the input end of the prescaler, the output end of the frequency divider is connected with the input end of the N frequency divider,
The DDS device comprises a reference clock source, a first phase accumulator, a phase register, a second phase accumulator, a phase amplitude converter, a D/A converter and a low-pass filter device, wherein the output end of the reference clock source is respectively connected with the D/A converter and the first phase accumulator, the output end of the first phase accumulator is connected with the phase register, the phase register is connected with the second phase accumulator, the opposite output end of the second phase accumulator is connected with the input end of the D/A converter, the output end of the D/A converter is further connected with the input end of the low-pass filter device,
The data input end of the D/A converter is connected with the amplitude limiting converter, the first output end of the D/A converter is connected with the negative input end of the comparator, the second output end of the D/A converter is connected with the positive input end of the comparator, and the output end of the comparator is connected with the low-pass filter device;
the phase discriminator, the low-pass filter device, the amplifier, the voltage-controlled vibrator, the dual-mode prescaler and the program counter form a phase-locked loop.
Further, the low-pass filter device comprises a first resistor, a second resistor, a first capacitor, a second capacitor and an operational amplifier, wherein one end of the first resistor is connected with the output end of the comparator, the other end of the first resistor is connected with one end of the second resistor, the other end of the second resistor is connected with the positive end of the operational amplifier and one end of the second capacitor, the other end of the second capacitor is grounded, the negative end of the operational amplifier is connected with the output end of the operational amplifier, the other end of the first resistor is further connected with one end of the first capacitor, and the other end of the first capacitor is connected with the output end of the operational amplifier.
Further, the DSP device adopts a DSP chip with the model TMS320C 5402.
The dual-mode pre-prescaler comprises a high-speed frequency divider, a first down counter and a second down counter, wherein the output end of the high-speed frequency divider is connected with the input end of the first down counter, the input end of the second down counter and two input ends of an AND gate, and the first down counter is further connected with an internal digital phase discriminator.
The voltage-controlled oscillator further comprises a resonant circuit and a voltage-controlled oscillating circuit, wherein the resonant circuit comprises a first varactor, a second varactor, a third varactor, a fourth varactor and a first inductor, the reverse end of the first varactor is connected with the reverse end of the second varactor, the reverse end of the third varactor is connected with the reverse end of the fourth varactor, the first inductor is connected in parallel between the first varactor and the second varactor and between the third varactor and the fourth varactor, and the voltage-controlled oscillating circuit is further connected at the two ends of the first inductor.
Further, the voltage-controlled oscillating circuit comprises a resistor connected between a base electrode and an emitter electrode of the first triode, the emitter electrode of the first triode is further connected with a collector electrode of the second triode, the base electrode of the second triode is connected with a collector electrode of the third triode, the base electrode of the third triode is connected with bias voltage and is further connected with a base electrode of the fourth triode, the emitter electrodes of the fourth triode and the fifth triode are commonly connected to a collector electrode of the sixth triode through the resistor, the collector electrode of the fifth triode is connected with a base electrode of the seventh triode, the collector electrode of the seventh triode is connected with a base electrode of the eighth triode, the emitter electrode of the eighth triode is connected with an emitter electrode of the ninth triode, the collector electrode of the ninth triode is connected with a base electrode of the thirteenth triode, and the emitter electrode of the tenth triode is used as an output end to be connected with the dual-mode pre-divider.
According to the high-performance phase-locked digital frequency synthesizer, the DDS+PLL frequency synthesizer design scheme is adopted, so that the high-performance phase-locked digital frequency synthesizer has the characteristics of excellent phase noise, tiny frequency stepping, low spurious emission, wide frequency range, strong frequency expansibility and the like. The method is realized by the PLL synthesis technology, and has the characteristics of high frequency, express delivery and good spectrum quality. In addition, the circuit of the invention has simple design, is easy to realize miniaturization, and is suitable for being applied to communication and measuring equipment with higher cost performance requirements. The invention adopts DDS technology, which has extremely wide coverage frequency, high stability and accuracy, quick frequency switching, continuous waveform, small error and low price when switching frequency, and is widely applied to the fields of radar, communication, remote control and remote measurement, navigation, instruments and meters, and the like.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
fig. 1 is a block diagram of a high-performance phase-locked digital frequency synthesizer according to an embodiment of the present invention;
Fig. 2 is a block diagram of a DDS device according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a DSP device according to an embodiment of the invention;
fig. 4 is a circuit diagram of a D/a converter according to an embodiment of the present invention;
Fig. 5 is a circuit diagram of a low pass filtering device according to an embodiment of the present invention;
fig. 6 is a circuit diagram of a bandpass filter according to an embodiment of the invention;
fig. 7 is a circuit diagram of a voltage controlled oscillation tuning circuit according to an embodiment of the present invention;
fig. 8 is a circuit diagram of a voltage controlled oscillator according to an embodiment of the present invention;
Fig. 9 is a circuit diagram of a dual mode prescaler in accordance with an embodiment of the present invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present invention and should not be construed as limiting the invention.
As shown in FIG. 1, the high-performance phase-locked digital frequency synthesizer according to the embodiment of the invention comprises a crystal oscillator circuit 1, a DSP device 2, a DDS device 3, a mixer 4, a band-pass filter 5, a phase discriminator 6, a low-pass filter device, an amplifier 8, a voltage-controlled oscillator 9, a dual-mode prescaler 10 and a N frequency divider.
The input end of a DDS device 3 of the output end of a crystal oscillator circuit 1 is connected, the output end of a DSP device 2 is connected with the input end of the DDS device 3, the output end of the crystal oscillator circuit 1 is connected with the input end of a mixer 4, the output end of the mixer 4 is connected with the input end of a band-pass filter 5, the output end of the band-pass filter 5 is connected with the input end of a phase discriminator 6, the output end of the phase discriminator 6 is connected with the input end of a low-pass filter device, the output end of the low-pass filter device is connected with the input end of an amplifier 8, the output end of the amplifier 8 is connected with the input end of a voltage-controlled oscillator 9, the output end of the voltage-controlled oscillator 9 is connected with the input end of a dual-mode prescaler 10, the output end of the dual-mode prescaler 10 is connected with the input end of an N-frequency divider, and the output end of the N-frequency divider is connected with the input end of the phase discriminator 6.
Specifically, as shown in fig. 5, the low-pass filter device comprises a first resistor R1, a second resistor R2, a first capacitor C1, a second capacitor C2 and an operational amplifier, wherein one end of the first resistor R1 is connected with the output end of the comparator, the other end of the first resistor R1 is connected with one end of the second resistor R2, the other end of the second resistor R2 is connected with the positive end of the operational amplifier and one end of the second capacitor C2, the other end of the second capacitor C2 is grounded, the negative end of the operational amplifier is connected with the output end of the operational amplifier, the other end of the first resistor R1 is further connected with one end of the first capacitor C1, and the other end of the first capacitor C1 is connected with the output end of the operational amplifier.
Fig. 6 is a circuit diagram of a bandpass filter according to an embodiment of the invention. As shown in fig. 6, the band-pass filter adopts a comparator, wherein the negative input end of the comparator is connected to the output end of the mixer through a capacitor C1 and a resistor R1, the positive input end of the comparator is grounded, the output end of the comparator is connected to the input end of the phase detector, and the negative input end and the output end of the comparator are in short circuit.
In an embodiment of the present invention, referring to FIG. 3, DSP device 2 employs a model TMS320C5402 DSP chip.
As shown in fig. 2, the DDS device 3 includes a reference clock source, a first phase accumulator, a phase register, a second phase accumulator, a phase amplitude converter, a D/a converter and a low-pass filter, where an output end of the reference clock source is connected to the D/a converter and the first phase accumulator, an output end of the first phase accumulator is connected to the phase register, the phase register is connected to the second phase accumulator, an output end of the second phase accumulator is connected to an input end of the D/a converter, and an output end of the D/a converter is further connected to an input end of the low-pass filter.
The invention selects the DDS excitation PLL mode, can combine the DDS and PLL two frequency synthesis technologies, and the digital and analog synthesis modes work simultaneously, and make up for the shortages to realize high-speed broadband frequency synthesis with high resolution and less spurious.
The DDS principle is to construct a relation table of phase and amplitude by utilizing the characteristic that the phase and the amplitude of a sinusoidal signal correspond, and construct discrete amplitude data by using a digital circuit mode, and finally reconstruct the frequency of an analog sinusoidal signal by digital-to-analog conversion, wherein the DDS principle comprises a phase accumulator, a waveform memory, a digital-to-analog converter, a filter and the like.
The invention adopts a DDS frequency mixing frequency division driving phase-locked loop mode, and the mode realizes low spurious indexes while meeting the requirement of small steps. The small step signal generated by the DDS is moved to the required frequency through frequency mixing and then is used as a reference signal for frequency synthesis after frequency division. Thus, the small stepping signal generated by the DDS can improve the spurious suppression degree after being processed, reduce the phase noise and ensure the final output frequency stepping.
In addition, since DDS generates a large amount of spurious, in order to obtain a good spurious suppression performance, a band-pass filter 5 is added after mixing to suppress spurious components. Preferably, the double-tuned band-pass filter 5 is adopted, and the factors such as the complexity of the filter, the reference frequency of the DDS, the output frequency of the DDS and the like can be considered, and the double-tuned filter has extremely steep sidebands and smaller bandwidth.
As shown in fig. 4, the data input end of the D/a converter is connected with the clipping converter, the first output end of the D/a converter is connected with the negative input end of the comparator, the second output end of the D/a converter is connected with the positive input end of the comparator, and the output end of the comparator is connected with the low-pass filter device. The D/A converter adopts a digital-to-analog conversion chip with the model of DAC0830 LCM.
The phase detector 6, the low-pass filter device, the amplifier 8, the voltage-controlled vibrator, the dual-mode prescaler 10 and the program counter 11 form a phase-locked loop.
Specifically, as shown in fig. 9, the dual-mode pre-prescaler comprises a high-speed frequency divider 91, a first down counter 92 and a second down counter 93, wherein the output end of the high-speed frequency divider 91 is connected with the input end of the first down counter 92, the input end of the second down counter 93 and two input ends of an and gate, and the first down counter 92 is further connected with an internal digital phase detector PD.
The dual-mode pre-divider adopts a pre-stage high-speed frequency divider to pre-divide f0 so as to reduce the frequency, then the frequency is continuously divided by a first down counter and a second down counter to obtain a frequency with equal reference frequency, and then the frequency is sent to an internal digital phase discriminator PD for phase discrimination. In addition, the invention adopts a swallowing pulse counting method to count, so that the frequency-dividing coefficient is continuously adjustable.
The dual mode prescaler 10 is initially operated with a p+1 division ratio and the count of the pulse swallow counter a is decremented to 0, at which time a total of (p+1) x a voltage controlled oscillator 9 pulses are input. At this time, the pulse swallowing counter A stops, the program counter 11N continues to count down from (N-A), the dual-mode prescaler 10 operates with the P frequency division ratio, and when the value count of the program counter 11A is reduced to 0, P× (N-A) voltage-controlled oscillator 9 pulses are input in total. Thus, in one operation the frequency division ratio is m= (p+1) ×a+p× (N-Sup>A) =np+Sup>A. In the working process, only the dual-mode pre-divider 10 works in a high-speed state, the pulse swallowing counter and the program technical device are lower than the dual-mode divider by P times, the frequency division ratio reaches NP+A, and the higher frequency output requirement can be obtained.
The voltage controlled oscillator 9 includes a resonant tank and a voltage controlled oscillating circuit.
Specifically, as shown in fig. 7, the resonant circuit includes a first varactor, a second varactor, a third varactor, a fourth varactor, and a first inductor, where a reverse end of the first varactor is connected to a reverse end of the second varactor, a reverse end of the third varactor is connected to a reverse end of the fourth varactor, the first inductor is connected in parallel between the first varactor and the second varactor, and between the third varactor and the fourth varactor, and voltage-controlled oscillation circuits are further connected at two ends of the first inductor.
The resonant circuit has 5V working voltage, up to 225MHz output frequency and high output frequency spectrum purity, and the bias voltage of the varactor can be controlled by adopting an LC resonant tank circuit consisting of the varactor and the inductor. The two varactors are connected back to back, namely, the bias points of the varactors are identical to the modulated state for direct current and modulated signals, and the varactors correspond to high-frequency signals, namely, the varactors are connected in series, so that the voltage amplitude of two ends of each varactor is reduced, the effect of high-frequency voltage is weakened, and the influence of the conduction of the varactors on a resonant circuit is prevented when the high-frequency voltage amplitude is overlarge.
As shown in FIG. 8, the voltage-controlled oscillation circuit comprises a resistor connected between a base electrode and an emitter electrode of a first triode, the emitter electrode of the first triode is further connected with a collector electrode of a second triode, the base electrode of the second triode is connected with a collector electrode of a third triode, the base electrode of the third triode is connected with a bias voltage and is further connected with a base electrode of a fourth triode, the emitter electrodes of the fourth triode and the fifth triode are commonly connected with a collector electrode of a sixth triode through the resistor, the collector electrode of the fifth triode is connected with a base electrode of a seventh triode, the collector electrode of the seventh triode is connected with a base electrode of an eighth triode, the emitter electrode of the eighth triode is connected with an emitter electrode of a ninth triode, the collector electrode of the ninth triode is connected with a base electrode of a thirteenth triode, and the emitter electrode of the tenth triode is used as an output end to be connected with the pre-dual-mode frequency divider 10.
The resonant circuit is connected from the pin 10BIAS and the pin 12TANK, and forms a positive feedback sinusoidal oscillation circuit with 720 degrees phase shift together with the internal Q7, Q4, Q5, D1 and Q8, and the base electrode of the Q6 is connected with the collector electrode of the Q7 to form positive feedback. The amplitude of the output frequency is stabilized by an amplifying circuit and an automatic gain control circuit (D1, Q6, Q7, Q8) in the voltage-controlled oscillation circuit. When the oscillation amplitude increases, the base voltage of Q8 increases, the collector current increases, and the output amplitude decreases. If the oscillation amplitude decreases, the current of the constant current source Q8 decreases, the amplification factors of Q6 and Q7 increase, and the output amplitude increases.
The invention starts testing the phase noise of the near end of the output 6GHz signal in the direct in-loop mixing of the DDS and the PLL to obtain the phase noise of-114.92 dBc/Hz output at the frequency shift of 10kHz, and the phase noise of the system output at the frequency shift of 10kHz is better than-126.38 dBc/Hz after the double phase-locked loop is adopted for optimization.
The working principle of the high-performance phase-locked digital frequency synthesizer is that a crystal oscillator circuit provides a clock signal with high stability, a DSP device sends a control command, a DDS device generates a low-frequency sinusoidal signal according to the control command, the low-frequency sinusoidal signal is further input to a mixer 4 together with a reference source of the crystal oscillator circuit, the mixer 4 mixes the clock signal of the reference source and the low-frequency sinusoidal signal to obtain a higher reference frequency, and the filtered signal enters a phase-locked loop after being filtered by a band-pass filter 5. The filtered signal is sent to a phase discriminator, the mixed reference frequency is subjected to frequency division for R times, and the frequency signal finally output by the system is subjected to phase comparison after being subjected to frequency division for N times (firstly subjected to pre-frequency division by a dual-mode prescaler 10), so that error voltage is obtained, and then the error voltage is subjected to tuning by an active low-pass filter 7, and a signal meeting the system requirement is output.
According to the high-performance phase-locked digital frequency synthesizer, the DDS+PLL frequency synthesizer design scheme is adopted, so that the high-performance phase-locked digital frequency synthesizer has the characteristics of excellent phase noise, tiny frequency stepping, low spurious emission, wide frequency range, strong frequency expansibility and the like. The method is realized by the PLL synthesis technology, and has the characteristics of high frequency, express delivery and good spectrum quality. In addition, the circuit of the invention has simple design, is easy to realize miniaturization, and is suitable for being applied to communication and measuring equipment with higher cost performance requirements. The invention adopts DDS technology, which has extremely wide coverage frequency, high stability and accuracy, quick frequency switching, continuous waveform, small error and low price when switching frequency, and is widely applied to the fields of radar, communication, remote control and remote measurement, navigation, instruments and meters, and the like.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Although embodiments of the present invention have been shown and described above, it will be understood that the above embodiments are illustrative and not to be construed as limiting the invention, and that variations, modifications, alternatives, and variations may be made in the above embodiments by those skilled in the art without departing from the spirit and principles of the invention. The scope of the invention is defined by the appended claims and equivalents thereof.
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| CN203166870U (en) * | 2013-04-28 | 2013-08-28 | 常州信息职业技术学院 | Frequency synthesizer based on DDS Technology |
| CN103957008A (en) * | 2014-05-21 | 2014-07-30 | 北京遥测技术研究所 | Multi-ring frequency mixing phase locking frequency synthesis type S frequency band small-step frequency synthesizer |
| CN204131498U (en) * | 2014-10-22 | 2015-01-28 | 华中科技大学 | A kind of phase-locked loop frequency synthesizer |
| CN107947790B (en) * | 2017-12-15 | 2023-10-03 | 成都爱科特科技发展有限公司 | Broadband fine stepping low-noise frequency source |
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