CN110993651A - Array substrate and preparation method thereof - Google Patents
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- CN110993651A CN110993651A CN201911157200.7A CN201911157200A CN110993651A CN 110993651 A CN110993651 A CN 110993651A CN 201911157200 A CN201911157200 A CN 201911157200A CN 110993651 A CN110993651 A CN 110993651A
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- 239000000758 substrate Substances 0.000 title claims abstract description 73
- 238000002360 preparation method Methods 0.000 title claims abstract description 10
- 239000010409 thin film Substances 0.000 claims abstract description 22
- 239000010408 film Substances 0.000 claims abstract description 8
- 239000010410 layer Substances 0.000 claims description 198
- 239000004020 conductor Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 22
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 17
- 239000000956 alloy Substances 0.000 claims description 17
- 239000011229 interlayer Substances 0.000 claims description 14
- 238000000034 method Methods 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 10
- 239000010936 titanium Substances 0.000 claims description 10
- 229910052719 titanium Inorganic materials 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 claims description 9
- 229910052804 chromium Inorganic materials 0.000 claims description 9
- 239000011651 chromium Substances 0.000 claims description 9
- 229910052750 molybdenum Inorganic materials 0.000 claims description 9
- 229910052759 nickel Inorganic materials 0.000 claims description 9
- 229910052721 tungsten Inorganic materials 0.000 claims description 9
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 8
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 8
- 239000011733 molybdenum Substances 0.000 claims description 8
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 8
- 239000010937 tungsten Substances 0.000 claims description 8
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000059 patterning Methods 0.000 claims description 6
- 230000008569 process Effects 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 2
- 230000003071 parasitic effect Effects 0.000 abstract description 4
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 229920001621 AMOLED Polymers 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 238000004020 luminiscence type Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- -1 titanium metals Chemical class 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements
- H10K59/1213—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements the pixel elements being TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6723—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device having light shields
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- Physics & Mathematics (AREA)
- Geometry (AREA)
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Thin Film Transistor (AREA)
Abstract
本申请提供一种阵列基板及其制备方法，该阵列基板包括：衬底基板；薄膜晶体管层，设置于衬底基板上，其包括层叠设置的无机膜层以及位于无机膜层中的薄膜晶体管；薄膜晶体管包括有源层、栅极、源极以及漏极；其中，源极和漏极在衬底基板上的正投影均位于栅极在衬底基板上的正投影的范围之外。本申请中薄膜晶体管的源极和漏极均采用与栅极无交叠的设计，从而减小寄生电容，提升显示性能。
The present application provides an array substrate and a preparation method thereof. The array substrate includes: a base substrate; a thin film transistor layer, which is disposed on the base substrate and includes a stacked inorganic film layer and a thin film transistor located in the inorganic film layer; The thin film transistor includes an active layer, a gate electrode, a source electrode and a drain electrode; wherein, the orthographic projections of the source electrode and the drain electrode on the base substrate are both outside the range of the orthographic projection of the gate electrode on the base substrate. The source and drain of the thin film transistor in the present application are designed not to overlap with the gate, thereby reducing parasitic capacitance and improving display performance.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a preparation method thereof.
Background
With the development of the AMOLED display technology towards large size, high resolution, high performance and the like, the problem of the performance reduction of the AMOLED caused by RC (capacitance resistance) delay in the array substrate is more prominent. The main reason for RC delay comes from the resistance of metal traces and the overlap capacitance of gate (S) and source/drain (S/D) in the TFT structure. In addition, due to the photo-sensitive property of the semiconductor material in the channel region, the characteristics of the TFT may be affected by ambient light, self-luminescence of the AMOLED, and the like, resulting in a reduction in display performance.
Therefore, the prior art has defects and needs to be improved urgently.
Disclosure of Invention
The application provides an array substrate and a preparation method thereof, which can solve the technical problem that the display performance is influenced by RC delay due to overlarge parasitic capacitance generated by a thin film transistor.
In order to solve the above problems, the technical solution provided by the present application is as follows:
the application provides an array substrate, includes:
a substrate base plate;
the thin film transistor layer is arranged on the substrate and comprises an inorganic film layer and a thin film transistor positioned in the inorganic film layer in a stacked mode;
the thin film transistor comprises an active layer, a grid electrode, a source electrode and a drain electrode;
wherein, the orthographic projections of the source electrode and the drain electrode on the substrate base plate are both positioned outside the range of the orthographic projection of the grid electrode on the substrate base plate.
In the array substrate of the application, the array substrate further comprises a patterned light shielding layer, wherein the light shielding layer is located between the active layer and the substrate and is arranged in an insulating mode with the active layer through a buffer layer.
In the array substrate of the present application, an orthographic projection of the thin film transistor on the substrate is located within a range of an orthographic projection of the light shielding layer on the substrate.
In the array substrate, the active layer includes a channel region and conductor regions located at two sides of the channel region, a gate insulation pattern block is arranged on the active layer corresponding to the channel region, and the gate and the active layer are arranged in an insulation manner through the gate insulation pattern block.
In the array substrate, an interlayer insulating layer is arranged on the grid electrode, a first through hole is formed in the interlayer insulating layer corresponding to the conductor region, and the source electrode and the drain electrode are in electrical contact with the conductor region through the first through hole respectively.
In the array substrate of this application, the grid includes first sub-grid layer and the second sub-grid layer of range upon range of, the second sub-grid layer is located on the first sub-grid layer, the material of first sub-grid layer includes one or more than one alloy material in molybdenum, titanium, tungsten, chromium, nickel, the material of second sub-grid layer includes one or more than one alloy material in copper, the aluminium.
In the array substrate, the source electrode comprises a first sub-source electrode layer and a second sub-source electrode layer which are stacked, the drain electrode comprises a first sub-drain electrode layer and a second sub-drain electrode layer which are stacked, and the materials of the first sub-source electrode layer and the first sub-drain electrode layer respectively comprise one or more alloy materials of molybdenum, titanium, tungsten, chromium and nickel, or are oxide semiconductor materials; the second sub-source electrode layer and the second sub-drain electrode layer are made of one or more alloy materials of copper and aluminum.
The application also provides a preparation method of the array substrate, which comprises the following steps:
step S10, sequentially forming a patterned light shielding layer, a buffer layer and a patterned active layer on a substrate, wherein the active layer comprises a channel region and conductor regions positioned on two sides of the channel region;
step S20, sequentially forming a gate insulating layer and a gate layer on the active layer, and patterning the gate insulating layer and the gate layer to form a gate insulating pattern corresponding to the channel region and a gate electrode on the gate insulating pattern;
step S30, forming an interlayer insulating layer on the gate electrode and patterning the interlayer insulating layer to form a first via hole corresponding to the conductor region;
step S40, forming a source drain electrode layer on the interlayer insulating layer and patterning the source drain electrode layer to form a source electrode and a drain electrode electrically contacting the conductor region of the active layer, where the orthographic projections of the source electrode and the drain electrode on the substrate are both outside the range of the orthographic projection of the gate electrode on the substrate.
In the manufacturing method of the present application, in the step S20, the gate insulating layer and the gate layer are patterned by a photo-masking process, and the gate insulating pattern and the gate are formed at the same time.
In the preparation method of the present application, after the step S20, the method further includes the steps of: and conducting a conductor process on the parts of the active layer corresponding to the two sides of the channel region to form a conductor region of the active layer.
The beneficial effect of this application does: according to the array substrate and the preparation method thereof, the light shading layer with the light shading performance is additionally arranged below the thin film transistor, so that the problem that the display performance of the thin film transistor is reduced due to the influence of external environment light, self-luminescence of the AMOLED display panel and the like can be avoided. In addition, the source electrode and the drain electrode of the thin film transistor are designed to be not overlapped with the grid electrode, so that parasitic capacitance is reduced, and display performance is improved.
Drawings
The technical solution and other advantages of the present application will become apparent from the detailed description of the embodiments of the present application with reference to the accompanying drawings.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure;
fig. 2 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present disclosure;
fig. 3A-3E is a schematic view of a preparation process of an array substrate provided in an embodiment of the present application.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings, which are included to illustrate specific embodiments that can be implemented by the application. Directional phrases used in this application, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], etc., refer only to the directions of the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and understanding, and is in no way limiting. In the drawings, elements having similar structures are denoted by the same reference numerals.
The application aims at the technical problem that the display performance is influenced by RC delay due to overlarge parasitic capacitance generated by a thin film transistor of the existing array substrate, and the defect can be solved by the embodiment.
Referring to fig. 1, the array substrate provided in the present application includes: the substrate 10 may be a glass substrate or a flexible substrate; the thin film transistor layer 30 is arranged on the substrate 10 and comprises an inorganic film layer 301 and a thin film transistor 302 positioned in the inorganic film layer 301 in a stacked manner; the thin film transistor 302 includes an active layer 3021, a gate electrode 3022, a source electrode 3023, and a drain electrode 3024.
Wherein, the orthographic projection of the source 3023 and the drain 3024 on the substrate 10 is out of the range of the orthographic projection of the gate 3022 on the substrate 10. That is, the source 3023 and the drain 3024 both do not overlap the gate 3022. The overlapping area of the source electrode 3023 and the drain electrode 3024 with the gate electrode 3022 is reduced, so that the overlapping capacitance between the source electrode 3023 and the drain electrode 3024 and the gate electrode 3022 is reduced, and the problem of RC delay is effectively solved.
Specifically, as shown in fig. 1, a schematic structural diagram of an array substrate provided in the embodiment of the present application is shown. The array substrate includes:
a light shielding layer 20 disposed on the base substrate 10 at intervals; a buffer layer 3011 disposed on the light-shielding layer 20; an active layer 3021 disposed on the buffer layer 3011 corresponding to the light-shielding layer 20, wherein the light-shielding layer 20 is disposed to insulate the buffer layer 3011 from the active layer 3021, and the active layer 3021 includes a channel region 3021a and conductor regions 3021b located on both sides of the channel region 3021 a; a gate insulating pattern 3012 disposed on the active layer 3021 corresponding to the channel region 3021 a; a gate 3022 is located over the gate insulation block 3012, and the gate 3022 and the active layer 3021 are insulated from each other by the gate insulation block 3012; an interlayer insulating layer 3013 is provided over the gate electrode 3022, and a first via hole is formed at a position corresponding to the conductor region 3021 b; a source electrode 3023 and a drain electrode 3024 are disposed on the interlayer insulating layer 3013 and are respectively in electrical contact with the conductor regions 3021b at both ends of the active layer 3021 through the first via.
Since the material of the active layer 3021 corresponding to the channel region 3021a has a photosensitive property, the light shielding layer 20 covers at least the corresponding portion of the channel region 3021a, so as to prevent the channel region 3021a from being affected by the external ambient light and thus the display performance from being degraded.
Further, orthographic projections of the active layer 3021, the gate electrode 3022, the source electrode 3023, and the drain electrode 3024 of the thin film transistor 302 on the substrate 10 are all located within a range of the orthographic projection of the light shielding layer 20 on the substrate 10. The light shielding layer 20 has a light shielding performance, and can prevent the thin film transistor 302 from being affected by ambient light, self-luminescence of the AMOLED display panel, and the like, and thus reducing the display performance.
Wherein, the orthographic projection of the source 3023 and the drain 3024 on the substrate 10 is out of the range of the orthographic projection of the gate 3022 on the substrate 10. That is, the source 3023 and the drain 3024 do not overlap with the gate 3022, so that the overlap capacitance between the gate 3022 and both the source 3023 and the drain 3024 can be reduced, or the overlap capacitance between the gate 3022 and both the source 3023 and the drain 3024 can be reduced, and the RC delay problem can be effectively solved.
In the present embodiment, the gate electrode 3022 has a double-layer structure, and the gate electrode 3022 includes a first sub-gate layer 3022a and a second sub-gate layer 3022b stacked, and the second sub-gate layer 3022b is located above the first sub-gate layer 3022 a. The first sub-gate layer 3022a may be a transition metal material, which includes but is not limited to one or more alloy materials of molybdenum, titanium, tungsten, chromium, and nickel; the material of the second sub-gate layer 3022b is a metal material, which includes but is not limited to one or more alloy materials of copper and aluminum.
The first sub-gate layer 3022a may prevent a metal material (e.g., copper) in the second sub-gate layer 3022b from diffusing toward the active layer 3021 below to affect the electrical characteristics of the active layer 3021.
In this embodiment, the source electrode 3023 includes a first sub-source electrode layer 3023a and a second sub-source electrode layer 3023b that are stacked, the drain electrode 3024 includes a first sub-drain electrode layer 3024a and a second sub-drain electrode layer 3024b that are stacked, and the materials of the first sub-source electrode layer 3023a and the first sub-drain electrode layer 3024a each include one or more alloy materials of molybdenum, titanium, tungsten, chromium, and nickel, or are oxide semiconductor materials (such as ITO, IZO, AZO, and the like); the materials of the second sub-source electrode layer 3023b and the second sub-drain electrode layer 3024b each include one or more alloy materials selected from copper and aluminum.
In which the active layer 3021 is usually made of a material containing silicon, since the adhesion between the first sub-source layer 3023a and the first sub-drain layer 3024a and the active layer 3021 is stronger than that between the second sub-source layer 3023b and the second sub-drain layer 3024b, the contact characteristics between the source layer 3023 and the drain layer 3024 and the active layer 3021 can be improved by using a two-layer structure design.
The first sub-source layer 3023a and the first sub-drain layer 3024a can prevent the material (e.g., copper) in the metal on the upper layer from diffusing toward the active layer 3021 below to affect the electrical characteristics of the active layer 3021; on the other hand, when the first sub-source and drain electrode layers 3023a and 3024a are active metals or alloy materials containing active metals, especially active titanium metals, the active metals in the layers thereof may diffuse toward the underlying active layer 3021, thereby enhancing the electrical characteristics of the active layer 3021.
In the array substrate of the present application, further comprising: a passivation layer 40 and a planarization layer 50 disposed over the source electrode 3023 and the drain electrode 3024, the passivation layer 40 and the planarization layer 50 having a second via hole formed at a position corresponding to the drain electrode 3024; the pixel electrode 60 is disposed on the planarization layer 50 and electrically connected to the drain electrode 3024 through the second via hole; the pixel defining layer 70 is disposed on the pixel electrode 60 and defines a pixel region.
Wherein, an organic light emitting layer and a cathode layer can be prepared in the pixel region, so that the array substrate forms an OLED display panel.
The present application further provides a method for manufacturing an array substrate, which is shown in fig. 2 and fig. 3A to 3E, and the method includes the following steps:
in step S10, as shown in fig. 3A to 3B, a patterned light-shielding layer 20, a buffer layer 3011, and a patterned active layer 3021 are sequentially formed on the base substrate 10, and the active layer 3021 includes a channel region and conductor regions located on both sides of the channel region.
The light-shielding layer 20 may be a single layer of Mo, Al, Cu, Ti, W, Cr, Ni, or a metal alloy thereof, or a double-layer combination of the above materials, with a thickness of 500-2000A. The active layer 3021 may be IGZO, ITZO, IGZTO, or the like.
In step S20, as shown in fig. 3C, a gate insulating layer and a gate layer are sequentially formed on the active layer 3021 and patterned to form a gate insulating pattern 3012 corresponding to the channel region and a gate 3022 on the gate insulating pattern 3012.
In step S20, the gate insulating layer and the gate layer are patterned by a photolithography process, and the gate insulating patterns 3012 and the gate 3022 are formed at the same time.
After the step S20, the method further includes the steps of: a conductor process is performed on portions of the active layer 3021 corresponding to both sides of the channel region 3021a, so as to form a conductor region 3021b of the active layer 3021.
In the present embodiment, the gate electrode 3022 has a double-layer structure, the gate electrode 3022 includes a first sub-gate layer 3022a and a second sub-gate layer 3022b stacked together, and the material of the first sub-gate layer 3022a includes, but is not limited to, one or more alloy materials of molybdenum, titanium, tungsten, chromium, and nickel; the material of the second sub-gate layer 3022b includes, but is not limited to, one or more alloy materials of copper and aluminum.
In step S30, as shown in fig. 3D, an interlayer insulating layer 3013 is formed on the gate electrode 3022 and patterned to form a first via hole 3013a corresponding to the conductor region 3021 b.
In step S40, as shown in fig. 3E, a source/drain electrode layer is formed on the interlayer insulating layer 3013 and patterned to form a source 3023 and a drain 3024 electrically contacting the conductor region 3021b of the active layer 3021, and the orthographic projections of the source 3023 and the drain 3024 on the substrate 10 are both outside the range of the orthographic projection of the gate 3022 on the substrate 10.
In this embodiment, the source electrode 3023 includes a first sub-source electrode layer 3023a and a second sub-source electrode layer 3023b that are stacked, the drain electrode 3024 includes a first sub-drain electrode layer 3024a and a second sub-drain electrode layer 3024b that are stacked, and the materials of the first sub-source electrode layer 3023a and the first sub-drain electrode layer 3024a each include one or more alloy materials of molybdenum, titanium, tungsten, chromium, and nickel, or are oxide semiconductor materials (such as ITO, IZO, AZO, and the like); the materials of the second sub-source electrode layer 3023b and the second sub-drain electrode layer 3024b each include one or more alloy materials selected from copper and aluminum.
The manufacturing method further includes sequentially manufacturing a passivation layer, a planarization layer, a pixel electrode, a pixel defining layer, and the like on the source electrode 3023 and the drain electrode 3024.
The source 3023 and the drain 3024 of the present application do not overlap with the gate 3022, and therefore, the overlap capacitance between the gate 3022 and both the source 3023 and the drain 3024 can be reduced, or the overlap capacitance between the gate 3022 and both the source 3023 and the drain 3024 can be reduced, so that the RC delay problem can be effectively solved.
In summary, although the present application has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present application, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present application, so that the scope of the present application shall be determined by the appended claims.
Claims (10)
1. An array substrate, comprising:
a substrate base plate;
the thin film transistor layer is arranged on the substrate and comprises an inorganic film layer and a thin film transistor positioned in the inorganic film layer in a stacked mode;
the thin film transistor comprises an active layer, a grid electrode, a source electrode and a drain electrode;
wherein, the orthographic projections of the source electrode and the drain electrode on the substrate base plate are both positioned outside the range of the orthographic projection of the grid electrode on the substrate base plate.
2. The array substrate of claim 1, further comprising a patterned light-shielding layer disposed between the active layer and the substrate and insulated from the active layer by a buffer layer.
3. The array substrate of claim 2, wherein an orthographic projection of the thin film transistor on the substrate is within a range of an orthographic projection of the light shielding layer on the substrate.
4. The array substrate of claim 1, wherein the active layer comprises a channel region and conductor regions on two sides of the channel region, a gate insulating pattern is disposed on the active layer corresponding to the channel region, and the gate and the active layer are insulated by the gate insulating pattern.
5. The array substrate of claim 4, wherein an interlayer insulating layer is disposed on the gate electrode, a first via hole is disposed on the interlayer insulating layer corresponding to the conductor region, and the source electrode and the drain electrode are electrically contacted with the conductor region through the first via hole, respectively.
6. The array substrate of claim 1, wherein the gate comprises a first sub-gate layer and a second sub-gate layer which are stacked, the second sub-gate layer is located on the first sub-gate layer, the material of the first sub-gate layer comprises one or more alloy materials of molybdenum, titanium, tungsten, chromium and nickel, and the material of the second sub-gate layer comprises one or more alloy materials of copper and aluminum.
7. The array substrate of claim 1, wherein the source electrode comprises a first and a second laminated sub-source electrode layers, the drain electrode comprises a first and a second laminated sub-drain electrode layers, and the material of the first sub-source electrode layer and the first sub-drain electrode layer comprises one or more alloy materials selected from molybdenum, titanium, tungsten, chromium and nickel, or is an oxide semiconductor material; the second sub-source electrode layer and the second sub-drain electrode layer are made of one or more alloy materials of copper and aluminum.
8. A preparation method of an array substrate is characterized by comprising the following steps:
step S10, sequentially forming a patterned light shielding layer, a buffer layer and a patterned active layer on a substrate, wherein the active layer comprises a channel region and conductor regions positioned on two sides of the channel region;
step S20, sequentially forming a gate insulating layer and a gate layer on the active layer, and patterning the gate insulating layer and the gate layer to form a gate insulating pattern corresponding to the channel region and a gate electrode on the gate insulating pattern;
step S30, forming an interlayer insulating layer on the gate electrode and patterning the interlayer insulating layer to form a first via hole corresponding to the conductor region;
step S40, forming a source drain electrode layer on the interlayer insulating layer and patterning the source drain electrode layer to form a source electrode and a drain electrode electrically contacting the conductor region of the active layer, where the orthographic projections of the source electrode and the drain electrode on the substrate are both outside the range of the orthographic projection of the gate electrode on the substrate.
9. The method for manufacturing a semiconductor device according to claim 8, wherein in step S20, the gate insulating layer and the gate layer are patterned by a photolithography process to form the gate insulating pattern and the gate electrode simultaneously.
10. The method for preparing as claimed in claim 9, wherein after the step S20, the method further comprises the steps of: and conducting a conductor process on the parts of the active layer corresponding to the two sides of the channel region to form a conductor region of the active layer.
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| CN111916492A (en) * | 2020-08-31 | 2020-11-10 | 武汉华星光电技术有限公司 | TFT device, preparation method thereof and array substrate |
| CN112002764A (en) * | 2020-08-11 | 2020-11-27 | Tcl华星光电技术有限公司 | TFT device and preparation method thereof, and TFT array substrate |
| CN112864174A (en) * | 2021-01-12 | 2021-05-28 | 京东方科技集团股份有限公司 | TFT array substrate, preparation method thereof and display device |
| CN113064298A (en) * | 2021-03-01 | 2021-07-02 | Tcl华星光电技术有限公司 | Display panel and preparation method thereof |
| CN113193048A (en) * | 2021-04-26 | 2021-07-30 | 深圳市华星光电半导体显示技术有限公司 | Thin film transistor and preparation method thereof |
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| JP2023542562A (en) * | 2021-08-25 | 2023-10-11 | 深▲セン▼市▲華▼星光▲電▼半▲導▼体▲顕▼示技▲術▼有限公司 | Thin film transistor array substrate and manufacturing method thereof |
| JP7480167B2 (en) | 2021-08-25 | 2024-05-09 | 深▲セン▼市▲華▼星光▲電▼半▲導▼体▲顕▼示技▲術▼有限公司 | Thin film transistor array substrate and its manufacturing method |
| CN113871346A (en) * | 2021-09-24 | 2021-12-31 | 深圳市华星光电半导体显示技术有限公司 | Array substrate and preparation method thereof and display panel |
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