CN110034131A - Array substrate and its manufacturing method, display panel and display device - Google Patents

Abstract

An embodiment of the present invention provides an array substrate, comprising: a base substrate, an active layer, a gate, a source electrode and a drain electrode sequentially arranged on the base substrate, and also includes a shielding layer, located on the base substrate and the active layer between layers. The outer contour of the orthographic projection area of the shielding layer on the base substrate is larger than the outer contour of the orthographic projection area of the active layer on the base substrate. and the shielding layer is provided with a first via hole, and the position of the first via hole corresponds to the position where the source electrode contacts the active layer; and/or the shielding layer is provided with a second via hole, and the position of the second via hole corresponds to the position of the drain electrode Corresponds to the position where the active layer is in contact. The embodiment of the present invention also discloses a manufacturing method of a display panel, a display device and an array substrate. Since the outer contour of the shielding layer in the embodiment of the present invention is larger than that of the active layer, the shielding effect of the shielding layer is enhanced. Meanwhile, the shielding layer is provided with a first via hole and/or a second via hole, so as to avoid the generation of parasitic capacitance between the source, the drain and the shielding layer.

Description

Array substrate and manufacturing method thereof, display panel and display device

technical field

The present invention relates to the field of display technology, in particular to an array substrate and a manufacturing method thereof, a display panel and a display device.

Background technique

A traditional display panel includes an array substrate and a color filter substrate arranged oppositely. The array substrate includes a plurality of thin film transistors. When the active layer included in the thin film transistor is exposed to light, its characteristics are prone to drift, which affects the normal use of the thin film transistor. In order to prevent ambient light from being directly or indirectly irradiated to the active layer, a shielding layer is usually arranged below the active layer to block the ambient light from being irradiated.

The inventor found that the current shielding layer only corresponds to the position of the channel region of the active layer, and does not shield the entire active layer area, so that the active layer is easily exposed to ambient light, thereby affecting the thin film. characteristics of transistors.

SUMMARY OF THE INVENTION

In view of this, the present invention provides an array substrate and a manufacturing method thereof, a display panel and a display device, which solve the technical problem in the prior art that the active layer is easily irradiated by ambient light, thereby affecting the characteristics of the thin film transistor.

In order to solve the above problems, the embodiments of the present invention mainly provide the following technical solutions:

In a first aspect, an embodiment of the present invention discloses an array substrate, comprising: a base substrate, an active layer, a gate electrode, a source electrode and a drain electrode sequentially arranged on the base substrate, and further includes a shielding layer , located between the base substrate and the active layer;

The outer contour of the orthographic projection area of the shielding layer on the base substrate is larger than the outer contour of the orthographic projection area of the active layer on the base substrate; and

The shielding layer is provided with a first via hole, and the position of the first via hole corresponds to the position where the source electrode contacts the active layer; and/or,

The shielding layer is provided with a second via hole, and the position of the second via hole corresponds to the position where the drain electrode contacts the active layer.

Optionally, the area of the orthographic projection area of the shielding layer on the base substrate is larger than the area of the orthographic projection area of the active layer on the base substrate.

Optionally, the outer contour of the orthographic projection area of the first via on the base substrate is greater than or equal to the outer contour of the orthographic projection area of the source via on the base substrate;

The outer contour of the orthographic projection area of the second via hole on the base substrate is greater than or equal to the outer contour of the orthographic projection area of the drain via hole on the base substrate.

Optionally, an orthographic projection area of the first via hole on the base substrate is greater than or equal to an orthographic projection area of a region where the source electrode is in contact with the active layer on the base substrate.

Optionally, an orthographic projection area of the second via hole on the base substrate is greater than or equal to an orthographic projection area of a region where the drain electrode is in contact with the active layer on the base substrate.

Optionally, the orthographic projection area of the first via hole on the base substrate is equal to the orthographic projection area of the second via hole on the base substrate.

Optionally, a common electrode line is also included, the common electrode line and the shielding layer are located on the same layer, and are electrically connected to the shielding layer.

Optionally, the common electrode line and the shielding layer have an integral structure.

Optionally, it further includes: a common electrode line, an insulating layer between the active layer and the shielding layer, and a gate insulating layer between the active layer and the gate;

The common electrode line is located on the same layer as the gate, and is electrically connected to the shielding layer through a third via hole penetrating the insulating layer and the gate insulating layer.

Optionally, the material of the shielding layer is at least one of copper, aluminum, molybdenum, titanium, chromium and tungsten.

In a second aspect, an embodiment of the present invention discloses a display panel including the array substrate described in the first aspect.

In a third aspect, an embodiment of the present invention discloses a display device, including the display panel described in the second aspect.

In a fourth aspect, an embodiment of the present invention discloses a method for manufacturing an array substrate, including the fabrication of an active layer, a gate electrode, a source electrode and a drain electrode, and further including:

A shielding layer is fabricated on the base substrate through a patterning process, and the outer contour of the orthographic projection area of the shielding layer on the base substrate is larger than the outer contour of the orthographic projection area of the active layer on the base substrate ;

A first via hole and/or a second via hole are formed on the shielding layer. The position of the first via hole corresponds to the position where the source electrode contacts the active layer. The position corresponds to the position where the drain electrode is in contact with the active layer.

Optionally, after forming the first via hole and/or the second via hole on the shielding layer, the method specifically includes:

making an insulating layer on the shielding layer;

An active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source electrode and a drain electrode are sequentially fabricated on the insulating layer through a patterning process.

Optionally, the method further includes making a common electrode line, and the common electrode line and the shielding layer are made by the same patterning process;

Or, the common electrode line and the gate electrode are formed by the same patterning process.

With the above technical solutions, the technical solutions provided by the embodiments of the present invention have at least the following advantages:

Since the outer contour of the orthographic projection area of the shielding layer on the base substrate included in the array substrate of the embodiment of the present invention is larger than the outer contour of the orthographic projection area of the active layer on the base substrate, the shielding layer can affect the entire active layer. The area of the shielding layer is shielded to prevent the active layer from being irradiated by ambient light, thereby improving the characteristics of the thin film transistor; in addition, since the shielding layer is provided with a first via hole in the embodiment of the present invention, the position of the first via hole is the same as the source electrode and the source electrode. The position where the active layer is in contact with the active layer can reduce the parasitic capacitance between the source electrode and the shielding layer at the contact position with the active layer; Corresponding to the position in contact with the active layer, the parasitic capacitance between the drain and the shielding layer at the position in contact with the active layer can be reduced, and the performance of the array substrate can be improved.

The above description is only an overview of the technical solutions of the embodiments of the present invention. In order to understand the technical means of the embodiments of the present invention more clearly, it can be implemented according to the contents of the description, and in order to make the above and other purposes, features and The advantages can be more obvious and easy to understand, and the following specific implementations of the embodiments of the present invention are given.

Description of drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of alternative embodiments. The drawings are only for the purpose of illustrating alternative embodiments, and are not considered to be limitations of the embodiments of the present invention. Also, the same components are denoted by the same reference numerals throughout the drawings. In the attached image:

FIG. 1 is a schematic structural diagram of an array substrate in the prior art;

Fig. 2 is the sectional view along A-A' line in Fig. 1;

FIG. 3 is a schematic structural diagram of a first embodiment of an array substrate according to an embodiment of the present invention;

Fig. 4 is the sectional view along A-A' line among Fig. 3;

FIG. 5 is a schematic structural diagram of a second embodiment of an array substrate according to an embodiment of the present invention;

Fig. 6 is the sectional view along A-A' line among Fig. 5;

Fig. 7 is a sectional view along the line B-B' in Fig. 5;

Fig. 8 is a cross-sectional view along line C-C' in Fig. 5;

FIG. 9 is a schematic structural diagram of a third embodiment of an array substrate according to an embodiment of the present invention;

Figure 10 is a sectional view along the line A-A' in Figure 9;

Figure 11 is a sectional view along the line B-B' in Figure 9;

Figure 12 is a cross-sectional view along line C-C' in Figure 9;

FIG. 13 is a flowchart of a method for manufacturing an array substrate according to an embodiment of the present invention.

Reference numerals are introduced as follows:

1-substrate; 2-shielding layer; 3-insulating layer; 4-active layer; 5-gate insulating layer; 6-gate; 7-interlayer insulating layer; 8-source electrode; 9-drain electrode ;

10-passivation layer; 11-pixel electrode; 12-data line; 13-gate line; 14-common electrode line; 15-first via hole; 16-second via hole; 17-via hole; 171-third Via hole; 18-common electrode; 19-second insulating layer.

Detailed ways

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure will be more thoroughly understood, and will fully convey the scope of the present disclosure to those skilled in the art.

It will be understood by those skilled in the art that the singular forms "a", "an", "the" and "the" as used herein can include the plural forms as well, unless expressly stated otherwise. It should be further understood that the word "comprising" used in the specification of this application refers to the presence of stated features, integers, steps, operations, elements and/or components, but does not preclude the presence or addition of one or more other features, Integers, steps, operations, elements, components and/or groups thereof. It will be understood that when we refer to an element as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. Also, "connection" as used herein may include wireless connections. As used herein, the term "and/or" includes all or any element and all combination of one or more of the associated listed items.

It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It should also be understood that terms, such as those defined in a general dictionary, should be understood to have meanings consistent with their meanings in the context of the prior art and, unless specifically defined as herein, should not be interpreted in idealistic or overly formal meaning to explain.

The inventor has studied the structure of the thin film transistor included in the array substrate in the prior art, as shown in FIG. 1 and FIG. 2 , FIG. 1 is a plan view of the array substrate in the prior art, and FIG. ' line cross-sectional view, the base substrate 1 is sequentially provided with a shielding layer 2, an insulating layer 3, an active layer 4, a gate insulating layer 5, a gate 6, an interlayer insulating layer 7, a source electrode 8, and a drain electrode 9 , passivation layer 10, pixel electrode 11, wherein, the data line 12 and the source 8 are located in the same layer, and connected to the source 8;

The inventor found that in the prior art, if the area of the orthographic projection area of the shielding layer 2 on the base substrate 1 is greater than or equal to the area of the orthographic projection area of the active layer 4 on the base substrate 1, the source electrode 8 and the The distance between the contact position of the source layer 4 and the shielding layer 2 is close, and the parasitic capacitance between the two is relatively large. Similarly, the distance between the contact position of the drain 9 and the active layer 4 and the shielding layer 2 is close, and the two The parasitic capacitance between them is also relatively large, which will affect the performance of the array substrate.

Therefore, the inventor found that the shielding layer 2 in the prior art only shields the channel region of the active layer 4. However, such a design method makes the shielding layer 2 unable to shield the entire region of the active layer 4, so that the active layer 4 cannot be shielded by the shielding layer 2. Layer 4 is susceptible to ambient light, which affects the characteristics of the thin film transistor.

In order to solve the above technical problems existing in the prior art, embodiments of the present invention provide a new array substrate structure.

An embodiment of the present invention provides an array substrate. As shown in FIG. 3 to FIG. 12 , the array substrate includes: a base substrate 1 and an active layer 4 , a gate 6 , and a source electrode that are sequentially arranged on the base substrate 1 8 and drain 9 , the array substrate further includes a shielding layer 2 located between the base substrate 1 and the active layer 4 . The outer contour of the orthographic projection area of the shielding layer 2 on the base substrate 1 is larger than the outer contour of the orthographic projection area of the active layer 4 on the base substrate 1 . The shielding layer 2 is provided with a first via hole 15, and the position of the first via hole 15 corresponds to the position where the source electrode 8 is in contact with the active layer 4; and/or, the shielding layer 2 is provided with a second via hole 16, the second via hole The position of the hole 16 corresponds to the position where the drain electrode 9 is in contact with the active layer 4 .

Since the outer contour of the orthographic projection area of the shielding layer 2 on the base substrate 1 included in the array substrate of the embodiment of the present invention is larger than the outer contour of the orthographic projection area of the active layer 4 on the base substrate 1, the shielding layer 2 The entire area of the active layer 4 can be shielded to prevent the active layer 4 from being irradiated by ambient light, thereby improving the characteristics of the thin film transistor; The position of a via hole 15 corresponds to the position where the source electrode 8 is in contact with the active layer 4, so that the parasitic capacitance between the source electrode 8 and the shielding layer 2 at the contact position with the active layer 4 can be reduced; and, the shielding layer 2 A second via hole 16 is provided, and the position of the second via hole 16 corresponds to the position where the drain 9 is in contact with the active layer 4 , which can reduce the gap between the drain 9 and the shielding layer 2 at the contact position with the active layer 4 the parasitic capacitance, and improve the performance of the array substrate.

The array substrate provided by the embodiments of the present invention is described in detail below through several specific embodiments.

3 and 4 are schematic structural diagrams of the first embodiment of the array substrate according to the embodiment of the present invention, FIG. 3 is a plan structure view of the first embodiment of the present invention, and FIG. sectional view.

As shown in FIG. 3 and FIG. 4 , the array substrate includes a base substrate 1 , an active layer 4 , a gate 6 , a source 8 and a drain 9 arranged on the base substrate 1 in sequence, and also includes a shielding layer 2, located between the base substrate 1 and the active layer 4 . The outer contour of the orthographic projection area of the shielding layer 2 on the base substrate 1 is larger than the outer contour of the orthographic projection area of the active layer 4 on the base substrate 1 . The shielding layer 2 is provided with a first via hole 15 , and the position of the first via hole 15 corresponds to the position where the source electrode 8 contacts the active layer 4 .

Usually, the frequency of signal change on the data line 12 is very high. When the data line 12 is connected to the source electrode 8, the distance between the contact position of the source electrode 8 and the active layer 4 and the shielding layer 2 is close, and the parasitic capacitance between the two It is relatively large, which affects the transmission of the signal of the data line 12 and causes the distortion and deformation of the signal of the data line. However, in the embodiment of the present invention, at the position where the source electrode 8 contacts the active layer 4 , the shielding layer 2 is provided with the first via hole 15 , thereby reducing the contact between the source electrode 8 and the shielding layer 2 at the position where the source electrode 8 contacts the active layer 4 . The parasitic capacitance between them reduces the load of the data line 12 .

Optionally, the area of the orthographic projection area of the shielding layer 2 on the base substrate 1 is larger than the area of the orthographic projection area of the active layer 4 on the base substrate 1; in this way, the shielding layer 2 can completely block the active layer. 4. Improve the shielding effect, further prevent the active layer 4 from being irradiated by ambient light, and improve the characteristics of the thin film transistor.

Optionally, usually, before making the source electrode, it is necessary to make a source electrode via hole passing through the gate insulating layer 5 and the interlayer insulating layer 7, so that after the source electrode is fabricated, the source electrode can pass through the source electrode via hole and the active electrode. Layer 4 is electrically connected. In order to achieve the technical effect of this embodiment, the outer contour of the orthographic projection area of the first via hole 15 on the base substrate 1 is greater than or equal to the outer contour of the orthographic projection area of the source via hole on the base substrate 1 .

Optionally, the orthographic projection area of the first via hole 15 on the base substrate 1 is greater than or equal to the orthographic projection area of the area where the source electrode 8 is in contact with the active layer 4 on the base substrate 1; in this way, the source electrode 8 is No parasitic capacitance can be generated at the position in contact with the active layer 4, which further reduces the influence of the parasitic capacitance on the signal transmission of the data line.

5 to 8 are schematic structural diagrams of a second embodiment of an array substrate according to an embodiment of the present invention, FIG. 5 is a plan structure view of the second embodiment of the present invention, and FIG. 6 is a line along AA' in FIG. 5 . Figure 7 is a cross-sectional view taken along line BB' in Figure 5, and Figure 8 is a cross-sectional view taken along line CC' in Figure 5.

As shown in FIG. 5 and FIG. 6 , the array substrate includes a base substrate 1 , an active layer 4 , a gate 6 , a source electrode 8 and a drain electrode 9 sequentially arranged on the base substrate 1 , and also includes a shielding layer 2, located between the base substrate 1 and the active layer 4 . The outer contour of the orthographic projection area of the shielding layer 2 on the base substrate 1 is larger than the outer contour of the orthographic projection area of the active layer 4 on the base substrate 1 . The shielding layer 2 is provided with a first via hole 15 , and the position of the first via hole 15 corresponds to the position where the source electrode 8 contacts the active layer 4 .

As shown in FIG. 5 , FIG. 7 and FIG. 8 , the array substrate further includes common electrode lines 14 , and the common electrode lines 14 are located on the same layer as the shielding layer 2 and are electrically connected to the shielding layer 2 . Since the common electrode line 14 is electrically connected to the shielding layer 2, the static charge accumulated on the shielding layer 2 can be dispersed by the common electrode line 14, which can prevent the electrostatic charge accumulated on the shielding layer 2 from affecting the characteristics of the thin film transistor.

Optionally, the common electrode line 14 and the shielding layer 2 have an integral structure, which can reduce manufacturing difficulty and improve market competitiveness.

9 to 12 respectively show schematic structural diagrams of a third embodiment of an array substrate according to an embodiment of the present invention, FIG. 9 is a plan structural view of the third embodiment of the present invention, and FIG. 10 is a line along AA' in FIG. 9 . Line cross-sectional view, FIG. 11 is a cross-sectional view taken along line BB' in FIG. 9, and FIG. 12 is a cross-sectional view taken along line CC' in FIG. 9.

As shown in FIG. 9 and FIG. 10 , the array substrate includes a base substrate 1 , an active layer 4 , a gate 6 , a source electrode 8 and a drain electrode 9 sequentially arranged on the base substrate 1 , and also includes a shielding layer 2, located between the base substrate 1 and the active layer 4 . The outer contour of the orthographic projection area of the shielding layer 2 on the base substrate 1 is larger than the outer contour of the orthographic projection area of the active layer 4 on the base substrate 1 . The shielding layer 4 is provided with a first via hole 15, and the position of the first via hole 15 corresponds to the position where the source electrode 8 contacts the active layer 4, and the shielding layer 2 is provided with a second via hole 16. The position corresponds to the position where the drain electrode 9 is in contact with the active layer 4 .

Optionally, the orthographic projection area of the second via hole 16 on the base substrate 1 is greater than or equal to the orthographic projection area of the area where the drain 9 contacts the active layer 4 on the base substrate 1; in this way, the drain 9 No parasitic capacitance can be generated at the position in contact with the active layer 4, which further reduces the influence of the parasitic capacitance on the signal transmission of the data line.

Optionally, usually, before making the source electrode, it is necessary to make a source electrode via hole passing through the gate insulating layer 5 and the interlayer insulating layer 7, so that after the source electrode is fabricated, the source electrode can pass through the source electrode via hole and the active electrode. Layer 4 is electrically connected. In order to achieve the technical effect of this embodiment, the outer contour of the orthographic projection area of the first via hole 15 on the base substrate 1 is greater than or equal to the outer contour of the orthographic projection area of the source via hole on the base substrate 1 .

Similarly, usually, before the drain is fabricated, a drain via hole penetrating the gate insulating layer 5 and the interlayer insulating layer 7 needs to be fabricated, so that after the drain is fabricated, the drain can pass through the drain via hole and the active layer. 4 Electrical connections. In order to achieve the technical effect of this embodiment, the outer contour of the orthographic projection area of the second via hole 16 on the base substrate 1 is greater than or equal to the outer contour of the orthographic projection area of the drain via hole on the base substrate 1 .

Optionally, the orthographic projection area of the first via hole 15 on the base substrate 1 is equal to the orthographic projection area of the second via hole 16 on the base substrate 1 . Equalizing the orthographic projection areas of the first via hole 15 and the second via hole 16 can reduce manufacturing difficulty and cost and improve market competitiveness.

As shown in FIG. 9 , FIG. 11 and FIG. 12 , the array substrate further includes a common electrode line 14 , and an insulating layer 3 between the active layer 4 and the shielding layer 2 and between the active layer 4 and the gate 6 The common electrode line 14 and the gate 6 are located on the same layer, and are electrically connected to the shielding layer 2 through the third via 171 penetrating the insulating layer 3 and the gate insulating layer 5 . Since the common electrode line 14 is electrically connected to the shielding layer 2, the static charge accumulated on the shielding layer 2 can be dispersed by the common electrode line 14, which can prevent the electrostatic charge accumulated on the shielding layer 2 from affecting the characteristics of the thin film transistor.

Specifically, as shown in FIG. 4 , FIG. 6 , FIG. 7 , FIG. 8 , FIG. 10 , FIG. 11 , and FIG. 12 , the array substrate further includes: an interlayer insulating layer 7 located on the gate electrode 6 , an interlayer insulating layer located on the gate electrode 6 , 7 , the passivation layer 10 on the passivation layer 10 , the pixel electrode 11 on the passivation layer 10 , the second insulating layer 19 on the pixel electrode 11 , and the common electrode 18 on the second insulating layer 19 .

As shown in FIG. 7 , the common electrode 18 is connected to the common electrode line 14 through a via hole penetrating the second insulating layer 19 , the passivation layer 10 , the interlayer insulating layer 7 , the gate insulating layer 5 and the insulating layer 3 . As shown in FIG. 11 , the common electrode 18 is connected to the common electrode line 14 through a via hole passing through the second insulating layer 19 , the passivation layer 10 and the interlayer insulating layer 7 .

Optionally, the material of the shielding layer 2 is at least one of copper (Cu), aluminum (Al), molybdenum (Mo), titanium (Ti), chromium (Cr) and tungsten (W). Specifically, one of copper, aluminum, molybdenum, titanium, chromium and tungsten can be selected, and alloy materials of these materials can also be selected. The shielding layer 2 can be a single-layer metal structure or a multi-layer metal structure, such as: The multi-layer metal of molybdenum, aluminum and molybdenum can be used, the multi-layer metal of titanium, copper and titanium can also be used, and the multi-layer metal of molybdenum, titanium and copper can also be used.

In the embodiment of the present invention, similar to the material of the shielding layer 2, the gate electrode 6, the source electrode 8, and the drain electrode 9 may use at least one of copper, aluminum, molybdenum, titanium, chromium, and tungsten, or may use any of these materials. alloy. The gate electrode 6, the source electrode 8, and the drain electrode 9 may adopt a single-layer metal structure, or may adopt a multi-layer metal structure.

In the embodiment of the present invention, the active layer 4 may be made of amorphous silicon, polysilicon, or oxide material.

In the embodiment of the present invention, the pixel electrode 11 and the common electrode 18 may be indium tin oxide (ITO) or indium zinc oxide (IZO).

In the embodiment of the present invention, the gate insulating layer 5 may be silicon nitride or silicon oxide. The gate insulating layer 5 can be a single-layer structure or a multi-layer structure, such as a double-layer structure of silicon nitride and silicon oxide.

In the embodiment of the present invention, the interlayer insulating layer 7 may be silicon nitride or silicon oxide. The interlayer insulating layer 7 may have a single-layer structure or a multi-layer structure.

In the embodiment of the present invention, the passivation layer 10 may be silicon nitride or silicon oxide. The passivation layer 10 may have a single-layer structure or a multi-layer structure.

In this embodiment of the present invention, the insulating layer 3 and the second insulating layer 19 may be silicon nitride or silicon oxide. The first insulating layer 3 and the second insulating layer 19 may have a single-layer structure or a multi-layer structure.

Based on the same inventive concept, an embodiment of the present invention further discloses a display panel including the above-mentioned array substrate. Since the display panel includes the above-mentioned array substrate, the display panel has the same beneficial effects as the array substrate. Therefore, the beneficial effects of the display panel are not repeated here.

Based on the same inventive concept, an embodiment of the present invention further discloses a display device, including the above-mentioned display panel. Since the display device includes the above-mentioned display panel, the display device has the same beneficial effects as the display panel. Therefore, the beneficial effects of the display device are not repeated here.

Based on the same inventive concept, an embodiment of the present invention also discloses a method for fabricating an array substrate, including fabrication of an active layer, a gate electrode, a source electrode and a drain electrode. And, as shown in FIG. 13 , the manufacturing method of the array substrate further includes:

S101 : forming a shielding layer on the base substrate through a patterning process, the outer contour of the orthographic projection area of the shielding layer on the base substrate is larger than the outer contour of the orthographic projection area of the active layer on the base substrate.

S102: Form a first via hole and/or a second via hole on the shielding layer, the position of the first via hole corresponds to the position where the source electrode contacts the active layer, and the position of the second via hole corresponds to the position of the drain electrode and the active layer The location of the contact corresponds.

Optionally, after the foregoing S102, the embodiment of the present invention specifically includes:

Make an insulating layer over the shield.

An active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source electrode and a drain electrode are sequentially fabricated on the insulating layer through a patterning process. The specific fabrication methods of the active layer, the gate insulating layer, the gate electrode, the interlayer insulating layer, the source electrode and the drain electrode according to the embodiment of the present invention are similar to those in the prior art, and will not be repeated here.

Optionally, the manufacturing method of the array substrate according to the embodiment of the present invention further includes the fabrication of common electrode lines. Specifically, the common electrode lines and the shielding layer are fabricated and formed by the same patterning process. Alternatively, the common electrode line and the gate electrode are formed by the same patterning process.

The beneficial effects obtained by applying the embodiments of the present invention include:

1. Since the outer contour of the orthographic projection area of the shielding layer on the base substrate included in the array substrate of the embodiment of the present invention is larger than the outer contour of the orthographic projection area of the active layer on the base substrate, the shielding layer can cover the entire The area of the active layer is shielded to prevent the active layer from being irradiated by ambient light, thereby improving the characteristics of the thin film transistor; A via hole, which can reduce the parasitic capacitance between the source electrode and the shielding layer at the contact position with the active layer; and, at the position where the drain electrode contacts the active layer, the shielding layer is provided with a second via hole, so that The parasitic capacitance between the drain and the shielding layer at the contact position with the active layer can be reduced, and the performance of the array substrate can be improved.

2. The orthographic projection area of the first via on the base substrate is greater than or equal to the orthographic projection area of the area where the source electrode contacts the active layer on the base substrate; in this way, the source electrode and the active layer are in contact with each other. No parasitic capacitance can be generated, which further reduces the influence of the parasitic capacitance on the signal transmission of the data line.

3. Since the common electrode line is electrically connected to the shielding layer, the electrostatic charge accumulated on the shielding layer can be dispersed through the common electrode line, which can prevent the electrostatic charge accumulated on the shielding layer from affecting the characteristics of the thin film transistor.

The above are only some embodiments of the present invention. It should be pointed out that for those skilled in the art, without departing from the principles of the present invention, several improvements and modifications can be made. It should be regarded as the protection scope of the present invention.

Claims (15)

1. An array substrate, comprising: a base substrate and an active layer, a gate electrode, a source electrode and a drain electrode sequentially arranged on the base substrate, characterized in that it also includes a shielding layer, located on the substrate between the substrate and the active layer; The outer contour of the orthographic projection area of the shielding layer on the base substrate is larger than the outer contour of the orthographic projection area of the active layer on the base substrate; and The shielding layer is provided with a first via hole, and the position of the first via hole corresponds to the position where the source electrode contacts the active layer; and/or, The shielding layer is provided with a second via hole, and the position of the second via hole corresponds to the position where the drain electrode contacts the active layer. 2 . The array substrate according to claim 1 , wherein an area of an orthographic projection area of the shielding layer on the base substrate is larger than an area of an orthographic projection area of the active layer on the base substrate. 3 . area. 3 . The array substrate of claim 1 , wherein the outer contour of the orthographic projection area of the first via hole on the base substrate is greater than or equal to that of the source via hole on the base substrate 3 . The outer contour of the orthographic projection area; The outer contour of the orthographic projection area of the second via hole on the base substrate is greater than or equal to the outer contour of the orthographic projection area of the drain via hole on the base substrate. 4 . The array substrate according to claim 1 , wherein the orthographic projection area of the first via hole on the base substrate is greater than or equal to the area where the source electrode is in contact with the active layer. 5 . orthographic projection area on the base substrate. 5 . The array substrate according to claim 1 , wherein the orthographic projection area of the second via hole on the base substrate is greater than or equal to the area where the drain electrode is in contact with the active layer. 6 . orthographic projection area on the base substrate. 6 . The array substrate of claim 1 , wherein an orthographic projection area of the first via hole on the base substrate is equal to an orthographic projection area of the second via hole on the base substrate 6 . area. 7 . The array substrate according to claim 1 , further comprising a common electrode line, the common electrode line and the shielding layer being located on the same layer and electrically connected to the shielding layer. 8 . 8 . The array substrate of claim 7 , wherein the common electrode line and the shielding layer are integral structures. 9 . 9 . The array substrate of claim 1 , further comprising: a common electrode line, and an insulating layer located between the active layer and the shielding layer, and located between the active layer and the shielding layer. 10 . gate insulating layer between gates; The common electrode line is located on the same layer as the gate, and is electrically connected to the shielding layer through a third via hole penetrating the insulating layer and the gate insulating layer. 10 . The array substrate of claim 1 , wherein the shielding layer is made of at least one of copper, aluminum, molybdenum, titanium, chromium and tungsten. 11 . 11. A display panel, comprising the array substrate according to any one of claims 1-10. 12. A display device, comprising the display panel according to claim 11. 13. A method for manufacturing an array substrate, comprising the fabrication of an active layer, a gate electrode, a source electrode and a drain electrode, further comprising: A shielding layer is fabricated on the base substrate through a patterning process, and the outer contour of the orthographic projection area of the shielding layer on the base substrate is larger than the outer contour of the orthographic projection area of the active layer on the base substrate ; A first via hole and/or a second via hole are formed on the shielding layer. The position of the first via hole corresponds to the position where the source electrode contacts the active layer. The position corresponds to the position where the drain electrode is in contact with the active layer. 14. The manufacturing method according to claim 13, wherein after forming the first via hole and/or the second via hole on the shielding layer, the method specifically comprises: making an insulating layer on the shielding layer; An active layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, a source electrode and a drain electrode are sequentially fabricated on the insulating layer through a patterning process. 15. The manufacturing method according to claim 14, further comprising making common electrode lines, wherein the common electrode lines and the shielding layer are made by the same patterning process; Or, the common electrode line and the gate electrode are formed by the same patterning process.