CN114883346A - Array substrate, manufacturing method thereof and display panel - Google Patents

Abstract

The invention provides an array substrate, a manufacturing method thereof, and a display panel; the array substrate includes a pixel driving circuit located in a display area and a peripheral driving circuit located in a peripheral circuit area on the peripheral side of the display area, and the peripheral driving circuit includes a first thin film The transistor and the pixel driving circuit include a second thin film transistor, and the mobility of the first oxide semiconductor pattern of the first thin film transistor and the second oxide semiconductor pattern of the second thin film transistor are different. Based on the difference in the characteristic requirements of the thin film transistor between the display area and the peripheral circuit area, the embodiments of the present invention adopt oxide semiconductor materials with different mobilities for the semiconductor patterns of the thin film transistors in the peripheral circuit area and the display area, so as to satisfy the requirements of the display panel while taking into account the high performance. Mobility and stability requirements.

Description

Array substrate and manufacturing method thereof, and display panel

technical field

The present invention relates to the field of display technology, and in particular, to an array substrate, a manufacturing method thereof, and a display panel.

Background technique

At present, oxide semiconductor materials are widely used in the field of semiconductor display technology. Compared with amorphous silicon (a-Si), oxide semiconductor has the characteristics of high mobility and low leakage current, and compared with low temperature polysilicon (LowTemperature Poly-Silicon, LTPS), oxide semiconductors can achieve large area uniformity and have lower production costs, therefore, oxide semiconductors are widely used as the semiconductor layer of thin film transistors (Thin Film Transistor, TFT). In the realization of large and medium-sized display panels.

In order to further improve the quality of the display panel, reduce the panel border, and realize the narrow border display, a conventional method is to increase the driving current capability of the peripheral driving circuit to reduce the size of the driving circuit, and use oxide semiconductor materials with higher mobility. (For example: Indium Gallium Tin Oxide (IGTO) material, with a mobility of about 20-30 cm ² /V·s) can achieve higher mobility, thereby reducing the size of the TFT and reducing the size of the driving circuit However, it follows that the high mobility oxide material has a mobility of 10cm ² / V s), the device stability will be reduced, resulting in TFT failure.

Therefore, the existing display panel has the technical problem that high mobility and stability cannot be taken into account at the same time, and needs to be improved.

SUMMARY OF THE INVENTION

The present invention provides an array substrate, a manufacturing method thereof, and a display panel, so as to alleviate the technical problem existing in the existing display panel that high mobility and stability cannot be taken into account at the same time.

For solving the above problems, the technical solutions provided by the present invention are as follows:

An embodiment of the present invention provides an array substrate, which includes a display area and a peripheral circuit area located on the peripheral side of the display area, the array substrate includes a peripheral driving circuit located in the peripheral circuit area and a peripheral circuit area located in the display area. A pixel driving circuit, the peripheral driving circuit includes a first thin film transistor, the pixel driving circuit includes a second thin film transistor, a first oxide semiconductor pattern of the first thin film transistor and a second oxide semiconductor pattern of the second thin film transistor The mobilities of the material semiconductor patterns are different.

In the array substrate provided by the embodiment of the present invention, the mobility of the first oxide semiconductor pattern is higher than the mobility of the second oxide semiconductor pattern.

In the array substrate provided by the embodiment of the present invention, the material of the first oxide semiconductor pattern includes indium gallium tin oxide, and the material of the second oxide semiconductor pattern includes indium gallium zinc oxide.

In the array substrate provided in the embodiment of the present invention, the array substrate includes a substrate, a first oxide semiconductor layer located on the substrate, a second gate insulating layer located on the first oxide semiconductor layer, and a second gate insulating layer located on the first oxide semiconductor layer. a second oxide semiconductor layer over the second gate insulating layer, the first oxide semiconductor layer including the first oxide semiconductor pattern, the second oxide semiconductor layer including the second oxide semiconductor pattern.

In the array substrate provided by the embodiment of the present invention, the array substrate further includes a second metal layer located above the second insulating layer, and the second metal layer includes the first source electrode of the first thin film transistor and the A first drain electrode, the first source electrode and the first drain electrode are electrically connected to the first oxide semiconductor pattern through the via hole of the second gate insulating layer.

In the array substrate provided in the embodiment of the present invention, the second metal layer further includes a second source electrode and a second drain electrode of the second thin film transistor, and the second source electrode and the second drain electrode are the same as the second source electrode and the second drain electrode. The second oxide semiconductor pattern is in direct contact.

In the array substrate provided by the embodiment of the present invention, the array substrate further includes a first metal layer on the substrate and a first gate insulating layer on the first metal layer, and the first oxide A semiconductor layer is located on the first gate insulating layer, and the first metal layer includes a gate of the first thin film transistor.

In the array substrate provided by the embodiment of the present invention, the first metal layer further includes the gate electrode of the second thin film transistor.

Further, an embodiment of the present invention also provides a method for fabricating an array substrate, wherein the array substrate includes a peripheral driving circuit located in the peripheral circuit area and a pixel driving circuit located in the display area, the peripheral driving circuit comprising a first thin film transistor, the pixel driving circuit comprising a second thin film transistor, the mobility of the first oxide semiconductor pattern of the first thin film transistor and the second oxide semiconductor pattern of the second thin film transistor are different; the The production method includes:

providing a substrate;

forming a first metal layer on the substrate, patterning the first metal layer to form a gate of the first thin film transistor and a gate of the second thin film transistor;

forming a first gate insulating layer on the first metal layer;

forming a first oxide semiconductor layer on the first gate insulating layer, patterning the first oxide semiconductor layer to form the first oxide semiconductor pattern;

forming a second gate insulating layer over the first oxide semiconductor pattern;

forming a second oxide semiconductor layer over the second gate insulating layer, patterning the second oxide semiconductor layer to form the second oxide semiconductor pattern;

patterning the second gate insulating layer to form vias;

A second metal layer is deposited over the second gate insulating layer and the second oxide semiconductor pattern, and the second metal layer is patterned to form a first source, a first drain of the first thin film transistor electrode and the second source electrode and the second drain electrode of the second thin film transistor.

Further, an embodiment of the present invention further provides a display panel, including the array substrate described in any one of the above embodiments or the array substrate fabricated according to the method described in the above embodiments.

The beneficial effects of the present invention are as follows: the present invention provides an array substrate, a manufacturing method thereof, and a display panel. The array substrate includes a pixel driving circuit located in a display area and a peripheral driver located in a peripheral circuit area on the peripheral side of the display area. circuit, the peripheral drive circuit includes a first thin film transistor, the pixel drive circuit includes a second thin film transistor, a first oxide semiconductor pattern of the first thin film transistor and a second oxide semiconductor of the second thin film transistor The mobility of the patterns is different. Based on the difference in the characteristic requirements of the thin film transistor between the display area and the peripheral circuit area, the embodiment of the present invention adopts oxide semiconductor materials with different mobilities for the semiconductor pattern of the thin film transistor in the peripheral circuit area and the display area, which satisfies the display panel while taking into account the high performance. Mobility and stability requirements.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings that are used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those skilled in the art, other drawings can also be obtained from these drawings without creative effort.

1 to 8 are schematic cross-sectional views of an array substrate according to an embodiment of the present invention;

FIG. 9 is a flowchart of a method for fabricating an array substrate according to an embodiment of the present invention.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present invention.

In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", " The orientation or positional relationship indicated by "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc. is based on the orientation shown in the drawings Or the positional relationship is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes, and should not be construed as indicating or implying relative importance or implying the number of indicated technical features. Thus, features defined as "first", "second" may expressly or implicitly include one or more of said features. In the description of the present invention, "plurality" means two or more, unless otherwise expressly and specifically defined.

In this application, the word "exemplary" is used to mean "serving as an example, illustration, or illustration." Any embodiment described in this application as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the present invention. In the following description, details are set forth for the purpose of explanation. It will be understood by one of ordinary skill in the art that the present invention may be practiced without the use of these specific details. In other instances, well-known structures and procedures have not been described in detail so as not to obscure the description of the present invention with unnecessary detail. Thus, the present invention is not intended to be limited to the embodiments shown but is to be accorded the widest scope consistent with the principles and features disclosed herein.

Aiming at the technical problem that the existing display panel cannot take both high mobility and stability into consideration, the embodiments of the present invention can be alleviated.

In order to alleviate the above problems, the present application provides an array substrate. Specifically, the array substrate provided by the present application includes a pixel driving circuit located in the display area and a peripheral driving circuit located in the peripheral circuit area on the peripheral side of the display area. The peripheral drive circuit includes a first thin film transistor, the pixel drive circuit includes a second thin film transistor, the mobility of the first oxide semiconductor pattern of the first thin film transistor and the second oxide semiconductor pattern of the second thin film transistor different.

In an embodiment, please refer to FIG. 8 , which is a schematic cross-sectional view of an array substrate provided by an embodiment of the present invention. As shown in FIG. 8 , the array substrate provided by the embodiment of the present invention includes a display area 101 and a peripheral circuit area 102 located on the peripheral side of the display area 101 , and the array substrate includes a peripheral driving circuit located in the peripheral circuit area 102 and a pixel driving circuit located in the display area 101, the peripheral driving circuit includes a first thin film transistor, the pixel driving circuit includes a second thin film transistor, the first oxide semiconductor pattern 10 of the first thin film transistor and The mobility of the second oxide semiconductor pattern 11 of the second thin film transistor is different.

That is, this embodiment provides an array substrate, the array substrate includes a pixel driving circuit located in a display area and a peripheral driving circuit located in a peripheral circuit area on the peripheral side of the display area, and the peripheral driving circuit includes a first thin film transistor , the pixel driving circuit includes a second thin film transistor, and the mobility of the first oxide semiconductor pattern of the first thin film transistor and the second oxide semiconductor pattern of the second thin film transistor are different. Based on the difference in the characteristic requirements of the thin film transistor between the display area and the peripheral circuit area, the embodiment of the present invention adopts oxide semiconductor materials with different mobilities for the semiconductor pattern of the thin film transistor in the peripheral circuit area and the display area, which satisfies the display panel while taking into account the high performance. Mobility and stability requirements. At the same time, the use of thin film transistors with an etch barrier structure in the peripheral circuit area can improve the stability reduction problem caused by high mobility semiconductors, and can also reduce the size of the thin film transistors in the peripheral driving circuit. Thus, the design space is saved, the frame of the display panel is reduced, and the comprehensive performance of the display panel is improved.

In one embodiment, the mobility of the first oxide semiconductor pattern 10 is higher than the mobility of the second oxide semiconductor pattern 11 . Specifically, in the array substrate, there are differences in the characteristic requirements of thin film transistors in the peripheral circuit area and the display area, and the peripheral circuit area requires thin film transistors with higher mobility. The semiconductor pattern of the thin film transistor adopts oxide semiconductor materials with different mobilities to realize that the mobility of the first oxide semiconductor pattern of the first thin film transistor located in the peripheral circuit area is higher than that of the second thin film transistor located in the display area. At the same time, the first thin film transistor in the peripheral circuit area adopts an etching barrier structure during preparation, which can not only improve the stability reduction caused by high mobility, but also realize the reduction of the first thin film of the peripheral driving circuit. The size of the transistors, thereby realizing the narrow frame of the display panel.

Preferably, the mobility of the first oxide semiconductor pattern 10 is about 20˜30 cm ² /V·s, and the mobility of the second oxide semiconductor pattern 11 is about 10 cm ² /V·s.

In one embodiment, the material of the first oxide semiconductor pattern 10 includes indium gallium tin oxide, and the material of the second oxide semiconductor pattern 11 includes indium gallium zinc oxide. It should be noted that the indium gallium tin oxide semiconductor material has higher mobility and can better meet the requirements of the high mobility of the first oxide semiconductor pattern; specifically, the mobility of the indium gallium tin oxide material is about 20-30 cm ² /V·s, the mobility of the indium gallium zinc oxide material is about 10 cm ² /V·s.

In one embodiment, as shown in FIG. 8 , the array substrate includes a substrate 12 , a first oxide semiconductor layer over the substrate 12 , and a second gate insulating layer over the first oxide semiconductor layer layer 14 and a second oxide semiconductor layer over the second gate insulating layer 14, the first oxide semiconductor layer including the first oxide semiconductor pattern 10, the second oxide semiconductor layer including the second oxide semiconductor pattern 11 . Specifically, the first oxide semiconductor pattern 10 and the second oxide semiconductor pattern 11 are located in different film layers.

It should be noted that the first thin film transistor is fabricated using an etching barrier structure, while the second thin film transistor is fabricated using a traditional back-channel etching structure. The first thin film transistor can improve the stability reduction problem caused by the high mobility semiconductor material and improve the overall performance of the display panel.

In an embodiment, as shown in FIG. 8 , the array substrate further includes a second metal layer located above the second gate insulating layer 14 , and the second metal layer includes a second metal layer of the first thin film transistor. A first source electrode 15 and a first drain electrode 16, the first source electrode 15 and the first drain electrode 16 are electrically connected to the first oxide through the via hole of the second gate insulating layer 14 The semiconductor pattern 10 . In this embodiment, considering that the first oxide semiconductor pattern 10 has higher mobility than the second oxide semiconductor pattern 11 and is more easily affected by the process, the second gate insulating layer 14 is formed as an etching method A barrier layer to avoid affecting the sensitive first oxide semiconductor pattern 10 when the second metal layer is patterned.

In an embodiment, as shown in FIG. 8 , the second metal layer further includes a second source electrode 17 and a second drain electrode 18 of the second thin film transistor, the second source electrode 17 and the The second drain electrode 18 is in direct contact with the second oxide semiconductor pattern 11 . In this embodiment, since the second oxide semiconductor pattern 11 has a lower mobility relative to the first oxide semiconductor pattern 10 , it is less affected by the process than the first oxide semiconductor pattern 10 . In order to simplify the process, The second source electrode 17 and the second drain electrode 18 are in direct contact with the second oxide semiconductor pattern 11 . By designing an etch barrier layer for the more sensitive first oxide semiconductor pattern 10 and not designing an etch barrier layer for the second oxide semiconductor pattern 11 with relatively low mobility, it breaks through all oxides in the prior art. The design of the etching barrier layer in semiconductor design not only ensures the mobility performance, but also simplifies the process.

In an embodiment, as shown in FIG. 8 , the array substrate further includes a first metal layer on the substrate 12 and a first gate insulating layer 13 on the first metal layer. The first oxide semiconductor layer is located on the first gate insulating layer 13 , and the first metal layer includes the gate 19 of the first thin film transistor.

In an embodiment, as shown in FIG. 8 , the first metal layer further includes the gate electrode 20 of the second thin film transistor; the gate electrodes of two kinds of thin film transistors are designed in the same layer in the present application, which can reduce the complexity of the process .

Embodiments of the present application further provide a method for fabricating an array substrate, wherein the array substrate includes a peripheral driving circuit located in the peripheral circuit area and a pixel driving circuit located in the display area, and the peripheral driving circuit includes a first Thin film transistor, the pixel driving circuit includes a second thin film transistor, the first oxide semiconductor pattern of the first thin film transistor and the second oxide semiconductor pattern of the second thin film transistor have different mobilities; the manufacturing method include:

providing a substrate;

forming a first metal layer on the substrate, patterning the first metal layer to form a gate of the first thin film transistor and a gate of the second thin film transistor;

forming a first gate insulating layer on the first metal layer;

forming a first oxide semiconductor layer on the first gate insulating layer, patterning the first oxide semiconductor layer to form the first oxide semiconductor pattern;

forming a second gate insulating layer over the first oxide semiconductor pattern;

forming a second oxide semiconductor layer over the second gate insulating layer, patterning the second oxide semiconductor layer to form the second oxide semiconductor pattern;

patterning the second gate insulating layer to form vias;

A second metal layer is deposited over the second gate insulating layer and the second oxide semiconductor pattern, and the second metal layer is patterned to form a first source, a first drain of the first thin film transistor electrode and the second source electrode and the second drain electrode of the second thin film transistor.

The manufacturing method of the array substrate provided by the embodiment of the present application will now be described with reference to FIG. 1 to FIG. 8 and FIG. 9 .

As shown in FIG. 1 to FIG. 8 and FIG. 9 , the manufacturing method of the array substrate provided by the present application includes the following steps:

Step S1, cleaning the substrate.

A glass substrate is provided as the substrate, and the glass substrate is cleaned.

Step S2, depositing a first metal layer, and patterning and etching to form a gate pattern.

Specifically, as shown in FIG. 1, a first metal layer is deposited on the cleaned glass substrate 12, and the first metal layer adopts a double-layer structure (not shown in the figure), wherein the first layer may be a transition metal material , such as molybdenum (Mo), titanium (Ti), tungsten (W), chromium (Cr), nickel (Ni), and alloy materials of the above metals, with a thickness of 50-500 angstroms, the second layer is a metal material, which can be copper (Cu), aluminum (Al), thickness 2000-5000 angstroms;

Further, the first metal layer is patterned to form the gate electrode 19 of the first thin film transistor located in the peripheral circuit region 102 and the gate electrode 20 of the second thin film transistor located in the display region 101 .

Step S3, depositing a first gate insulating layer.

Specifically, as shown in FIG. 2 , a first gate insulating layer 13 is deposited over the gate 19 of the first thin film transistor and the gate 20 of the second thin film transistor, and the first gate insulating layer 13 can not only cover all the upper surface of the gate 19 of the first thin film transistor and the gate 20 of the second thin film transistor, and can also cover the gate 19 of the first thin film transistor and the gate 20 of the second thin film transistor The material of the first gate insulating layer 13 may be silicon dioxide (SiO2), with a thickness of 1000-4000 angstroms.

Step S4, depositing a first oxide semiconductor layer, and patterned etching to form a first oxide semiconductor pattern.

Specifically, as shown in FIG. 3 , a first oxide semiconductor layer is deposited on the first gate insulating layer 13 , and the material of the first oxide semiconductor layer may be a high mobility oxide semiconductor material, such as Indium gallium tin oxide, thickness 100-1000 angstroms;

further, patterning the first oxide semiconductor layer to form the first oxide semiconductor pattern 10;

It should be noted that the first oxide semiconductor pattern 10 is located in the peripheral circuit region 102 of the array substrate.

Step S5 , fabricating a second gate insulating layer (etching barrier layer).

Specifically, as shown in FIG. 4 , a second gate insulating layer 14 is deposited over the first oxide semiconductor pattern 10 , and the second gate insulating layer 14 can not only cover the first oxide semiconductor pattern 10 The upper surface of the first oxide semiconductor pattern 10 can also be covered; the material of the second gate insulating layer 14 can be silicon dioxide (SiO 2 ) with a thickness of 1000-4000 angstroms.

It should be noted that the second gate insulating layer 14 may also be referred to as an etch stop layer.

Step S6, depositing a second oxide semiconductor layer, and patterned etching to form a second oxide semiconductor pattern.

Specifically, as shown in FIG. 5 , a second oxide semiconductor layer is deposited on the second gate insulating layer 14 , and the material of the second oxide semiconductor layer may be an oxide semiconductor material, such as indium gallium zinc oxide material, thickness 100-1000 angstroms;

further, patterning the second oxide semiconductor layer to form the second oxide semiconductor pattern 11;

It should be noted that the second oxide semiconductor pattern 11 is located in the display area 101 of the array substrate.

Step S7, patterning the second gate insulating layer to form openings.

Specifically, as shown in FIG. 6 , a yellow light process is used to etch the second gate insulating layer 14 to define contact holes between the first oxide semiconductor pattern 10 and the source and drain of the first thin film transistor.

In step S8, a second metal layer is deposited, and patterned and etched to form source and drain patterns.

Specifically, as shown in FIG. 7 , a second metal layer is deposited on the second oxide semiconductor pattern 11. The second metal layer not only covers the upper surface of the second oxide semiconductor pattern 11, but also can Covering the side surfaces of the second oxide semiconductor pattern 11 and the region of the second gate insulating layer 14 not covered by the second oxide semiconductor pattern and the via holes on the second gate insulating layer 14 region; the second metal layer adopts a double-layer structure (not shown in the figure), wherein the first layer can be a transition metal material, such as molybdenum (Mo), titanium (Ti), tungsten (W), chromium (Cr) , nickel (Ni), and alloy materials of the above metals, or conductive oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), aluminum zinc oxide (AZO), with a thickness of 50-500 angstroms; The second layer is a metal material, which can be copper (Cu) or aluminum (Al), with a thickness of 2000-10000 angstroms, and the same mask is used to define the first source electrode 15 and the first drain electrode of the first thin film transistor. 16 and the second source electrode 17 and the second drain electrode 18 of the second thin film transistor.

Step S9, making a passivation layer (protective layer).

Specifically, as shown in FIG. 8 , a passivation layer 21 is deposited on the second metal layer. The passivation layer 21 is a silicon dioxide film with a thickness of 1000-5000 angstroms and is used to protect the peripheral circuit area 102 The first thin film transistor of the peripheral driving circuit and the second thin film transistor of the pixel driving circuit located in the display area 101 .

So far, the fabrication of the array substrate is completed.

According to the above description, in the manufacturing method of the array substrate provided by the present application, the mobilities of the materials used in the semiconductor patterns of the thin film transistors located in the peripheral circuit area and the display area are different, so as to meet the requirements of the characteristics of the thin film transistors in different areas, and at the same time , the use of thin film transistors with an etch barrier structure in the peripheral circuit area can not only improve the stability reduction problem caused by high mobility semiconductors, but also reduce the size of the thin film transistors in the peripheral driving circuit, thereby realizing a narrow frame of the display panel.

Correspondingly, an embodiment of the present invention further provides a display panel, the display panel includes the array substrate provided by the present invention or the array substrate fabricated according to the method of the present invention. The display panel can be applied to electronic terminals with display functions, such as fixed terminals such as desktop computers and televisions, mobile terminals such as smart phones and tablet computers, and wearable devices such as smart glasses and telephone watches.

According to the above embodiment, it can be known that:

The present invention provides an array substrate, a manufacturing method, and a display panel. The array substrate includes a pixel driving circuit located in a display area and a peripheral driving circuit located in a peripheral circuit area on the peripheral side of the display area. The peripheral driving circuit includes A first thin film transistor, the pixel driving circuit includes a second thin film transistor, and the mobility of the first oxide semiconductor pattern of the first thin film transistor and the second oxide semiconductor pattern of the second thin film transistor are different. Based on the difference in the characteristic requirements of the thin film transistor between the display area and the peripheral circuit area, the embodiment of the present invention adopts oxide semiconductor materials with different mobilities for the semiconductor pattern of the thin film transistor in the peripheral circuit area and the display area, which satisfies the display panel while taking into account the high performance. Mobility and stability requirements. At the same time, the use of thin film transistors with an etch barrier structure in the peripheral circuit area can improve the stability reduction problem caused by high mobility semiconductors, and can also reduce the size of the thin film transistors in the peripheral driving circuit. Thus, the design space is saved, the frame of the display panel is reduced, and the comprehensive performance of the display panel is improved.

In summary, although the present invention has been disclosed above with preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those of ordinary skill in the art can make various Therefore, the protection scope of the present invention is subject to the scope defined by the claims.

Claims (10)

1. An array substrate comprises a display area and a peripheral circuit area located on the periphery side of the display area, and is characterized in that the array substrate comprises a peripheral driving circuit located in the peripheral circuit area and a pixel driving circuit located in the display area, the peripheral driving circuit comprises a first thin film transistor, the pixel driving circuit comprises a second thin film transistor, and mobility of a first oxide semiconductor pattern of the first thin film transistor is different from mobility of a second oxide semiconductor pattern of the second thin film transistor.

2. The array substrate of claim 1, wherein the first oxide semiconductor pattern has a higher mobility than the second oxide semiconductor pattern.

3. The array substrate of claim 2, wherein the material of the first oxide semiconductor pattern comprises indium gallium tin oxide, and the material of the second oxide semiconductor pattern comprises indium gallium zinc oxide.

4. The array substrate of claim 2, wherein the array substrate comprises a substrate, a first oxide semiconductor layer over the substrate, the first oxide semiconductor layer comprising the first oxide semiconductor pattern, a second gate insulating layer over the first oxide semiconductor layer, and a second oxide semiconductor layer over the second gate insulating layer, the second oxide semiconductor layer comprising the second oxide semiconductor pattern.

5. The array substrate of claim 4, further comprising a second metal layer over the second insulating layer, the second metal layer comprising a first source and a first drain of the first thin film transistor, the first source and the first drain being electrically connected to the first oxide semiconductor pattern through a via of the second gate insulating layer.

6. The array substrate of claim 5, wherein the second metal layer further comprises a second source electrode and a second drain electrode of the second thin film transistor, the second source electrode and the second drain electrode being in direct contact with the second oxide semiconductor pattern.

7. The array substrate of claim 4, further comprising a first metal layer on the substrate and a first gate insulating layer on the first metal layer, wherein the first oxide semiconductor layer is on the first gate insulating layer, and wherein the first metal layer comprises a gate of the first thin film transistor.

8. The array substrate of claim 7, wherein the first metal layer further comprises a gate of the second thin film transistor.

9. The manufacturing method of the array substrate is characterized in that the array substrate comprises a peripheral driving circuit and a pixel driving circuit, wherein the peripheral driving circuit is located in a peripheral circuit area, the pixel driving circuit is located in a display area, the peripheral driving circuit comprises a first thin film transistor, the pixel driving circuit comprises a second thin film transistor, and the mobility of a first oxide semiconductor pattern of the first thin film transistor is different from that of a second oxide semiconductor pattern of the second thin film transistor; the manufacturing method comprises the following steps:

providing a substrate;

forming a first metal layer on the substrate, and patterning the first metal layer to form a gate of the first thin film transistor and a gate of the second thin film transistor;

forming a first gate insulating layer on the first metal layer;

forming a first oxide semiconductor layer on the first gate insulating layer, patterning the first oxide semiconductor layer to form the first oxide semiconductor pattern;

forming a second gate insulating layer over the first oxide semiconductor pattern;

forming a second oxide semiconductor layer over the second gate insulating layer, patterning the second oxide semiconductor layer to form the second oxide semiconductor pattern;

patterning the second gate insulating layer to form a via hole;

depositing a second metal layer over the second gate insulating layer and the second oxide semiconductor pattern, and patterning the second metal layer to form a first source electrode and a first drain electrode of the first thin film transistor and a second source electrode and a second drain electrode of the second thin film transistor.

10. A display panel comprising the array substrate according to any one of claims 1 to 8 or the array substrate manufactured by the method according to claim 9.

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