CN110992912A - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN110992912A CN110992912A CN201911374443.6A CN201911374443A CN110992912A CN 110992912 A CN110992912 A CN 110992912A CN 201911374443 A CN201911374443 A CN 201911374443A CN 110992912 A CN110992912 A CN 110992912A
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- 239000000758 substrate Substances 0.000 title claims abstract description 53
- 238000010586 diagram Methods 0.000 description 20
- 230000000694 effects Effects 0.000 description 11
- 239000004973 liquid crystal related substance Substances 0.000 description 7
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3607—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels
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- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention provides an array substrate, a display panel and a display device.A buffer is additionally and electrically connected between a first sub-grid line and a second sub-grid line, and the driving capability of signals output by the first sub-grid line is improved and then the signals are output to the second sub-grid line through the buffer, so that the signals transmitted on the first sub-grid line and the second sub-grid line have higher driving capability; compared with the situation that the gate line is connected with the whole sub-pixel row in the prior art, the first sub-gate line and the second sub-gate line are respectively connected with the sub-pixels, so that the load connected with each sub-gate line is reduced, and the high driving capability of the gate line for transmitting signals is further ensured. The display device provided by the invention is only required to additionally connect a buffer between the first sub-gate line and the second sub-gate line, the buffer has a simple structure, the influence of the buffer on the aperture opening ratio and the frame width of the display device is avoided, and the high aperture opening ratio of the display device is ensured and the display device conforms to the narrow frame trend.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
The display screen is divided into a liquid crystal display screen and an organic light emitting display screen, and with the development of the display screen technology, the application field of the display screen is continuously expanded. Like vehicle-mounted display screen, wherein, vehicle-mounted display screen can design in the panel board, well accuse and copilot position department, along with the technological promotion of display screen, more display device has gradually been integrated to the automotive products, has strengthened modern sense and science and technology and has felt, seems more high-end, also more likes jumbo size, super wide screen display that accounts for in the on-vehicle device field moreover. However, as the width of the display screen is made larger and larger, the requirement for the driving capability of the signal transmitted on the gate line is higher and higher, and the signal with lower driving capability transmitted on the gate line is obviously no longer suitable for the display device with ultra-wide screen ratio.
Disclosure of Invention
In view of the above, the present invention provides an array substrate, a display panel and a display device, which effectively solve the technical problems in the prior art and ensure high driving capability of gate line transmission signals.
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
an array substrate, comprising:
a sub-pixel array including first to Nth sub-pixel rows, N being an integer not less than 2;
the first gate line to the Nth gate line, the ith gate line is connected with the ith sub-pixel row and is used for transmitting scanning signals to the sub-pixels in the corresponding sub-pixel row, and i is a positive integer not greater than N;
wherein at least one of the first to nth gate lines includes a first sub-gate line and a second sub-gate line, and a buffer is connected between an output terminal of the first sub-gate line and an input terminal of the second sub-gate line, the first sub-gate line connects a part of sub-pixels in a corresponding sub-pixel row, and another part of sub-pixels in the corresponding sub-pixel row is connected to the second sub-gate line.
Optionally, in a sub-pixel row connected to a gate line including a first sub-gate line and a second sub-gate line, at least one sub-pixel is divided into two sub-pixel groups at intervals, one sub-pixel group is electrically connected to the first sub-gate line, and the other sub-pixel group is electrically connected to the second sub-gate line.
Optionally, in a sub-pixel row connected to a gate line including a first sub-gate line and a second sub-gate line, all sub-pixels are sequentially divided into two sub-pixel groups according to an arrangement direction of the sub-pixels, one sub-pixel group is electrically connected to the first sub-gate line, and the other sub-pixel group is electrically connected to the second sub-gate line.
Optionally, all of the first to nth gate lines include a first sub-gate line and a second sub-gate line.
Optionally, the array substrate includes a display area and a frame area located outside the display area, and the buffer is located in the frame area.
Optionally, the array substrate includes first to nth scanning circuits, and the first to nth scanning circuits output the scanning signals step by step, wherein the ith scanning circuit is electrically connected to the ith gate line;
and in a scanning circuit and a sub-pixel row which are connected with a gate line comprising a first sub-gate line and a second sub-gate line, the scanning circuit and the buffer are respectively positioned at two sides of the pixel row along the sub-pixel arrangement direction in the sub-pixel row.
Optionally, the array substrate includes a first-stage scanning circuit to an nth-stage scanning circuit, wherein the ith-stage scanning circuit is electrically connected to the ith gate line;
along the sub-pixel arrangement direction in the sub-pixel row, the odd-level scanning circuit and the even-level scanning circuit are respectively positioned at two sides of the sub-pixel array.
Optionally, in the arrangement direction of all the sub-pixel rows, the first sub-gate line and the second sub-gate line connected to the sub-pixel row are respectively located at two sides of the sub-pixel row.
Optionally, a predetermined number of sub-pixels electrically connected to an output end side of the first sub-gate line are also electrically connected to the second sub-gate line.
Optionally, a predetermined number of sub-pixels electrically connected to an output end side of the second sub-gate line are also electrically connected to the first sub-gate line.
Correspondingly, the invention also provides a display panel which comprises the array substrate.
Correspondingly, the invention further provides a display device which comprises the display panel.
Compared with the prior art, the technical scheme provided by the invention at least has the following advantages:
the invention provides an array substrate, a display panel and a display device, comprising: a sub-pixel array including first to Nth sub-pixel rows, N being an integer not less than 2; the first gate line to the Nth gate line, the ith gate line is connected with the ith sub-pixel row and is used for transmitting scanning signals to the sub-pixels in the corresponding sub-pixel row, and i is a positive integer not greater than N; wherein at least one of the first to nth gate lines includes a first sub-gate line and a second sub-gate line, and a buffer is connected between an output terminal of the first sub-gate line and an input terminal of the second sub-gate line, the first sub-gate line connects a part of sub-pixels in a corresponding sub-pixel row, and another part of sub-pixels in the corresponding sub-pixel row is connected to the second sub-gate line.
According to the technical scheme provided by the invention, the buffer is additionally and electrically connected between the first sub-gate line and the second sub-gate line, so that the driving capability of the signal output by the first sub-gate line is improved by the buffer and then the signal is output to the second sub-gate line, and the signals transmitted on the first sub-gate line and the second sub-gate line are ensured to have higher driving capability; compared with the situation that the gate line is connected with the whole sub-pixel row in the prior art, the first sub-gate line and the second sub-gate line are respectively connected with the sub-pixels, so that the load connected with each sub-gate line is reduced, and the high driving capability of the gate line for transmitting signals is further ensured.
In addition, the display device provided by the invention only needs to additionally connect a buffer between the first sub-gate line and the second sub-gate line, the buffer has a simple structure, the influence of the buffer on the aperture opening ratio and the frame width of the display device is avoided, and the high aperture opening ratio of the display device is ensured and the display device conforms to the narrow frame trend.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a connection structure between a gate line and a sub-pixel row according to an embodiment of the present invention;
FIG. 3 is a schematic view of another connection structure of a gate line and a sub-pixel row according to an embodiment of the present invention;
FIG. 4 is a schematic view of another connection structure of a gate line and a sub-pixel row according to an embodiment of the present invention;
FIG. 5 is a schematic view of another connection structure of a gate line and a sub-pixel row according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 7 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
fig. 8 is a schematic structural diagram of another array substrate according to an embodiment of the present invention;
FIG. 9a is a schematic view of another connection structure of a gate line and a sub-pixel row according to an embodiment of the present invention;
FIG. 9b is a schematic view of another connection structure of a gate line and a sub-pixel row according to an embodiment of the present invention;
FIG. 10a is a schematic view of another connection structure of a gate line and a sub-pixel row according to an embodiment of the present invention;
FIG. 10b is a schematic view of another gate line and sub-pixel row connection structure according to an embodiment of the present invention;
fig. 11 is a schematic structural diagram of a display panel according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram of a display device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
As described in the background art, display panels are classified into liquid crystal display panels and organic light emitting display panels, and their application fields are continuously expanding with the development of display panel technologies. Like vehicle-mounted display screen, wherein, vehicle-mounted display screen can design in the panel board, well accuse and copilot position department, along with the technological promotion of display screen, more display device has gradually been integrated to the automotive products, has strengthened modern sense and science and technology and has felt, seems more high-end, also more likes jumbo size, super wide screen display that accounts for in the on-vehicle device field moreover. However, as the width of the display screen is made larger and larger, the requirement for the driving capability of the signal transmitted on the gate line is higher and higher, and the signal with lower driving capability transmitted on the gate line is obviously no longer suitable for the display device with ultra-wide screen ratio.
Along with the research of the display with the ultra-wide screen ratio, the extension length of the gate line is longer and longer, and the driving capability of the scanning signal accessed from the input end of the gate line is gradually reduced at the tail end side along with the extension of the gate line, so that the driving effect of the scanning signal on the sub-pixels connected with the tail end side of the gate line is reduced, and the display effect of the display device is poor.
In the prior art, in order to improve the driving capability of signals transmitted by the gate lines, a mode of respectively connecting a scanning circuit to two ends of the gate lines is generally adopted, and a mode of respectively outputting signals to two ends of the gate lines by two scanning circuits is adopted to improve the driving capability of the signals on the gate lines.
Based on the above, the invention provides an array substrate, a display panel and a display device, which effectively solve the technical problems in the prior art and ensure high driving capability of gate line transmission signals.
In order to achieve the above object, the technical solutions provided by the present invention are described in detail below, specifically with reference to fig. 1 to 12.
Referring to fig. 1, a schematic structural diagram of an array substrate according to an embodiment of the present invention is shown, where the array substrate includes:
a subpixel array including first to nth subpixel rows P1 to Pn, N being an integer not less than 2;
and first to nth gate lines G1 to Gn, Gi th gate line being connected to the ith sub-pixel row Pi for transmitting a scan signal to the sub-pixels in the corresponding sub-pixel row, i being a positive integer not greater than N;
at least one of the first gate line G1 to the nth gate line Gn includes a first sub-gate line 101 and a second sub-gate line 102, a buffer 200 is connected between an output terminal of the first sub-gate line 101 and an input terminal of the second sub-gate line 102, the first sub-gate line 101 connects a part of sub-pixels in a corresponding sub-pixel row, and another part of sub-pixels in the corresponding sub-pixel row is connected to the second sub-gate line 102.
The array substrate provided by the embodiment of the invention comprises a sub-pixel array, wherein the sub-pixel array comprises a plurality of sub-pixel rows and a plurality of sub-pixel columns, the number of the sub-pixel rows and the sub-pixel columns is not particularly limited, and the sub-pixel array needs to be specifically designed according to factors such as the type and the size of a display device in practical application.
And the array substrate comprises a plurality of gate lines and a plurality of data lines, and the gate lines and the data lines are crossed to define the position of each sub-pixel in the sub-pixel array. Generally, each sub-pixel row is electrically connected to a gate line, and each sub-pixel column is electrically connected to a data line, wherein the scanning signal transmitted through the gate line scans each sub-pixel in the sub-pixel row, and the data line transmits the data signal to the currently scanned sub-pixel.
According to the technical scheme provided by the invention, the buffer has the function of improving the driving capability of signals input into the buffer and outputting the signals, and is electrically connected between the first sub-gate line and the second sub-gate line; compared with the situation that the gate line is connected with the whole sub-pixel row in the prior art, the first sub-gate line and the second sub-gate line are respectively connected with the sub-pixels, so that the load connected with each sub-gate line is reduced, and the high driving capability of the gate line for transmitting signals is further ensured.
In addition, the display device provided by the invention only needs to additionally connect a buffer between the first sub-gate line and the second sub-gate line, the buffer has a simple structure, the influence of the buffer on the aperture opening ratio and the frame width of the display device is avoided, and the high aperture opening ratio of the display device is ensured and the display device conforms to the narrow frame trend.
In an embodiment of the present invention, in the first to nth gate lines provided by the present invention, all the gate lines may have the first sub-gate line and the second sub-gate line, and the buffer is electrically connected between the first sub-gate line and the second sub-gate line, so that the driving capability of all the gate lines of the entire display device for transmitting signals can be improved, and the display effect can be improved; or, the first gate line to the nth gate line are sequentially divided into two groups of gate line groups, all gate lines in the first group of gate line groups are provided with a first sub-gate line and a second sub-gate line, the buffer is electrically connected between the first sub-gate line and the second sub-gate line, and all gate lines in the second group of gate line groups are a whole signal line as in the prior art; or, the first gate line to the nth gate line are alternately divided into two groups every a certain number of gate lines, and all the gate lines in one group of gate lines have the first sub-gate line and the second sub-gate line, and the buffer is electrically connected between the first sub-gate line and the second sub-gate line, and all the gate lines in the other group of gate lines are the same as those in the prior art as one whole signal line, which does not specifically limit the present invention.
In an embodiment of the present invention, in a gate line having a first sub-gate line and a second sub-gate line, a sub-pixel row connected to the gate line may be divided into two groups according to an indefinite number of sub-pixels, and the two groups are electrically connected to the first sub-gate line and the second sub-gate line, respectively. Referring to fig. 2, a schematic diagram of a connection between a gate line and a sub-pixel row according to an embodiment of the present invention is shown, where at least one sub-pixel in the sub-pixel row connected to the gate line including a first sub-gate line 101 and a second sub-gate line 102 is divided into two sub-pixel groups at intervals, one sub-pixel group is electrically connected to the first sub-gate line 101, and the other sub-pixel group is electrically connected to the second sub-gate line 102.
As can be understood from fig. 2, in the gate line having the first and second sub-gate lines provided in the present invention, the rows of sub-pixels electrically connected to the gate line may be divided into two groups at intervals of the same number of sub-pixels; as shown in fig. 2, each sub-pixel row includes sub-pixels Pi1, Pi2, Pi3, Pi4, Pi5, Pi6, Pi7, Pi8, Pi9 and Pi10, which are divided into two groups every other sub-pixel, the first group of sub-pixel groups includes sub-pixels Pi1, Pi3, Pi5, Pi7 and Pi9, the first group of sub-pixel groups is electrically connected to the first sub-gate line 101, the second group of sub-pixel groups includes sub-pixels Pi2, Pi4, Pi6, Pi8 and Pi10, and the second group of sub-pixel groups is electrically connected to the second sub-gate line 102.
Fig. 2 shows two groups of sub-pixels with the same number of sub-pixels, and the present invention can also divide two groups of sub-pixels with different numbers of sub-pixels, specifically, in combination with fig. 3, an exemplary connection scheme of a gate line and a sub-pixel row is provided in the present invention, wherein each sub-pixel row includes sub-pixels Pi1, Pi2, Pi3, Pi4, Pi5, Pi6, Pi7, Pi8, Pi9 and Pi10, the first group of sub-pixels includes sub-pixels Pi1, Pi4, Pi5 and Pi6, and the first group of sub-pixels is electrically connected to the first sub-gate line 101, and the second group of sub-pixels includes sub-pixel Pi2, Pi3, Pi7, Pi8, Pi 27 and the second group of sub-pixels Pi 36102, and the second group of sub-pixels Pi 36102 is electrically connected to the gate line.
It should be noted that, when all the sub-pixels in the sub-pixel row are divided into two sub-pixel groups according to at least one interval, the number of intervals may be the same number, may also be different numbers, or may be different numbers for some of the same number, and the present invention is not limited specifically.
In an embodiment of the present invention, in the gate line having the first sub-gate line and the second sub-gate line, the sub-pixel rows connected to the gate line may be further divided into two sub-pixel groups in sequence according to the arrangement direction. Referring to fig. 4, a schematic diagram of a connection structure of a gate line and a sub-pixel row according to another embodiment of the present invention is provided, wherein in the sub-pixel row connected to the gate line including a first sub-gate line 101 and a second sub-gate line 102, all sub-pixels are sequentially divided into two sub-pixel groups according to an arrangement direction X of the sub-pixels, one sub-pixel group is electrically connected to the first sub-gate line 101, and the other sub-pixel group is electrically connected to the second sub-gate line 102.
As can be understood from fig. 4, in the gate line having the first sub-gate line and the second sub-gate line provided in the present invention, the sub-pixel rows electrically connected to the gate line may be sequentially divided into two groups according to the sub-pixel arrangement direction, and for example, when the sub-pixel rows include even number of sub-pixels, the number of sub-pixels in the two sub-pixel groups may be the same. As shown in fig. 4, each sub-pixel row includes sub-pixels Pi1, Pi2, Pi3, Pi4, Pi5, Pi6, Pi7, Pi8, Pi9 and Pi10, which are sequentially divided into two sub-pixel groups according to the arrangement direction X of the sub-pixels, wherein the first sub-pixel group includes sub-pixels Pi1, Pi2, Pi3, Pi4 and Pi5, the first sub-pixel group is electrically connected to the first sub-gate line 101, the second sub-pixel group includes sub-pixels Pi6, Pi7, Pi8, Pi9 and Pi10, and the second sub-pixel group is electrically connected to the second sub-gate line 102.
Wherein fig. 4 shows that the numbers of sub-pixels in two sub-pixel groups are the same, the present invention can also be designed such that the numbers of sub-pixels in two sub-pixel groups are different, and specifically, in combination with fig. 5, the present invention provides a schematic connection diagram of another gate line and sub-pixel row according to an embodiment of the present invention, wherein, taking as an example that each sub-pixel row comprises a sub-pixel Pi1, a sub-pixel Pi2, a sub-pixel Pi3, a sub-pixel Pi4, a sub-pixel Pi5, a sub-pixel Pi6, a sub-pixel Pi7, a sub-pixel Pi8, a sub-pixel Pi9 and a sub-pixel Pi10, the first group of sub-pixel groups comprises a sub-pixel Pi1, a sub-pixel Pi2, a sub-pixel Pi3 and a sub-pixel Pi4, and the first group of sub-pixel groups is electrically connected with the first sub-gate line 101, and the second group of sub-pixel groups includes sub-pixel Pi5, sub-pixel Pi6, sub-pixel Pi7, sub-pixel Pi8, sub-pixel Pi9 and sub-pixel Pi10, and is electrically connected to the second sub-gate line 102.
It should be noted that, when all the sub-pixels in the sub-pixel row are sequentially divided into two sub-pixel groups according to the sub-pixel arrangement direction, the number of the sub-pixels in the two sub-pixel groups may be the same or different, and the specific design is required according to the actual application.
In an embodiment of the invention, the buffer provided by the invention can be disposed in a frame region of the array substrate, thereby preventing the buffer from being disposed in the display region to affect the aperture ratio. Referring to fig. 6, a schematic structural diagram of another array substrate according to an embodiment of the present invention is shown, where the array substrate includes a display area AA and a frame area SA located outside the display area AA, and the buffer 200 is located in the frame area SA.
In an embodiment of the present invention, the array substrate further includes a gate scanning circuit, the gate scanning circuit includes cascaded multi-stage scanning circuits, each stage of the scanning circuit is electrically connected to a corresponding gate line, and is configured to provide scanning signals for the gate lines, wherein the multi-stage scanning circuits are disposed in a frame region of the array substrate; the buffer and the scanning circuit provided by the invention can be respectively positioned at two sides of the sub-pixel array in the arrangement direction of the sub-pixel rows. Referring to fig. 7, a schematic structural diagram of another array substrate according to an embodiment of the present invention is shown, where the array substrate includes first to nth scan circuits SR1 to SRn, and the first to nth scan circuits SR1 to SRn output the scan signals step by step, where the ith scan circuit SRi is electrically connected to the ith gate line Gi;
in the scan circuit and the sub-pixel row connected to the gate line including the first and second sub-gate lines 101 and 102, the scan circuit and the buffer 200 are respectively located at both sides of the pixel row along the sub-pixel arrangement direction in the sub-pixel row.
The multi-stage scanning circuit and the buffer provided by the embodiment of the invention can be arranged in the frame area SA positioned outside the display area AA.
It can be understood that the scanning circuit and the buffer are respectively arranged at two sides of the sub-pixel array, so that the problem that the width of the frame area is influenced when the scanning circuit and the buffer are arranged at the same side is avoided, and the narrow width of the frame area provided by the invention is ensured.
In an embodiment of the invention, since the area occupied by the scanning circuits is large, the array substrate provided by the invention can also divide the multi-stage scanning circuits into two groups which are respectively arranged at two sides of the sub-pixel array, thereby avoiding the problem that the width of one side of the frame region is large due to the fact that all the scanning circuits are arranged at the same side. Referring to fig. 8, a schematic structural diagram of another array substrate according to an embodiment of the present invention is shown, where the array substrate includes first to nth scan circuits SR1 to SRn, and the first to nth scan circuits SR1 to SRn output the scan signals step by step, where the ith scan circuit SRi is electrically connected to the ith gate line Gi;
along the sub-pixel arrangement direction X in the sub-pixel row, the odd-level scanning circuit and the even-level scanning circuit are respectively positioned at two sides of the sub-pixel array.
The multi-stage scan circuit and the buffer 200 provided by the embodiment of the invention can be disposed in the frame area SA outside the display area AA. Further, in the scan circuit and the sub-pixel row connected to the gate line including the first sub-gate line 101 and the second sub-gate line 102 provided in the embodiment of the present invention, the scan circuit and the buffer 200 are respectively located at both sides of the pixel row along the sub-pixel arrangement direction X in the sub-pixel row.
It can be understood that, in the technical solution provided by the embodiment of the present invention, the odd scanning circuit and the even scanning circuit are respectively disposed at two sides of the sub-pixel array, and the scanning circuit and the buffer are respectively disposed at two sides of the sub-pixel array, so as to ensure the width of the frame region to be narrow to the greatest extent.
In an embodiment of the present invention, in the technical solution provided by the present invention, the first sub-gate line and the second sub-gate line in the same gate line may be respectively disposed on two sides of the sub-pixel row electrically connected thereto in the sub-pixel arrangement direction. Namely, the first sub-gate line and the second sub-gate line connected to the sub-pixel row are respectively located at both sides of the sub-pixel row along the arrangement direction of all the sub-pixel rows.
It should be noted that, the first sub-gate line and the second sub-gate line in the same gate line provided by the present invention may also be located on the same side of the sub-pixel row, and the present invention is not limited in particular. The first sub-gate line and the second sub-gate line are arranged in a shading area between adjacent sub-pixel rows, and therefore the influence of the first sub-gate line and the second sub-gate line on display is avoided.
In an embodiment of the present invention, since the output end side of the first sub-gate line is lower than the input end side in driving capability of the transmitted signal, in order to improve the driving effect of the electrically connected sub-pixels on the output end side of the first sub-gate line, a part of the sub-pixels electrically connected to the output end side of the first sub-gate line may be further electrically connected to the second sub-gate line, that is, the predetermined number of sub-pixels electrically connected to the output end side of the first sub-gate line provided by the present invention are further electrically connected to the second sub-gate line. It should be noted that the output end side of the first sub-gate line according to the present invention is the side of the first sub-gate line connected to one end of the buffer.
Referring specifically to fig. 9a, a schematic diagram of connection between a gate line and a sub-pixel row according to another embodiment of the present invention is provided, wherein each sub-pixel row includes a sub-pixel Pi1, a sub-pixel Pi2, a sub-pixel Pi3, a sub-pixel Pi4, a sub-pixel Pi5, a sub-pixel Pi6, a sub-pixel Pi7, a sub-pixel Pi8, a sub-pixel Pi9 and a sub-pixel Pi10, which are sequentially divided into two sub-pixel groups according to an arrangement direction X of the sub-pixels, wherein the first sub-pixel group includes the sub-pixel Pi1, the sub-pixel Pi2, the sub-pixel Pi3, the sub-pixel Pi4 and the sub-pixel Pi5, the first sub-pixel group is electrically connected to the first sub-gate line 101, the second sub-pixel group includes the sub-pixel Pi6, the sub-pixel Pi7, the sub-pixel Pi8, the sub-pixel Pi9 and the sub-pixel Pi10, and the second sub-pixel group is electrically connected to the gate line 102;
here, the driving capability of the signal at the output terminal side of the first sub-gate line is lowered, so that the sub-pixel Pi4 and the sub-pixel Pi5 electrically connected to the output terminal side of the first sub-gate line can be set to be electrically connected to the second sub-gate line 102, and further the sub-pixel Pi4 and the sub-pixel Pi5 are supplied with the signal through the first sub-gate line 101 and the second sub-gate line 102 in common, ensuring a high driving effect on the sub-pixel Pi4 and the sub-pixel Pi 5.
Alternatively, referring to fig. 9b, a schematic diagram of the connection between the gate line and the sub-pixel row according to another embodiment of the present invention is provided, wherein each sub-pixel row includes a sub-pixel Pi1, a sub-pixel Pi2, a sub-pixel Pi3, a sub-pixel Pi4, a sub-pixel Pi5, a sub-pixel Pi6, a sub-pixel Pi7, a sub-pixel Pi8, a sub-pixel Pi9 and a sub-pixel Pi10, each sub-pixel is divided into two groups every other sub-pixel, the first sub-pixel group includes a sub-pixel Pi1, a sub-pixel Pi3, a sub-pixel Pi5, a sub-pixel Pi7 and a sub-pixel Pi9, the first sub-pixel group is electrically connected to the first sub-gate line 101, the second sub-pixel group includes a sub-pixel Pi2, a sub-pixel Pi4, a sub-pixel Pi6, a sub-pixel Pi8 and a sub-pixel Pi10, and the second sub-pixel group includes a sub-pixel Pi2 and a sub-gate line 102;
here, the driving capability of the signal at the output terminal side of the first sub-gate line is lowered, so that the sub-pixel Pi7 and the sub-pixel Pi9 electrically connected to the output terminal side of the first sub-gate line can be set to be electrically connected to the second sub-gate line 102, and further the sub-pixel Pi7 and the sub-pixel Pi9 are supplied with the signal through the first sub-gate line 101 and the second sub-gate line 102 in common, ensuring a high driving effect on the sub-pixel Pi7 and the sub-pixel Pi 9.
Also, since the output end side of the second sub gate line is reduced in driving capability of a transmitted signal compared to the input end side thereof, in order to improve a driving effect of the electrically connected sub pixels at the output end side of the second sub gate line, a part of the sub pixels electrically connected at the output end side of the second sub gate line may be further electrically connected to the first sub gate line, that is, a predetermined number of the sub pixels electrically connected at the output end side of the second sub gate line may be further electrically connected to the first sub gate line. It should be noted that the output end side of the second sub-gate line in the present invention is the side of the second sub-gate line far away from the buffer.
Referring specifically to fig. 10a, a schematic diagram of connection between a gate line and a sub-pixel row according to another embodiment of the present invention is provided, wherein each sub-pixel row includes a sub-pixel Pi1, a sub-pixel Pi2, a sub-pixel Pi3, a sub-pixel Pi4, a sub-pixel Pi5, a sub-pixel Pi6, a sub-pixel Pi7, a sub-pixel Pi8, a sub-pixel Pi9 and a sub-pixel Pi10, which are sequentially divided into two sub-pixel groups according to an arrangement direction X of the sub-pixels, wherein the first sub-pixel group includes the sub-pixel Pi1, the sub-pixel Pi2, the sub-pixel Pi3, the sub-pixel Pi4 and the sub-pixel Pi5, the first sub-pixel group is electrically connected to the first sub-gate line 101, the second sub-pixel group includes the sub-pixel Pi6, the sub-pixel Pi7, the sub-pixel Pi8, the sub-pixel Pi9 and the sub-pixel Pi10, and the second sub-pixel group is electrically connected to the gate line 102;
here, the driving capability of the signal at the output terminal side of the second sub-gate line is lowered, so that the sub-pixel Pi6 and the sub-pixel Pi7 electrically connected to the output terminal side of the second sub-gate line can be set to be electrically connected to the first sub-gate line 101, and further the sub-pixel Pi6 and the sub-pixel Pi7 are supplied with the signal through the first sub-gate line 101 and the second sub-gate line 102 in common, thereby ensuring a high driving effect on the sub-pixel Pi6 and the sub-pixel Pi 7. Meanwhile, the sub-pixel Pi4 and the sub-pixel Pi5 electrically connected to the output terminal side of the first sub-gate line may be disposed to be also electrically connected to the second sub-gate line 102, ensuring that the driving effects on the sub-pixel Pi4, the sub-pixel Pi5, the sub-pixel Pi6, and the sub-pixel Pi7 are high.
Alternatively, referring to fig. 10b, a schematic diagram of the connection between the gate line and the sub-pixel row according to another embodiment of the present invention is provided, wherein each sub-pixel row includes a sub-pixel Pi1, a sub-pixel Pi2, a sub-pixel Pi3, a sub-pixel Pi4, a sub-pixel Pi5, a sub-pixel Pi6, a sub-pixel Pi7, a sub-pixel Pi8, a sub-pixel Pi9 and a sub-pixel Pi10, each sub-pixel is divided into two groups every other sub-pixel, the first sub-pixel group includes a sub-pixel Pi1, a sub-pixel Pi3, a sub-pixel Pi5, a sub-pixel Pi7 and a sub-pixel Pi9, the first sub-pixel group is electrically connected to the first sub-gate line 101, the second sub-pixel group includes a sub-pixel Pi2, a sub-pixel Pi4, a sub-pixel Pi6, a sub-pixel Pi8 and a sub-pixel Pi10, and the second sub-pixel group includes a sub-pixel Pi 36102;
here, the driving capability of the signal at the output terminal side of the second sub-gate line is lowered, so that the sub-pixel Pi2 and the sub-pixel Pi4 electrically connected to the output terminal side of the second sub-gate line can be set to be electrically connected to the first sub-gate line 101, and further the sub-pixel Pi2 and the sub-pixel Pi4 are supplied with the signal through the second sub-gate line 102 and the first sub-gate line 101 in common, thereby ensuring a high driving effect on the sub-pixel Pi2 and the sub-pixel Pi 4. Meanwhile, the sub-pixel Pi7 and the sub-pixel Pi9 electrically connected to the output terminal side of the first sub-gate line may be disposed to be also electrically connected to the second sub-gate line 102, ensuring that the driving effects on the sub-pixel Pi2, the sub-pixel Pi4, the sub-pixel Pi7, and the sub-pixel Pi9 are high.
In an embodiment of the present invention, the buffer provided in the present invention may include an even number of inverters connected in series, wherein the output terminal of the first sub-gate line is electrically connected to the input terminal of the buffer, and the output terminal of the buffer is electrically connected to the input terminal of the second sub-gate line.
Furthermore, the output end of the second sub-gate line provided by the embodiment of the invention can be electrically connected with an electrostatic discharge module, so as to protect the gate line and the electrical connection structure thereof from being damaged by static electricity.
Correspondingly, the invention further provides a display panel, and the display panel comprises the array substrate provided by any one of the embodiments.
Optionally, the display panel provided in the embodiment of the present invention may be a liquid crystal display panel, an organic light emitting display panel, and the like, and the present invention is not particularly limited.
Referring to fig. 11, a schematic structural diagram of a display panel according to an embodiment of the present invention is shown, where the display panel is a liquid crystal display panel, and the liquid crystal display panel includes the array substrate 1000 according to any one of the embodiments;
a color film substrate 2000 disposed opposite to the array substrate 1000;
and a liquid crystal layer 3000 located between the array substrate 1000 and the color filter substrate 2000.
It can be understood that, the display panel provided by the embodiment of the present invention adopts the array substrate provided by any one of the above embodiments, and since the gate line of the array substrate is designed to be the first sub-gate line and the second sub-gate line, and a buffer is added between the first sub-gate line and the second sub-gate line to electrically connect the first sub-gate line and the second sub-gate line, the buffer improves the driving capability of the signal output by the first sub-gate line and outputs the signal to the second sub-gate line, thereby ensuring that the signals transmitted on the first sub-gate line and the second sub-gate line have higher driving capability; compared with the situation that the gate line is connected with the whole sub-pixel row in the prior art, the first sub-gate line and the second sub-gate line are respectively connected with the sub-pixels, so that the load connected with each sub-gate line is reduced, and the high driving capability of the gate line for transmitting signals is further ensured.
In addition, the display panel provided by the invention only needs to additionally connect a buffer between the first sub-gate line and the second sub-gate line, the buffer has a simple structure, the influence of the buffer on the aperture opening ratio and the frame width of the display panel is avoided, and the high aperture opening ratio of the display panel is ensured and the display panel meets the design of narrow frame trend.
Correspondingly, the invention further provides a display device which comprises the display panel provided by any one of the embodiments.
Optionally, the display device provided in the embodiment of the present invention may be a mobile terminal device, and may also be a vehicle-mounted display device, which is not limited in particular to the present invention.
Referring to fig. 12, a schematic structural diagram of a display device according to an embodiment of the present invention is shown, where the display device 10 may be an on-vehicle display device, and the display device 10 includes a display panel according to any of the embodiments described above;
and when the display device is a liquid crystal display device, the display device also comprises a backlight source module for providing backlight for the display panel.
The invention provides an array substrate and a display device, comprising: a sub-pixel array including first to Nth sub-pixel rows, N being an integer not less than 2; the first gate line to the Nth gate line, the ith gate line is connected with the ith sub-pixel row and is used for transmitting scanning signals to the sub-pixels in the corresponding sub-pixel row, and i is a positive integer not greater than N; wherein at least one of the first to nth gate lines includes a first sub-gate line and a second sub-gate line, and a buffer is connected between an output terminal of the first sub-gate line and an input terminal of the second sub-gate line, the first sub-gate line connects a part of sub-pixels in a corresponding sub-pixel row, and another part of sub-pixels in the corresponding sub-pixel row is connected to the second sub-gate line.
According to the technical scheme provided by the invention, the buffer is additionally and electrically connected between the first sub-gate line and the second sub-gate line, so that the driving capability of the signal output by the first sub-gate line is improved by the buffer and then the signal is output to the second sub-gate line, and the signals transmitted on the first sub-gate line and the second sub-gate line are ensured to have higher driving capability; compared with the situation that the gate line is connected with the whole sub-pixel row in the prior art, the first sub-gate line and the second sub-gate line are respectively connected with the sub-pixels, so that the load connected with each sub-gate line is reduced, and the high driving capability of the gate line for transmitting signals is further ensured.
In addition, the display device provided by the invention only needs to additionally connect a buffer between the first sub-gate line and the second sub-gate line, the buffer has a simple structure, the influence of the buffer on the aperture opening ratio and the frame width of the display device is avoided, and the high aperture opening ratio of the display device is ensured and the display device conforms to the narrow frame trend.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (12)
1. An array substrate, comprising:
a sub-pixel array including first to Nth sub-pixel rows, N being an integer not less than 2;
the first gate line to the Nth gate line, the ith gate line is connected with the ith sub-pixel row and is used for transmitting scanning signals to the sub-pixels in the corresponding sub-pixel row, and i is a positive integer not greater than N;
wherein at least one of the first to nth gate lines includes a first sub-gate line and a second sub-gate line, and a buffer is connected between an output terminal of the first sub-gate line and an input terminal of the second sub-gate line, the first sub-gate line connects a part of sub-pixels in a corresponding sub-pixel row, and another part of sub-pixels in the corresponding sub-pixel row is connected to the second sub-gate line.
2. The array substrate of claim 1, wherein at least one subpixel at intervals in the subpixel rows connected to the gate lines including the first and second sub-gate lines is divided into two subpixel groups, and one subpixel group is electrically connected to the first sub-gate line and the other subpixel group is electrically connected to the second sub-gate line.
3. The array substrate according to claim 1, wherein in the sub-pixel row connected to the gate lines including the first and second sub-gate lines, all the sub-pixels are sequentially divided into two sub-pixel groups in the arrangement direction of the sub-pixels, and one sub-pixel group is electrically connected to the first sub-gate line and the other sub-pixel group is electrically connected to the second sub-gate line.
4. The array substrate of claim 1, wherein all of the first to N-th gate lines comprise a first sub-gate line and a second sub-gate line.
5. The array substrate of claim 1, wherein the array substrate comprises a display area and a frame area located outside the display area, and the buffer is located in the frame area.
6. The array substrate of claim 1, wherein the array substrate comprises first to nth stage scanning circuits that output the scanning signals stage by stage, wherein an ith stage scanning circuit is electrically connected to the ith gate line;
and in a scanning circuit and a sub-pixel row which are connected with a gate line comprising a first sub-gate line and a second sub-gate line, the scanning circuit and the buffer are respectively positioned at two sides of the pixel row along the sub-pixel arrangement direction in the sub-pixel row.
7. The array substrate of claim 1, wherein the array substrate comprises a first stage scanning circuit to an Nth stage scanning circuit, wherein an ith stage scanning circuit is electrically connected with the ith gate line;
along the sub-pixel arrangement direction in the sub-pixel row, the odd-level scanning circuit and the even-level scanning circuit are respectively positioned at two sides of the sub-pixel array.
8. The array substrate according to any one of claims 1 to 7, wherein the first sub gate line and the second sub gate line connected to the sub pixel row are respectively located at both sides of the sub pixel row in an arrangement direction of all the sub pixel rows.
9. The array substrate of claim 8, wherein a predetermined number of sub-pixels electrically connected to an output side of the first sub-gate line are also electrically connected to the second sub-gate line.
10. The array substrate of claim 8, wherein a predetermined number of sub-pixels electrically connected to an output side of the second sub-gate line are also electrically connected to the first sub-gate line.
11. A display panel comprising the array substrate according to any one of claims 1 to 10.
12. A display device characterized by comprising the display panel according to claim 11.
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