CN110943132B - Low capacitance trench type VDMOS device and preparation method thereof - Google Patents
Low capacitance trench type VDMOS device and preparation method thereof Download PDFInfo
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- CN110943132B CN110943132B CN201911300327.XA CN201911300327A CN110943132B CN 110943132 B CN110943132 B CN 110943132B CN 201911300327 A CN201911300327 A CN 201911300327A CN 110943132 B CN110943132 B CN 110943132B
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- 238000002360 preparation method Methods 0.000 title claims abstract description 21
- 210000000746 body region Anatomy 0.000 claims abstract description 43
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 37
- 229920005591 polysilicon Polymers 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 229910052751 metal Inorganic materials 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 15
- 229920002120 photoresistant polymer Polymers 0.000 claims description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 230000000873 masking effect Effects 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- 238000000206 photolithography Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 18
- 230000003071 parasitic effect Effects 0.000 abstract description 12
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- XHXFXVLFKHQFAL-UHFFFAOYSA-N phosphoryl trichloride Chemical compound ClP(Cl)(Cl)=O XHXFXVLFKHQFAL-UHFFFAOYSA-N 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- QQMBHAVGDGCSGY-UHFFFAOYSA-N [Ti].[Ni].[Ag] Chemical compound [Ti].[Ni].[Ag] QQMBHAVGDGCSGY-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000005380 borophosphosilicate glass Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/668—Vertical DMOS [VDMOS] FETs having trench gate electrodes, e.g. UMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
- H10D30/0297—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs using recessing of the gate electrodes, e.g. to form trench gate electrodes
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
本发明属于半导体芯片制造的技术领域，具体涉及到一种低电容的沟槽型VDMOS器件及其制备方法，器件包括衬底层、外延层、体区及源区，所述外延层设置在所述衬底层上表面，所述体区设置在所述外延层上部，所述源区设置在所述外延层且位于所述体区上部，其特征在于，还包括第一沟槽，其设置在所述外延层，且穿过所述体区和源区；第二沟槽，其设置在所述外延层，所述第二沟槽穿过所述体区，且所述第二沟槽位于所述第一沟槽之间；栅极结构，其设置在所述第一沟槽和所述第二沟槽内。制备方法为制备上述器件的流程。本发明在源区下面通过填充多晶硅，并与源区短接，从而可以起到辅助体区耗尽，增加耗尽层宽度，从而减小器件源漏间寄生电容的目的。
The present invention belongs to the technical field of semiconductor chip manufacturing, and specifically relates to a low-capacitance trench-type VDMOS device and a preparation method thereof, wherein the device comprises a substrate layer, an epitaxial layer, a body region and a source region, wherein the epitaxial layer is arranged on the upper surface of the substrate layer, the body region is arranged on the upper part of the epitaxial layer, and the source region is arranged in the epitaxial layer and located on the upper part of the body region, and is characterized in that it also comprises a first trench, which is arranged in the epitaxial layer and passes through the body region and the source region; a second trench, which is arranged in the epitaxial layer, the second trench passes through the body region, and the second trench is located between the first trenches; and a gate structure, which is arranged in the first trench and the second trench. The preparation method is a process for preparing the above-mentioned device. The present invention fills polysilicon under the source region and short-circuits with the source region, thereby assisting the depletion of the body region, increasing the width of the depletion layer, and thus reducing the parasitic capacitance between the source and drain of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductor chip manufacturing, and particularly relates to a trench type VDMOS device with low capacitance and a preparation method thereof.
Background
In order to reduce the power loss of the chip device, the smaller and better the on-resistance of the device is, and in order to improve the utilization rate of the power device, the parasitic capacitance of the VDMOS needs to be as small as possible, and for the deep trench VDMOS device, the parasitic capacitance exists near the gate and in the depletion layer. In practical application, the parasitic capacitance between gate and drain exists in the trench VDMOS, which results in a relatively low response frequency, and fig. 7 is a schematic structural diagram of a conventional trench VDMOS device. Therefore, it is necessary to reduce the parasitic capacitance of the trench VDMOS.
Current methods for reducing parasitic capacitance of trench VDMOS devices mainly begin with reducing the capacitance of the gate oxide, such as increasing the thickness of the gate oxide as a whole, but this affects other parameters of the VDMOS device, such as the threshold on voltage. The second method is to locally increase the thickness of the gate oxide layer, which can reduce the gate-drain capacitance to a certain extent and avoid the influence of the thickness variation of the gate oxide layer on the threshold voltage, but the method cannot fundamentally solve the above problems and the manufacturing process is much more complicated.
In order to solve the problems, the invention provides a trench type VDMOS device with low capacitance and a preparation method thereof.
Disclosure of Invention
It is an object of the present invention to address at least one of the above problems or disadvantages and to provide at least one advantage as will be described below.
The invention also aims to provide a low-capacitance trench VDMOS device and a preparation method thereof, wherein polysilicon is filled under a source region and is in short circuit with the source region, so that the purpose of assisting in body region depletion and increasing the width of a depletion layer can be achieved, and the parasitic capacitance between source and drain of the device is reduced.
To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, there is provided a trench type VDMOS device having a low capacitance, comprising a substrate layer, an epitaxial layer, a body region, and a source region, wherein the epitaxial layer is disposed on an upper surface of the substrate layer, the body region is disposed on an upper portion of the epitaxial layer, and the source region is disposed on the epitaxial layer and on an upper portion of the body region, characterized by further comprising:
a first trench disposed in the epitaxial layer, the first trench passing through the body region and the source region;
and the second groove is arranged on the epitaxial layer, penetrates through the body region and is positioned between the first grooves.
And a gate structure disposed within the first trench and the second trench.
Preferably, the gate structure includes:
a gate oxide layer covering surfaces of the first trench and the second trench;
and a polysilicon layer filling the remaining space in the first trench and the second trench.
Preferably, the polysilicon layer includes a first polysilicon layer and the second polysilicon layer, the first polysilicon layer is located in the first trench, and the second polysilicon layer is located in the second trench;
The polysilicon layer is a P-type polysilicon layer, the polysilicon is undoped, the polysilicon is doped by POCL3 (phosphorus oxychloride) to have P-type characteristic, and the main purpose of doping is to perform low resistance treatment on the polysilicon region.
Preferably, the semiconductor device further comprises a dielectric layer, a source metal layer and a drain metal layer, wherein the dielectric layer is arranged on the upper surface of the epitaxial layer and covers the gate structure in the first groove, the source metal layer covers the dielectric layer and contacts with the gate structure in the second groove, and the drain metal layer is arranged on the lower surface of the substrate layer.
Preferably, the depth of the first trench exceeds the depth of the body region, and the depth of the second trench is less than the depth of the body region.
Preferably, the source region is an n+ source region, the body region is a P-body region, the epitaxial layer is an N-epitaxial layer, and the substrate layer is an n+ substrate layer.
The invention also provides a preparation method of the low-capacitance trench VDMOS device, which comprises the following steps:
Manufacturing a shallow groove on the epitaxial layer to form a second groove and a first preparation groove;
Deep etching is carried out on the first preparation grooves to form first grooves, and the second grooves are located between the first grooves;
generating a gate structure in the first trench and the second trench;
manufacturing a body region on the epitaxial layer, and enabling the first groove and the second groove to pass through the body region;
a source region is manufactured in the body region, and the first groove penetrates through the source region;
Manufacturing a dielectric layer on the surface of the source region;
And manufacturing a source electrode metal layer on the upper surface of the dielectric layer, and manufacturing a drain electrode metal layer on the lower surface of the substrate layer.
Preferably, the fabricating a shallow trench in the epitaxial layer to form a second trench and a first preliminary trench includes:
Forming an oxide layer of silicon dioxide on the upper surface of the epitaxial layer;
And etching a groove window on the oxide layer by photoetching, and etching a shallow groove under the masking of the oxide layer to form a second groove and a first preparation groove.
Preferably, the deep etching the first preliminary trenches to form first trenches, and the second trenches are located between the first trenches, including:
Covering the oxide layer and the second groove with photoresist, and carrying out deep etching on the first preparation groove under the masking of the photoresist and the oxide layer;
and after etching is finished, removing the photoresist and the oxide layer to form a first groove, wherein the depth of the first groove is larger than that of the second groove.
Preferably, the generating the gate structure in the first trench and the second trench includes:
Growing a gate oxide layer on the inner surfaces of the first groove and the second groove;
and filling P-type polycrystalline silicon in the residual spaces in the first groove and the second groove.
The beneficial effects of the invention are that
1. The trench type VDMOS device with low capacitance provided by the invention achieves the purpose of reducing parasitic capacitance between source and drain of the device by increasing the width of the depletion layer.
2. The trench type VDMOS device with low capacitance has the advantage of low conduction loss, and the switching loss of the device is reduced.
3. According to the trench type VDMOS device with the low capacitance, the P type polycrystalline silicon is filled below the source region and is in short circuit with the N+ region of the source electrode, so that the depletion of the auxiliary body region can be achieved, and the width of a depletion layer of a P-/N-junction can be increased.
4. The invention provides a preparation method of a low-capacitance trench VDMOS device, which has simple manufacturing flow and easy operation, reduces parasitic capacitance of the device and simultaneously saves manufacturing cost.
Drawings
Fig. 1 is a schematic cross-sectional structure of a trench VDMOS device with low capacitance according to the present invention;
fig. 2 is a flow chart of the preparation of the trench type VDMOS device with low capacitance according to the present invention;
FIG. 3 is a schematic diagram of the etched structure of the first preliminary trench and the second trench according to the present invention;
FIG. 4 is a schematic diagram of the structure of the etched first and second trenches according to the present invention;
FIG. 5 is a schematic diagram of a gate oxide layer formation structure according to the present invention;
FIG. 6 is a schematic diagram of a polysilicon layer formation structure according to the present invention;
fig. 7 is a schematic structural diagram of a conventional trench VDMOS device;
In the figure, the 1-substrate layer, the 2-epitaxial layer 2, 3-body, the 4-source, the 5-first trench, the 6-second trench, the 7-gate structure, the 71-gate oxide layer, the 72-first polysilicon layer, the 73-second polysilicon layer, the 8-dielectric layer, the 9-source metal layer, the 10-drain metal layer, and the 11-first preliminary trench.
Detailed Description
The present invention is described in further detail below with reference to the drawings to enable those skilled in the art to practice the invention by referring to the description.
It will be understood that terms, such as "having," "including," and "comprising," as used herein, do not preclude the presence or addition of one or more other elements or groups thereof.
As shown in fig. 1, the present invention provides a low-capacitance trench VDMOS device, which includes a substrate layer 1, an epitaxial layer 2, a body region 3, and a source region 4, wherein the epitaxial layer 2 is disposed on the upper surface of the substrate layer 1, the body region 3 is disposed on the upper portion of the epitaxial layer 2, and the source region 4 is disposed on the epitaxial layer 2 and is located on the upper portion of the body region 3, and is characterized in that the device further includes:
a first trench 5 provided in the epitaxial layer 2, the first trench 5 passing through the body region 3 and the source region 4;
A second trench 6 is provided in the epitaxial layer 2, the second trench 6 passing through the body region 3, and the second trench 6 being located between the first trenches 5.
A gate structure 7 disposed within the first trench 5 and the second trench 6.
The source region is an N+ source region, the body region is a P-body region, the epitaxial layer is an N-epitaxial layer, and the substrate layer is an N+ substrate layer. Because the device is an N-channel device, the substrate layer adopted by the invention is an N-type substrate layer 1, and an N-type epitaxial layer 2 is grown on the N-type substrate layer 1.
Specifically, the epitaxial layer further comprises a dielectric layer 8, a source metal layer 9 and a drain metal layer 10, wherein the dielectric layer 8 is arranged on the upper surface of the epitaxial layer 2 and covers the gate structure 7 in the first trench 5, the source metal layer 9 covers the dielectric layer 8 and contacts with the gate structure 7 in the second trench 6, the drain metal layer 10 is arranged on the lower surface of the substrate layer 1,
Specifically, the gate structure 7 includes:
A gate oxide layer 71 covering the surfaces of the first trench 5 and the second trench 6;
A polysilicon layer filling the remaining space within the first trench 5 and the second trench 6.
Specifically, the polysilicon layer is a P-type polysilicon layer.
Specifically, the polysilicon layer includes a first polysilicon layer 72 and the second polysilicon layer 73, the first polysilicon layer 72 is located in the first trench 5, and the second polysilicon layer 73 is located in the second trench 6;
the depth of the first groove exceeds the depth of the body region, and the depth of the second groove is smaller than the depth of the body region.
Specifically, the metal of the source electrode comprises tungsten metal (good in conductivity) filled in the hole and aluminum copper metal covered on the surface, and belongs to an alloy layer. The drain metal, i.e., the back metal, is mainly composed of titanium nickel silver. The dielectric layer is an oxide layer region under the metal, over the silicon and polysilicon, and often contains multiple layers of doped or undoped phosphosilicate glass, such as LPTEOS, USG, PSG, BPSG, which is predominantly silicon dioxide.
The P-type polysilicon is filled under the source region and is in short circuit with the N+ region of the source electrode, so that the depletion of the auxiliary body region is realized, and the short circuit is that the N+ position is strictly connected with the second groove position of the buried layer. The position of filling the P-type polycrystalline silicon is positioned below the normal groove type MOS source region, which is equivalent to forming a buried layer in the P-body region, and the main purpose of manufacturing the buried layer is to assist the P-body to deplete towards the bottom epitaxial layer, so that the area of the depletion region is increased. The principle of plate capacitance shows that the capacitance of the depletion region in the semiconductor is reduced by doing so, namely the capacitance between the source and the drain is reduced. If we want to ensure that the turn-on voltage is normal, we need to ensure that the effective length of the channel does not change, and the increase in length of the P-body will also affect the increase in capacitance of the insulating oxide.
The invention also provides a preparation method of the low-capacitance trench VDMOS device, as shown in figure 2, comprising the following steps:
Manufacturing a shallow groove on the epitaxial layer to form a second groove and a first preparation groove;
Deep etching is carried out on the first preparation grooves to form first grooves, and the second grooves are located between the first grooves;
generating a gate structure in the first trench and the second trench;
And forming the body region, wherein the first groove and the second groove penetrate through the body region, and the step of forming the body region can be completed at any step before the step of manufacturing the dielectric layer in a conventional manufacturing process.
A source region is manufactured in the body region, and the first groove penetrates through the source region;
Manufacturing a dielectric layer on the surface of the source region;
And manufacturing a source electrode metal layer on the upper surface of the dielectric layer, and manufacturing a drain electrode metal layer on the lower surface of the substrate layer.
According to the preparation method, the second groove is added below the source region, so that the grid structure in the second groove is in short circuit with the source N+ region, the depletion of the auxiliary body region can be achieved, the width of the depletion layer is increased, and the purpose of reducing parasitic capacitance between the source and the drain of the device is achieved.
In addition to the foregoing embodiment, as shown in fig. 3, in another embodiment, the fabricating a shallow trench in an epitaxial layer to form a second trench and a first preliminary trench includes:
Forming an oxide layer of silicon dioxide on the upper surface of the epitaxial layer, wherein the surface of the device is easily damaged in the etching process, and the device can be effectively protected by presetting an initial oxide layer;
And etching a groove window on the oxide layer by photoetching, and etching a shallow groove under the masking of the oxide layer to form a second groove and a first preparation groove.
In addition to the foregoing embodiment, as shown in fig. 4, in a further embodiment, the deep etching the first preliminary trench to form a first trench, where the second trench is located between the first trenches, includes:
Covering the oxide layer and the second groove by using photoresist, namely, the photoetching only needs to use the photoresist to block the middle second groove, and under the masking of the photoresist and the oxide layer, the first preparation groove is deeply etched;
And after etching is finished, removing the oxide layer and the photoresist on the surface to form a first groove, wherein the depth of the first groove is larger than that of the second groove.
The second groove is used as a shallow groove to be designed for introducing a buried layer, current is led to extend an electric field line to the bottom of a trench through the edge of the trench structure morphology, the width of a P-body region depletion region is increased, and the capacitance between a source and a drain is reduced on the basis of ensuring UIS capability.
Whereas conventional trench-type VDMOS devices (as shown in fig. 7) have only two trenches of the same depth, the problem of reducing parasitic capacitance cannot be solved.
In addition to the foregoing embodiments, in yet another embodiment, as shown in fig. 5 and fig. 6, the generating a gate structure in the first trench and the second trench includes:
Growing a gate oxide layer on the inner surfaces of the first groove and the second groove, as shown in fig. 5;
The first polysilicon layer is filled in the residual space in the first groove, the second polysilicon layer is filled in the residual space in the second groove, and the step is different from the conventional mode, a plurality of second polysilicon layers in the second groove are added, which are not in contact with the source region, but form short circuit with the source electrode, so that the auxiliary body region is used up, the width of the depletion layer is increased, and the purpose of reducing parasitic capacitance between source and drain of the device is achieved.
The first polysilicon layer and the second polysilicon layer are P-type polysilicon layers.
The polysilicon deposition process is synchronous, and the doping type is realized by two modes, namely, in the growth process, the vapor particles are grown and doped, and the deposition is carried out before the doping injection.
The invention has other alternative embodiments, which will not be described in detail here.
Although embodiments of the present invention have been disclosed above, it is not limited to the details and embodiments shown and described, it is well suited to various fields of use for which the invention would be readily apparent to those skilled in the art, and accordingly, the invention is not limited to the specific details and illustrations shown and described herein, without departing from the general concepts defined in the claims and their equivalents.
Claims (2)
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| CN201911300327.XA CN110943132B (en) | 2019-12-17 | 2019-12-17 | Low capacitance trench type VDMOS device and preparation method thereof |
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| WO2005065385A2 (en) * | 2003-12-30 | 2005-07-21 | Fairchild Semiconductor Corporation | Power semiconductor devices and methods of manufacture |
| EP2248159A4 (en) * | 2008-02-14 | 2011-07-13 | Maxpower Semiconductor Inc | SEMICONDUCTOR DEVICE STRUCTURES AND METHODS RELATING THERETO |
| US8203181B2 (en) * | 2008-09-30 | 2012-06-19 | Infineon Technologies Austria Ag | Trench MOSFET semiconductor device and manufacturing method therefor |
| JP5849882B2 (en) * | 2011-09-27 | 2016-02-03 | 株式会社デンソー | Semiconductor device provided with vertical semiconductor element |
| JP6304445B2 (en) * | 2015-03-16 | 2018-04-04 | 富士電機株式会社 | Manufacturing method of semiconductor device |
| CN109119476A (en) * | 2018-08-23 | 2019-01-01 | 电子科技大学 | Separate gate VDMOS device and its manufacturing method with internal field plate |
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| CN104241386A (en) * | 2014-09-25 | 2014-12-24 | 无锡新洁能股份有限公司 | Power MOSFT (metal-oxide -semiconductor field effect transistor) device with low specific on-resistance and manufacturing method of power MOSFT device |
| CN106257684A (en) * | 2015-06-16 | 2016-12-28 | 北大方正集团有限公司 | The manufacture method of VDMOS device and VDMOS device |
| CN105789288A (en) * | 2016-03-15 | 2016-07-20 | 江苏中科君芯科技有限公司 | IGBT device with integrated gate-source capacitance |
| CN211017087U (en) * | 2019-12-17 | 2020-07-14 | 华羿微电子股份有限公司 | Low-capacitance groove type VDMOS device |
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