CN110943070A - Semiconductor structure, method for making semiconductor structure and use thereof - Google Patents
Semiconductor structure, method for making semiconductor structure and use thereof Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76832—Multiple layers
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Layout of the interconnection structure
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Abstract
本发明提供一种半导体结构，半导体结构制备方法及其用途，所述制备方法包括，提供一衬底，所述衬底中嵌有至少一个第一金属结构；所述第一金属结构顶面与所述衬底顶面处于同一平面；于所述衬底上形成一层间介质层；于所述层间介质层中形成至少一个沟槽，所述沟槽显露出所述第一金属结构顶面；于所述沟槽侧壁形成一扩散阻挡层；以及于形成有所述扩散阻挡层的所述沟槽中形成第二金属结构，所述第二金属结构与所述第一金属结构直接接合以实现电连接。利用本发明，通过去除底部的扩散阻挡层，不仅降低互连接触电阻，减少RC延迟，而且还能保护层间介质层，提高通孔填充质量，另外还能采用绝缘材料作为扩散阻挡层，提高器件的电性能稳定性和可靠性。
The present invention provides a semiconductor structure, a method for preparing the semiconductor structure and its use, the method comprising providing a substrate, wherein at least one first metal structure is embedded in the substrate; the top surface of the first metal structure is in the same plane as the top surface of the substrate; forming an interlayer dielectric layer on the substrate; forming at least one groove in the interlayer dielectric layer, wherein the groove exposes the top surface of the first metal structure; forming a diffusion barrier layer on the sidewall of the groove; and forming a second metal structure in the groove having the diffusion barrier layer formed therein, wherein the second metal structure is directly bonded to the first metal structure to achieve electrical connection. By using the present invention, by removing the diffusion barrier layer at the bottom, not only the interconnection contact resistance is reduced, the RC delay is reduced, but also the interlayer dielectric layer can be protected, the through-hole filling quality is improved, and insulator material can be used as the diffusion barrier layer to improve the electrical performance stability and reliability of the device.
Description
Technical Field
The present invention relates to the field of semiconductor manufacturing, and more particularly to semiconductor structures, methods of making semiconductor structures, and uses thereof.
Background
In semiconductor manufacturing, with the trend of very large scale integrated circuits, the feature size of the integrated circuit is smaller and smaller, and the interconnection resistance becomes one of the important factors influencing the electrical performance and reliability of the semiconductor device. The delay of a back-end interconnection Resistor Capacitor (RC) tends to increase significantly, which affects the performance of a semiconductor device. In order to reduce the RC delay, on one hand, the metal wire is developed from the original metal aluminum interconnection line to a metal copper interconnection line to reduce the wire resistance R, and on the other hand, the interlayer dielectric material uses a Low-K material with a lower dielectric constant K to reduce the parasitic capacitance C.
The by-products formed by the common copper dry etching are not easy to volatilize, and a Damascus process is introduced to prepare the metal copper interconnection line, wherein the basic process comprises the steps of etching a through hole or a groove, and then filling a barrier layer, a copper seed crystal layer, electroplating copper and CMP, so that the problem of copper etching is avoided. Later dual damascene processes were developed in which vias and trenches were formed in the dielectric layer, which then also required filling of barrier layers, copper seed layers, copper electroplating, CMP.
The resistivity of the commonly used diffusion barrier layer material is far larger than that of copper, so that the interconnection resistance is increased, the electrical property and the reliability of the semiconductor device are influenced, and according to a resistance formula R ═ rho L/S (rho is the resistivity of the diffusion barrier layer material, and L is the thickness of the diffusion barrier layer material), the thicker the diffusion barrier layer is, the larger the influence on the electrical property and the reliability of the semiconductor device is.
In addition, Ar ion etching is adopted to thin the barrier layer at present so as to reduce resistance, but the selectivity to materials is Low during high-energy Ar bombardment, so that ① diffusion barrier layer side walls and steps (dual damascene structures) are easy to generate local defects (bombardment and sputtering effects) to cause Cu diffusion, the stability of the device is reduced, ② damage to Low-k interlayer dielectric layer materials with poor mechanical properties, even stress deformation, subsequent Cu filling is influenced, and the electrical property stability and reliability of the device are influenced.
Therefore, finding a semiconductor structure capable of reducing the contact resistance of metal interconnects in the semiconductor structure and a method for fabricating the semiconductor structure become an important technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a semiconductor structure, a method for manufacturing the semiconductor structure, and a use thereof, which are used to solve the problem of poor electrical stability and reliability of a semiconductor device caused by large contact resistance of a metal interconnection structure in the prior art.
To achieve the above and other related objects, the present invention provides a method for fabricating a semiconductor structure, comprising:
providing a substrate, wherein at least one first metal structure is embedded in the substrate; the top surface of the first metal structure and the top surface of the substrate are positioned on the same plane;
forming an interlayer dielectric layer on the substrate;
forming at least one groove in the interlayer dielectric layer, wherein the groove exposes the top surface of the first metal structure;
forming a diffusion barrier layer on the side wall of the groove; and
and forming a second metal structure in the groove with the diffusion barrier layer formed on the side wall, wherein the second metal structure is directly jointed with the first metal structure to realize electric connection joint.
As an improvement of the above semiconductor structure manufacturing method of the present invention, the step of forming the diffusion barrier layer on the trench sidewall includes:
forming a diffusion barrier material on the inner wall of the groove;
and removing the diffusion barrier layer material at the bottom of the groove to expose the top surface of the first metal structure.
As an improvement of the above semiconductor structure preparation method of the present invention, a first stop layer is further formed between the substrate and the interlayer dielectric layer, and a second stop layer is further formed on the interlayer dielectric layer; the step of forming the trench includes:
and forming at least one groove in the second stop layer, the interlayer dielectric layer and the first stop layer, wherein the groove exposes the top surface of the first metal structure.
As an improvement of the above semiconductor structure manufacturing method of the present invention, the step of forming the diffusion barrier layer on the trench sidewall includes:
forming a diffusion barrier material on the inner wall of the groove;
and etching and removing the diffusion barrier layer material at the bottom of the groove by taking the second stop layer as a mask to expose the top surface of the first metal structure.
As an improvement of the above semiconductor structure manufacturing method of the present invention, the step of forming the diffusion barrier layer on the sidewall of the trench includes:
forming a diffusion barrier material on the inner wall of the groove;
filling a sacrificial layer in the groove formed with the diffusion barrier layer material, wherein the top surface of the sacrificial layer is higher than the top surface of the diffusion barrier layer material;
forming a patterned first photoresist layer on the sacrificial layer, wherein the patterned first photoresist layer is provided with at least one second opening which is used as a window for subsequently etching the diffusion barrier layer material at the bottom of the groove;
etching the sacrificial layer and the diffusion barrier layer material downwards in sequence by taking the patterned first photoresist layer as a mask to expose the top surface of the first metal structure;
and removing the residual patterned first photoresist layer and the residual sacrificial layer.
As an improvement of the above semiconductor structure preparation method of the present invention, a first stop layer is further formed between the substrate and the interlayer dielectric layer, and a second stop layer is further formed on the interlayer dielectric layer; the preparation method further comprises the following steps:
forming at least one groove in the second stop layer and the interlayer dielectric layer, wherein the groove exposes the first stop layer;
forming a diffusion barrier material on the inner wall of the groove;
removing the diffusion barrier layer material at the bottom of the trench to form the diffusion barrier layer on the side wall of the trench and expose the first stop layer;
removing the exposed part of the first stop layer to form a first opening in the first stop layer, wherein the first opening exposes the top surface of the first metal structure; and
and forming the second metal structure in the groove with the diffusion barrier layer on the side wall and the first opening, wherein the second metal structure is directly connected with the first metal structure through the first opening so as to realize electric connection.
As an improvement to the above semiconductor structure manufacturing method of the present invention, the manufacturing method further includes:
after a diffusion barrier material is formed on the inner wall of the trench, the diffusion barrier material and the first stop layer at the bottom of the trench are sequentially etched downwards by using the second stop layer and the diffusion barrier material on the surface of the second stop layer as masks, so that a first opening is formed in the first stop layer, and the top surface of the first metal structure is exposed by the first opening;
and forming the second metal structure in the groove with the diffusion barrier layer on the side wall and the first opening, wherein the second metal structure is connected with the first metal structure through the first opening to realize electric connection.
As an improvement to the above semiconductor structure manufacturing method of the present invention, the manufacturing method further includes:
filling a sacrificial layer in the groove with the diffusion barrier layer material formed on the inner wall, wherein the top surface of the sacrificial layer is higher than the top surface of the diffusion barrier layer material;
forming a patterned first photoresist layer on the sacrificial layer, wherein the patterned first photoresist layer is provided with at least one second opening which is used as a window for subsequently etching the diffusion barrier layer material at the bottom of the groove;
etching the sacrificial layer and the diffusion barrier layer material in sequence downwards by taking the patterned first photoresist layer as a mask until the first stop layer is exposed;
removing the remaining patterned first photoresist layer and the remaining sacrificial layer to expose the diffusion barrier material on the second stop layer, and etching the first stop layer downward using the second stop layer and the diffusion barrier material on the surface thereof as masks to form the first opening in the first stop layer, wherein the first opening exposes the top surface of the first metal structure;
and forming the second metal structure in the groove with the diffusion barrier layer and the first opening, wherein the second metal structure is directly jointed with the first metal structure through the first opening so as to realize electric connection.
As an improvement to the above semiconductor structure manufacturing method of the present invention, the manufacturing method further includes:
filling a sacrificial layer in the groove with the diffusion barrier layer material formed on the inner wall, wherein the top surface of the sacrificial layer is higher than the top surface of the diffusion barrier layer material;
forming a patterned first photoresist layer on the sacrificial layer, wherein the patterned first photoresist layer is provided with at least one second opening which is used as a window for subsequently etching the diffusion barrier layer material at the bottom of the groove;
etching the sacrificial layer, the diffusion barrier layer material and the first stop layer in sequence downwards by taking the patterned first photoresist layer as a mask so as to form a first opening in the first stop layer, wherein the first opening exposes the top surface of the first metal structure;
removing the residual patterned first photoresist layer and the residual sacrificial layer;
and forming a second metal structure in the groove with the diffusion barrier layer formed on the side wall, wherein the second metal structure is jointed with the first metal structure through the first opening so as to realize electric connection.
As an improvement to the above semiconductor structure fabrication method of the present invention, the thickness of the second stop layer is greater than the thickness of the first stop layer; the thickness of the second stop layer is 200-250% of the thickness of the first stop layer.
As an improvement to the above semiconductor structure fabrication method of the present invention, the sacrificial layer includes a mask layer and an anti-reflection layer on the sacrificial layer.
As an improvement to the above-described semiconductor structure fabrication method of the present invention, the method of etching the diffusion barrier material includes using a conventional dry etch process or atomic layer etch process.
As an improvement to the above semiconductor structure fabrication method of the present invention, the diffusion barrier layer material comprises a conductive diffusion barrier layer material or an insulating diffusion barrier layer material; the conductive diffusion barrier layer material comprises one of titanium nitride, tantalum, tungsten nitride, tantalum nitride and ruthenium; the insulating diffusion barrier layer material comprises one of silicon nitride and silicon oxynitride.
As an improvement of the above semiconductor structure manufacturing method of the present invention, the step of forming the second metal structure in the trench in which the diffusion barrier layer is formed includes:
filling a second metal material in the groove with the diffusion barrier layer;
and carrying out planarization treatment on the structure filled with the second metal material so as to form the second metal structure in the groove formed with the diffusion barrier layer.
As an improvement of the above semiconductor structure manufacturing method of the present invention, the step of filling the trench formed with the diffusion barrier layer with a second metal material includes:
forming a seed crystal layer on the inner surface of the groove on which the diffusion barrier layer is formed;
filling the second metal material in the groove formed with the seed crystal layer;
and carrying out planarization treatment on the structure filled with the second metal material so as to form the second metal structure in the groove formed with the diffusion barrier layer.
As an improvement of the above semiconductor structure preparation method of the present invention, a step of removing the residue of the top surface of the first metal structure and the oxide layer is further included between the step of removing the remaining patterned first photoresist layer and the remaining sacrificial layer and the step of forming the second metal structure.
To achieve the above and other related objects, the present invention also provides a semiconductor structure comprising:
a substrate having at least one first metal structure embedded in a surface thereof;
the interlayer dielectric layer is formed on the substrate, at least one groove is formed in the interlayer dielectric layer, and the groove exposes the top surface of the first metal structure;
a diffusion barrier layer formed on the side wall of the trench; and
and the second metal structure is filled in the groove formed with the diffusion barrier layer, and is directly jointed with the first metal structure to realize electric connection.
As an improvement to the above semiconductor structure of the present invention, the semiconductor structure further comprises:
the first stop layer is positioned between the substrate and the interlayer dielectric layer;
the second stop layer is positioned above the interlayer dielectric layer;
the groove is formed in the second stop layer, the interlayer dielectric layer and the first stop layer, and the top surface of the first metal structure is exposed.
As an improvement to the above semiconductor structure of the present invention, the semiconductor structure further comprises:
the first stop layer is positioned between the substrate and the interlayer dielectric layer and is provided with at least one first opening;
the second stop layer is positioned above the interlayer dielectric layer;
the groove is formed in the second stop layer and the interlayer dielectric layer, and the groove exposes the first opening and a part of the first stop layer located on the periphery of the first opening;
the bottom of the diffusion barrier layer is connected with the surface of the first stop layer exposed by the groove;
the second metal structure is filled in the groove formed with the diffusion barrier layer and the first opening, and the second metal structure is directly jointed with the first metal structure through the first opening to realize electric connection.
As an improvement to the above semiconductor structure of the present invention, the top surface of the second stop layer, the top surface of the diffusion barrier layer, and the top surface of the first metal structure are formed on the same polishing plane.
As an improvement of the above semiconductor structure of the present invention, the second metal structure includes a main body portion and a seed layer, and the seed layer is disposed on an outer surface of the main body portion, which does not include an upper surface.
As an improvement to the above semiconductor structure of the present invention, the substrate includes a third stop layer and a bottom dielectric layer on the third stop layer; at least one of the first metal structures is embedded in the bottom dielectric layer and the third stop layer.
As an improvement to the above semiconductor structure of the present invention, the diffusion barrier layer material includes a conductive diffusion barrier layer material or an insulating diffusion barrier layer material; the conductive diffusion barrier layer material comprises one of titanium nitride, tantalum, tungsten nitride, tantalum nitride and ruthenium; the insulating diffusion barrier layer material comprises one of silicon nitride and silicon oxynitride.
In order to achieve the above objects and other related objects, the present invention also provides the use of the above semiconductor structure fabrication method applied to a single damascene process and a dual damascene process.
By utilizing the invention, the diffusion barrier layer at the contact part of the metal interconnection structure is removed by etching, so that the interconnection contact resistance between the upper and lower layers of metal structures can be reduced, the RC delay is reduced, the speed of a semiconductor device is improved, and the reliability of the device is ensured;
by using the method, the diffusion barrier layer material at the bottom of the Damascus structure is removed, and the interlayer dielectric layer is protected, so that the filling quality of the through hole is improved, and the electrical property stability and the device reliability of the semiconductor device are improved;
according to the invention, because the diffusion barrier layer between the first metal structure and the second metal structure is removed, the first metal structure and the second metal structure can be directly jointed to realize electric connection, and the diffusion barrier layer material is selected only by considering the capability of the diffusion barrier layer material for blocking the diffusion of the second metal material (such as Cu) and not considering the conductive characteristic of the diffusion barrier layer material, so that an insulating material with better capability of blocking the diffusion of the second metal material (such as Cu) can be selected for the diffusion barrier layer, and the electrical property stability and the device reliability of the semiconductor device are further improved.
Drawings
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure according to the present invention.
Fig. 2a-2g are schematic structural diagrams illustrating the preparation of trenches a and B in the semiconductor structure preparation method of the present invention.
FIG. 3 is a schematic view of a structure of a substrate in the method for fabricating a semiconductor structure according to the present invention.
Fig. 4a-4d are schematic structural views illustrating a method for fabricating a semiconductor structure according to a first embodiment of the present invention.
Fig. 5a-5f are schematic structural views illustrating a second embodiment of the method for fabricating a semiconductor structure according to the present invention.
Fig. 6a to 6f are schematic structural views illustrating a method for fabricating a semiconductor structure according to a third embodiment of the present invention.
Fig. 7a to 7c are schematic structural views illustrating a fourth embodiment of the method for fabricating a semiconductor structure according to the present invention.
Fig. 8a to 8f are schematic structural views illustrating a fifth embodiment of the method for fabricating a semiconductor structure according to the present invention.
Fig. 9a to 9f are schematic structural views illustrating a sixth embodiment of the method for fabricating a semiconductor structure according to the present invention.
Fig. 10-12 show three defect diagrams for the ion thinning process used to thin the diffusion barrier layer in the present invention.
Description of the element reference numerals
1 substrate
11 first metal structure
12 third stop layer
13 bottom dielectric layer
2 first stop layer
3 interlayer dielectric layer
31 deformation part
4 second stop layer
5 diffusion barrier layer
51 defective part
50 diffusion barrier material
6 second metal structure
61 seed crystal layer
62 body portion
71 first sacrificial layer
72 second sacrificial layer
81 first antireflection layer
82 second anti-reflection layer
91 the third photoresist layer
92 second photoresist layer
93 the first photoresist layer
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1-12. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed.
FIG. 1 is a flow chart of a method of fabricating a semiconductor structure of the present invention, the method comprising the steps of:
performing step S10, as shown in fig. 2a, providing a substrate 1, wherein at least one first metal structure 11 is embedded in the substrate 1; the top surface of the first metal structure 11 and the top surface of the substrate 1 are in the same plane. For example, the substrate 1 may be a general semiconductor structure after a Front End Of Line (FEOL) process is completed, and the first metal structure 11 includes an electrical connection terminal (for example, a gate terminal Of a transistor device) for making an electrical connection with the outside or a contact portion formed on the electrical connection terminal (for example, a contact portion formed on a source/drain terminal Of the transistor device).
In one embodiment, as shown in fig. 3, the substrate 1 also includes a third stop layer 12 and a bottom dielectric layer 13 on the third stop layer 12; at least one of the first metal structures 11 is embedded in the bottom dielectric layer 13 and the third stop layer 12.
The substrate 1 shown in fig. 2 or fig. 3 can be obtained in a variety of ways by a person skilled in the art by means of front-end processes. Here, details of the manufacturing of the substrate 1 will not be described.
As shown in fig. 2a-2g, step S20 is performed, as shown in fig. 2a-2g, an interlayer dielectric layer 3 is formed on the substrate 1, and then step S30 is performed to form at least one trench in the interlayer dielectric layer 3, wherein the trench exposes the top surface of the first metal structure 11. The trenches include a type a trench (hereinafter referred to as trench a) formed through a one-step photolithography process as shown in fig. 2B and a type B trench (hereinafter referred to as trench B) having a step shape formed through a two-or multi-step photolithography process as shown in fig. 2 g.
The step of forming the trench a includes:
as shown in fig. 2a-2b, first, a first stop layer 2, an interlayer dielectric layer 3, a second stop layer 4 and a third photoresist layer 91 are sequentially formed on the substrate 1; secondly, the third photoresist layer 91 is patterned to form an opening in the third photoresist layer 91; then, the second stop layer 4 and the interlayer dielectric layer 3 are sequentially etched downward using the patterned third photoresist layer 91 as a mask to form a trench a in the second stop layer 4 and the interlayer dielectric layer 3. It should be noted that the first stop layer 2 under the trench a is opened in the subsequent step to form a first opening, so as to expose the top surface of the first metal structure 11 under the first stop layer 2.
The first stop layer 2 and the second stop layer 4 may be made of, for example, silicon nitride (Si)3N4) Or silicon carbide, although other suitable materials may be used, without limitation, and silicon nitride (Si) may be used as an example3N4)。
In order to reduce the distributed capacitance between the layers and the delay time of signal transmission, the interlayer dielectric layer 3 may use a low-k dielectric material (low-k material), which refers to a dielectric material with a dielectric constant lower than that of SiO2, and the dielectric constant ranges between the dielectric constant of air and that of SiO2, and the low-k dielectric materials that may be used include but are not limited to SiF, SiOC, parylene, HSQ, and xerogel, and the low dielectric material is required to have a k value as low as possible, and the following conditions should be satisfied: good thermal stability, high mechanical strength, high thermal conductivity, good dimensional stability, easy patterning and corrosion, and compatibility with IC processes, such as cleaning, etching, CMP, and heat treatment.
It should be noted that, in order to effectively reduce the problems of line deformation and surface roughness increase of the patterned photoresist layer caused by light reflection, standing wave and other factors in the photolithography process, an anti-reflection layer (not shown) may be formed between the second stop layer 4 and the third photoresist layer 91. In an embodiment, the second stop layer 4 may also function as an anti-reflective layer.
As shown in fig. 2a to 2g, the step of forming the trench B includes, first, as shown in fig. 2a and 2B, performing the step of forming the trench a; next, as shown in fig. 2c, filling the first sacrificial layer 71 material into the surface of the structure (the surface of the second stop layer 4) where the trench a is formed and the trench a, and performing a planarization process (e.g., chemical mechanical polishing CMP) to form a first sacrificial layer 71; then, as shown in fig. 2d, a second photoresist layer 92 is formed on the first sacrificial layer 71, and the second photoresist layer 92 is patterned to form an opening in the second photoresist layer 92, wherein the size of the opening in the second photoresist layer 92 is larger than the size of the trench a and the projection thereof includes the trench a; then, as shown in fig. 2e and 2f, the second sacrificial layer 72, the second stop layer 4 and the interlayer dielectric layer 3 with a partial thickness are sequentially etched downward by using the patterned second photoresist layer 92 as a mask; finally, as shown in FIG. 2g, the excess material of the second photoresist layer 92 and the excess material of the first sacrificial layer 71 are removed to form a trench B having a step shape. It should be noted that the first stop layer 2 under the trench B is also opened in the subsequent step to form a first opening, so as to expose the top surface of the first metal structure 11 under the first stop layer 2.
It should be noted that, as shown in fig. 2c, in order to effectively reduce the problems of line deformation and increased surface roughness of the patterned photoresist layer caused by light reflection, standing wave and the like in the photolithography process, a first anti-reflection layer 81 is further formed between the first sacrificial layer 71 and the second photoresist layer 92.
It should be noted that other non-photolithography processes such as injection laser etching may also be used to prepare the trench structure, which is not limited to this.
Step S40 is performed to form a diffusion barrier layer 5 on the trench sidewall. Two embodiments are included in the order of formation of the first opening in the first stop layer 2 and the diffusion barrier layer 5.
In a first embodiment, first, the portion of the first stop layer 2 under the trench a/the trench B in fig. 2B/fig. 2g is opened to form a first opening in the first stop layer 2, which first opening together with the trench a/the trench B serves as a trench for forming the diffusion barrier layer 5 to expose the top surface of the first metal structure 11 under the first stop layer 2; then, forming a diffusion barrier layer material 50 on the inner wall of the trench; finally, the diffusion barrier material 50 at the bottom of the trench is removed, exposing the top surface of the first metal structure 11.
In one embodiment, the step of forming the diffusion barrier layer 5 on the trench sidewall includes: first, the part of the first stop layer 2 under the trench a in fig. 2b is opened to form a first opening in the first stop layer 2, which serves as a trench for forming a diffusion barrier 5 together with the trench a to expose the first metal structure 11 under the first stop layer 2, resulting in the structure shown in fig. 4 a; next, as shown in fig. 4b, a diffusion barrier material 50 is formed on the inner wall of the trench as shown in fig. 4 a; again, as shown in fig. 4c, the diffusion barrier material 50 at the bottom of the trench is removed by etching using the second stop layer 4 as a mask, and the top surface of the first metal structure 11 is exposed. In order to prevent the second stop layer 4 from being etched through, thereby exposing and damaging the underlying interlayer dielectric layer 3, the thickness of the second stop layer 4 is greater than that of the first stop layer 2; the thickness of the second stop layer 4 is 200 to 250% of the thickness of the first stop layer 2.
In another embodiment, the step of forming the diffusion barrier layer 5 on the sidewall of the trench includes: first, the first stop layer 2 under the trench B in fig. 2g is opened to form a first opening in the first stop layer 2, the first opening and the trench B together serve as a trench for forming a diffusion barrier layer 5 to expose the first metal structure 11 under the first stop layer 2, forming the structure shown in fig. 5 a; next, as shown in fig. 5b, a diffusion barrier material 50 is formed on the inner wall of the trench shown in fig. 5 a; thirdly, as shown in fig. 5c, filling a second sacrificial layer 72 into the trench formed with the diffusion barrier material 50, wherein the top surface of the second sacrificial layer 72 is higher than the top surface of the diffusion barrier material 50; from now on, as shown in fig. 5c, a patterned first photoresist layer 93 is formed on the second sacrificial layer 72, the patterned first photoresist layer 93 has at least one second opening, and the second opening is used as a window for subsequently etching the diffusion barrier layer material 50 at the bottom of the trench; then, as shown in fig. 5d, the second sacrificial layer 72 and the diffusion barrier layer material 50 are sequentially etched down by using the patterned photoresist layer as a mask, exposing the top surface of the first metal structure 11; finally, as shown in fig. 5f, the remaining patterned photoresist layer and the remaining second sacrificial layer 72 are removed. Since the oxygen plasma is typically used to remove the remaining patterned photoresist layer and the remaining sacrificial layer 72, the top surface of the first metal structure 11 exposed at the bottom of the trench is oxidized and remains, and thus, the exposed top surface of the first metal structure 11 and the exposed top surface of the oxide layer need to be removed before forming the second metal structure 6. For example, Ar plasma bombardment may be used to remove the residue and the oxide layer on the top surface of the first metal structure 11, but other suitable plasmas may be used for the treatment, and not limited thereto, and H is introduced at the same time2The top surface of the first metal structure 11 is prevented from being oxidized.
In another embodiment, the step of forming the diffusion barrier layer 5 on the sidewall of the trench includes: first, the part of the first stop layer 2 under the trench a in fig. 2b is opened to form a first opening in the first stop layer 2, the first opening and the trench a together act as a trench for forming the diffusion barrier layer 5 to expose the first metal structure 11 under the first stop layer 2, forming the structure shown in fig. 6 a; next, as shown in fig. 6b, a diffusion barrier material 50 is formed on the inner wall of the trench shown in fig. 6 a; thirdly, as shown in fig. 6b, filling a second sacrificial layer 72 into the trench formed with the diffusion barrier material 50, wherein the top surface of the second sacrificial layer 72 is higher than the top surface of the diffusion barrier material 50; from now on, as shown in fig. 6b, a patterned first photoresist layer 93 is formed on the second sacrificial layer 72, the patterned first photoresist layer 93 has at least one second opening, and the second opening is used as a window for subsequently etching the diffusion barrier material 50 at the bottom of the trench; then, as shown in fig. 6d, the second sacrificial layer 72 and the diffusion barrier layer material 50 are sequentially etched down by using the patterned photoresist layer as a mask, exposing the top surface of the first metal structure 11; finally, as shown in fig. 6f, the remaining patterned photoresist layer and the remaining second sacrificial layer 72 are removed. Since the oxygen plasma is typically used to remove the remaining patterned photoresist layer and the remaining sacrificial layer 72, the top surface of the first metal structure 11 exposed at the bottom of the trench is oxidized and remains, and thus, the exposed top surface of the first metal structure 11 and the exposed top surface of the oxide layer need to be removed before forming the second metal structure 6. For example, Ar plasma bombardment may be used to remove the residue and the oxide layer on the top surface of the first metal structure 11, but other suitable plasmas may be used for the treatment, and not limited thereto, and H is introduced at the same time2The top surface of the first metal structure 11 is prevented from being oxidized.
It should be noted that, as shown in fig. 6c, in order to effectively reduce the problems of line deformation and increased surface roughness of the patterned photoresist layer caused by light reflection and standing wave in the photolithography process, which affect the accurate pattern transfer, a second anti-reflection layer 82 may be formed between the second sacrificial layer 72 and the first photoresist layer 93.
In the first embodiment, the first stop layer 2 needs to be etched first, which may cause damage and deformation of the interlayer dielectric layer 3 exposed by the trench during etching of the first stop layer 2, thereby affecting the filling of the subsequent second metal structure, and further affecting the electrical performance stability and reliability of the finally formed device.
To this end, the present invention discloses another embodiment comprising the steps of: firstly, as shown in fig. 2B/2g, the first trench a/trench B is used as a trench for forming the diffusion barrier layer 5, and a diffusion barrier layer material 50 is formed on the inner wall of the trench a/trench B; secondly, removing the diffusion barrier layer material 50 at the bottom of the trench a/trench B to form the diffusion barrier layer 5 on the sidewall of the trench a/trench B and expose the first stop layer 2; finally, the exposed portion of the first stop layer 2 is removed to form a first opening in the first stop layer 2, where the first opening exposes the top surface of the first metal structure 11. With this embodiment, damage and deformation of the interlayer dielectric layer 3 at the time of opening the first stop layer 2 can be avoided by the protection of the diffusion barrier layer.
In one embodiment, the step of forming the diffusion barrier layer 5 on the trench sidewall includes: first, as shown in fig. 7a, a diffusion barrier material 50 is formed on the inner wall of the trench a in fig. 2 b; next, as shown in fig. 7b, after forming a diffusion barrier material 50 on the inner wall of the trench a, the diffusion barrier material 50 and the first stop layer 2 at the bottom of the trench a are sequentially etched downward using the second stop layer 4 and the diffusion barrier material 50 on the surface thereof as masks, so as to form the first opening in the first stop layer 2, wherein the first opening exposes the top surface of the first metal structure 11. In order to prevent the second stop layer 4 from being etched through, thereby exposing and damaging the underlying interlayer dielectric layer 3, the thickness of the second stop layer 4 is greater than that of the first stop layer 2; the thickness of the second stop layer 4 is 200 to 250% of the thickness of the first stop layer 2.
In another embodiment, the step of forming the diffusion barrier layer 5 on the trench sidewall includes: first, as shown in fig. 8a, a diffusion barrier material 50 is formed on the inner wall of the trench a in fig. 2 b; next, as shown in fig. 8b, filling a second sacrificial layer 72 into the trench a having the diffusion barrier material 50 formed on the inner wall thereof, wherein the top surface of the second sacrificial layer 72 is higher than the top surface of the diffusion barrier material 50; thirdly, as shown in fig. 8b, a patterned first photoresist layer 93 is formed on the second sacrificial layer 72, the patterned first photoresist layer 93 has at least one second opening, and the second opening is used as a window for subsequently etching the diffusion barrier material 50 at the bottom of the trench a; from the next time, as shown in fig. 8c, the second sacrificial layer 72 and the diffusion barrier layer 50 are sequentially etched down by using the patterned photoresist layer as a mask until the first stop layer 2 is exposed; next, as shown in fig. 8d, removing the remaining patterned photoresist layer and the remaining second sacrificial layer 72, exposing the diffusion barrier material 50 on the second stop layer 4; finally, as shown in fig. 8e, etching the first stop layer 2 downward using the second stop layer 4 and the diffusion barrier layer material 50 on the surface thereof as a mask to form the first opening in the first stop layer 2, wherein the first opening exposes the top surface of the first metal structure 11, and in order to prevent the second stop layer 4 from being etched through to expose and damage the underlying interlayer dielectric layer 3, the thickness of the second stop layer 4 is greater than that of the first stop layer 2; the thickness of the second stop layer 4 is 200 to 250% of the thickness of the first stop layer 2.
In another embodiment, the step of forming the diffusion barrier layer 5 on the trench sidewall includes: first, as shown in fig. 9a, a diffusion barrier material 50 is formed on the inner wall of the trench B of the structure shown in fig. 2 g; next, as shown in fig. 9B, a second sacrificial layer 72 is filled in the trench B having the diffusion barrier material 50 formed on the inner wall thereof, and the second sacrificial layerThe top surface of the second sacrificial layer 72 is higher than the top surface height of the diffusion barrier material 50; thirdly, as shown in fig. 9B, a patterned first photoresist layer 93 is formed on the second sacrificial layer 72, the patterned first photoresist layer 93 has at least one second opening, and the second opening is used as a window for subsequently etching the diffusion barrier material 50 at the bottom of the trench B; then, as shown in fig. 9c and 9d, the second sacrificial layer 72, the diffusion barrier layer 50 and the first stop layer 2 are sequentially etched down by using the patterned first photoresist layer 93 as a mask, so as to form the first opening in the first stop layer 2, wherein the first opening exposes the top surface of the first metal structure 11; finally, as shown in fig. 9e, the remaining patterned first photoresist layer 93 and the remaining second sacrificial layer 72 are removed. Since the oxygen plasma is typically used to remove the remaining patterned first photoresist layer 93 and the remaining sacrificial layer 72, the exposed top surface of the first metal structure 11 at the bottom of the first opening is oxidized and remains, and thus the exposed top surface of the first metal structure 11 and the exposed oxide layer need to be removed before forming the second metal structure 6. For example, Ar plasma bombardment may be used to remove the residue and the oxide layer on the top surface of the first metal structure 11, but other suitable plasmas may be used for the treatment, and not limited thereto, and H is introduced at the same time2The top surface of the first metal structure 11 is prevented from being oxidized.
It should be noted that in order to effectively reduce the problems of line deformation and increased surface roughness of the patterned photoresist layer caused by light reflection and standing wave in the photolithography process, which affect the pattern transfer, a second anti-reflection layer 82 may be formed between the second sacrificial layer 72 and the second photoresist layer 92.
It should be noted that the method for forming the diffusion barrier layer 5 on the inner wall of the trench may use PVD, CVD, ALD or other suitable processes, but is not limited thereto.
It should be noted that the method for etching the diffusion barrier material 50 includes using a conventional dry etching process or an atomic layer etching process, and other processes such as laser thinning and the like can also be used for this purpose, which is not limited to this.
It should be noted that, since the bottom of the diffusion barrier material 50 can be removed, the barrier material is selected only in consideration of its ability to block the diffusion of the second metal material (e.g., copper), and not in consideration of its conductive properties. Therefore, the diffusion barrier material 50 can be selected from both the conductive diffusion barrier material 50 and the insulating diffusion barrier material 50 with better ability to block the diffusion of the second metal material (e.g., copper); wherein the conductive diffusion barrier layer material 50 comprises one of titanium nitride, tungsten nitride, tantalum nitride, and ruthenium; the insulating diffusion barrier material 50 comprises one of silicon nitride and silicon oxynitride.
It should be noted that, by using the method of the present invention to remove the diffusion barrier layer 5 at the bottom, it can be avoided that when the diffusion barrier layer 5 at the bottom is removed by ion thinning process, the electrical stability and reliability of the device are affected by the local defects of the sidewall of the diffusion barrier layer 5 and the interlayer dielectric layer 3 due to the poor selectivity of the material caused by high-energy Ar bombardment. The ion thinning process is used to thin and remove the common defects of the diffusion barrier layer 5 at the bottom as shown in fig. 10-12, for example, as shown in fig. 10-11, a defect portion 51 is generated at the sidewall and step of the diffusion barrier layer 5, which causes diffusion of metal (e.g., Cu), or as shown in fig. 12, a deformation portion 31 is generated at the interlayer dielectric layer 3, which affects the filling of the subsequent second metal structure 6, thereby affecting the electrical stability and reliability of the device.
Step S50 is executed to form a second metal structure 6 in the trench having the diffusion barrier layer 5 formed on the sidewall, where the second metal structure 6 is directly bonded to the first metal structure 11 to realize an electrical connection, and the second metal structure 6 may include an interconnection wire or a conductive plug.
The step of forming the second metal structure 6 in the trench (trench a/trench B and first opening) having the diffusion barrier layer 5 formed on the sidewall thereof in step S40 includes: filling a second metal material in the trench (trench a/trench B and first opening) in which the diffusion barrier layer 5 is formed; the structure filled with the second metal material is planarized to form the second metal structure 6 in the trench (trench a/trench B and first opening) where the diffusion barrier layer 5 is formed, resulting in one of the structures shown in fig. 4d, 5f, 6f, 7c, 8f and 9 f.
The step of filling the trench (trench a/trench B and first opening) having the diffusion barrier layer 5 formed on the sidewall thereof in step S40 with a second metal material further includes: forming a seed layer 61 on an inner surface of the trench (trench a/trench B and first opening) in which the diffusion barrier layer 5 is formed; filling the second metal material in the trench (trench a/trench B and first opening) in which the seed layer 61 is formed; and planarizing the structure filled with the second metal material to form the second metal structure 6 in the trench in which the diffusion barrier layer 5 is formed, wherein the second metal structure 6 includes a main body portion 62 and a seed layer 61, and the seed layer 61 is coated and disposed on an outer surface of the main body portion 62, which does not include an upper surface, so as to form one of the structures shown in fig. 4d, fig. 5f, fig. 6f, fig. 7c, fig. 8f and fig. 9 f.
The material of the second metal structure 6 may include, but is not limited to, a metal such as Cu or Al.
It should be noted that the semiconductor structure manufacturing method of the present invention is also suitable for performing repeatedly many times to form three or more layers of metal interconnection structures.
The semiconductor structure manufacturing method of the invention can be used for reducing the contact resistance of copper interconnection aiming at the back-stage copper interconnection process of the dynamic random access memory.
The preparation method of the semiconductor structure is applied to a single damascene process and a dual damascene process.
As shown in fig. 4d, 5f, 6f, 7c, 8f or 9f, the present invention also provides a semiconductor structure prepared by the above semiconductor structure preparation method, comprising: a substrate 1, wherein at least one first metal structure 11 is embedded on the surface of the substrate 1; an interlayer dielectric layer 3 formed on the substrate 1, wherein at least one groove is formed in the interlayer dielectric layer 3, and the groove exposes the top surface of the first metal structure 11; a diffusion barrier layer 5 formed on the side wall of the trench; and a second metal structure 6 filled in the trench formed with the diffusion barrier layer 5, wherein the second metal structure 6 is directly bonded with the first metal structure 11 to realize electrical connection. The second metal structure 6 comprises a main body part 62 and a seed layer 61, wherein the seed layer 61 is coated and arranged on the outer surface of the main body part 62, which does not comprise the upper surface.
As shown in fig. 4d, 5f or 6f, the semiconductor structure further includes a first stop layer 2 located between the substrate 1 and the interlayer dielectric layer 3; the second stop layer 4 is positioned above the interlayer dielectric layer 3; the trench is formed in the second stop layer 4, the interlayer dielectric layer 3, and the first stop layer 2, and exposes the top surface of the first metal structure 11.
The semiconductor structure of fig. 7c, 8f or 9f further comprises a first stop layer 2 located between the substrate 1 and the interlayer dielectric layer 3, wherein the first stop layer 2 has at least one first opening; the second stop layer 4 is positioned above the interlayer dielectric layer 3; the groove is formed in the second stop layer 4 and the interlayer dielectric layer 3, and the groove exposes the first opening and a part of the first stop layer 2 located at the periphery of the first opening; the bottom of the diffusion barrier layer 5 is jointed with the surface of the first stop layer 2 exposed by the groove; the second metal structure 6 is filled in the trench formed with the diffusion barrier layer 5 and in the first opening, and the second metal structure 6 is directly bonded to the first metal structure 11 through the first opening to realize electrical connection. The top surface of the second stop layer 4, the top surface of the diffusion barrier layer 5 and the top surface of the first metal structure 11 are formed on the same polishing plane.
As shown in fig. 3, the substrate 1 also includes a third stop layer 12 and a bottom dielectric layer 13 on the third stop layer 12; at least one of the first metal structures 11 is embedded in the bottom dielectric layer 13 and the third stop layer 12.
It should be noted that, since the bottom of the diffusion barrier material 50 can be removed, the barrier material is selected only in consideration of its ability to block the diffusion of the second metal material (e.g., copper), and not in consideration of its conductive properties. Therefore, the diffusion barrier material 50 can be selected from both the conductive diffusion barrier material 50 and the insulating diffusion barrier material 50 with better ability to block the diffusion of the second metal material (e.g., copper); wherein the conductive diffusion barrier layer material 50 comprises one of titanium nitride, tungsten nitride, tantalum nitride, and ruthenium; the insulating diffusion barrier material 50 comprises one of silicon nitride and silicon oxynitride.
The idea of the present invention will be further described in the following with specific embodiments, it should be noted that in embodiments 1-7, the substrate 1 has been described by using the structure shown in fig. 2 as an example, and of course, the substrate 1 may also use the structure shown in fig. 3 as described above.
Example 1
As shown in fig. 2a-2b, and 4a-4d, this embodiment provides a method for fabricating a semiconductor structure, which specifically includes the following steps.
Firstly, as shown in fig. 2a, providing a substrate 1, where the substrate 1 includes a bottom dielectric layer 13 and a first metal structure 11, the first metal structure 11 is embedded in the bottom dielectric layer 13, and a top surface of the first metal structure 11 and a top surface of the bottom dielectric layer 13 are on the same plane; forming a first stop layer 2, an interlayer dielectric layer 3, a second stop layer 4 and a third photoresist layer 91 on the substrate 1 from bottom to top in sequence; illustratively, the thickness of the first stop layer 2 is 40-70nm, the thickness of the interlayer dielectric layer 3 is 250-300 nm, and the thickness of the second stop layer 4 is 200% -250% of the thickness of the first stop layer 2, so as to prevent the second stop layer 4 from being etched through when the subsequent second stop layer 4 is used as a mask to remove the first stop layer 2 and the bottom of the diffusion barrier layer 5, thereby exposing and damaging the underlying interlayer dielectric layer 3.
Next, as shown in fig. 2b, the second stop layer 4 and the interlayer dielectric layer 3 are sequentially etched downward by using a photolithography process, and the etching is stopped on the surface of the first stop layer 2, so as to form at least one trench a in the second stop layer 4 and the interlayer dielectric layer 3.
Next, as shown in fig. 4a, the first stop layer 2 is etched using the etched second stop layer 4 as a mask, so as to form a via (first opening) in the first stop layer 2, exposing a top surface of the first metal structure 11, where the via and the trench a are used as a trench for forming a diffusion barrier layer 5.
From the next, as shown in FIG. 4b, a layer of diffusion barrier material 50 is formed in the inner wall of the trench by PVD, CVD or ALD process, the diffusion barrier material 50 being selected from Si3N4WN, TiN, Ta, TaN, Ru, for example Ta.
Next, as shown in fig. 4c, the diffusion barrier layer 5 at the bottom of the trench (trench a and first opening) is removed by using a conventional dry etching or atomic layer etching ALE process, and the diffusion barrier layer 5 on the sidewall of the trench (trench a and first opening) is remained.
As an example, when the barrier layer is Ta, for example, the dimensional accuracy is precisely controlled by a method of atomic layer etching ALE. The atomic layer etching process for removing the bottom of the diffusion barrier layer 5 comprises the following steps: placing the structure formed with the diffusion barrier material 50 in an atomic layer etching chamber; introducing Cl into the atomic layer etching chamber2The surface of the diffusion barrier material 50 adsorbs etching gas molecules Cl2，Cl2Reacting with the diffusion barrier material 50 to produce a compound; excess Cl is pumped off by means of a vacuum pump2(ii) a Irradiating Ar atomic beams into the atomic layer etching chamber, and decomposing and adsorbing a compound generated by reaction on the surface of the diffusion barrier layer material 50 through the Ar atomic beams; the compound was evacuated using a vacuum pump. The chamber temperature is 50 deg.C to 150 deg.C, the chamber pressure is 0.3mtorr to 0.5mtorr, and the irradiation dose of Ar atom beam is 7 × 1015atom/cm2To 8X 1015atom/cm2. The above process is repeated until the diffusion barrier material 50 at the bottom of the trench is completely removed, which is significantExposing the top surface of the first metal structure 11.
Ta and Cl2The reaction equation of (a) is: ta + Cl2→TaClx+Cl*
Finally, as shown in fig. 4d, depositing a Cu seed layer 61 on the inner wall of the trench (trench a and first opening) where the diffusion barrier layer 5 is formed, electroplating Cu, and forming a Cu filled via structure (second metal structure 6), although electroless plating and other feasible processes may also be used to form the second metal structure 6, which is not limited thereto; the CMP process stops at layer 230 and the structure is formed as shown in figure 4d, with the sidewalls of the second metal structure 6 all in contact with the diffusion barrier 5.
Example 2
As shown in fig. 2a-2g, 5a-5f, the present embodiment provides a method for fabricating a semiconductor structure, which specifically includes the following steps.
First, a structure as shown in fig. 2g is provided, and the detailed forming process is described with reference to the foregoing description, which is not repeated herein, wherein the thickness of the interlayer dielectric layer 3 may be 500-550 nm.
Next, as shown in fig. 5a, the portion of the first stop layer 2 under the trench B in fig. 2g is opened to form a first opening in the first stop layer 2, which first opening together with the trench B serves as a trench for forming a diffusion barrier 5 to expose the first metal structure 11 under the first stop layer 2.
Thirdly, as shown in fig. 5B, a layer of diffusion barrier material 50 is formed on the inner wall of the trench (trench B and first opening) shown in fig. 5a by PVD, CVD or ALD process, wherein the diffusion barrier material 50 may be selected from Si3N4WN, TiN, Ta, TaN, Ru, for example Ta.
Then, as shown in fig. 5c, filling a second sacrificial layer 72 into the trench (trench B and the first opening) formed with the diffusion barrier material 50, wherein the top surface of the second sacrificial layer 72 is higher than the top surface of the diffusion barrier material 50; a patterned first photoresist layer 93 is formed on the second sacrificial layer 72, and the patterned first photoresist layer 93 has at least one second opening as a window for subsequently etching the diffusion barrier material 50 at the bottom of the trench (trench B and first opening).
Next, as shown in fig. 5d, the second sacrificial layer 72 and the diffusion barrier layer material 50 are sequentially etched down using the patterned photoresist layer as a mask, exposing the top surface of the first metal structure 11. As an example, the second anti-reflective layer 82 is etched first (the etching gas includes CF)4) The second sacrificial layer 72 is etched again (the etching gas includes CO), and the diffusion barrier material 50Ta is etched again; as an example, BCl may be used, for example, by etching the diffusion barrier material 50Ta using conventional RIE3/Cl2Etching gas by generating TaCl5Is pumped away and has a chemical formula of Ta + Cl2→TaCl5+ Cl. Note that the 50Ta etch of the diffusion barrier material can also be removed with ALE (Cl) in example 12/Ar)。
Then, as shown in fig. 5e, the remaining patterned photoresist layer and the remaining second sacrificial layer 72 are removed. Since the oxygen plasma is typically used to remove the remaining patterned photoresist layer and the remaining sacrificial layer 72, the top surface of the first metal structure 11 (e.g., Cu or Al) exposed at the bottom of the trench (trench B and first opening) is oxidized and remains, and thus, the exposed top surface of the first metal structure 11 and the exposed top surface of the oxide layer are removed before forming the second metal structure 6. For example, Ar plasma bombardment may be used to remove the residue and the oxide layer on the top surface of the first metal structure 11, but other suitable plasmas may be used for the treatment, and not limited thereto, and H is introduced at the same time2The top surface of the first metal structure 11 is prevented from being oxidized.
Finally, as shown in fig. 5f, forming a second metal structure 6 in the trench (trench B and the first opening) where the diffusion barrier layer 5 is formed, for example, depositing a Cu seed layer 61 on the inner wall of the trench where the diffusion barrier layer 5 is formed, electroplating Cu, and forming a Cu filled via structure, although electroless plating and other feasible processes may also be used to form the second metal structure 6, which is not limited thereto; the CMP process stops at layer 230 and the structure is formed as shown in figure 5f, with the sidewalls of the second metal structure 6 all in contact with the diffusion barrier 5.
Example 3
As shown in fig. 2a-2b, and 6a-6f, this embodiment provides a method for fabricating a semiconductor structure, which specifically includes the following steps.
First, a structure as shown in fig. 2b is provided, and please refer to the description in the foregoing for a detailed forming process, which is not described herein again.
Next, as shown in fig. 6a, the portion of the first stop layer 2 under the trench a in fig. 2b is opened to form a first opening in the first stop layer 2, which first opening together with the trench a serves as a trench for forming a diffusion barrier 5 to expose the first metal structure 11 under the first stop layer 2.
Thirdly, as shown in fig. 6b, a layer of diffusion barrier material 50 is formed on the inner wall of the trench (trench a and first opening) shown in fig. 6a by PVD, CVD or ALD process, wherein the diffusion barrier material 50 may be selected from Si3N4WN, TiN, Ta, TaN, Ru, for example Ta.
Then, as shown in fig. 6c, filling a second sacrificial layer 72 into the trench (trench a and the first opening) formed with the diffusion barrier material 50, wherein the top surface of the second sacrificial layer 72 is higher than the top surface of the diffusion barrier material 50; a patterned first photoresist layer 93 is formed on the second sacrificial layer 72, and the patterned first photoresist layer 93 has at least one second opening as a window for subsequently etching the diffusion barrier material 50 at the bottom of the trench (trench a and first opening).
Next, as shown in fig. 6d, the second sacrificial layer 72 and the diffusion barrier layer material 50 are sequentially etched down using the patterned photoresist layer as a mask to expose the top surface of the first metal structure 11, for example, a second anti-reflection layer is first etched (the etching gas includes CF)4) Then amorphous carbon second sacrificial layer 72 is etched (etching gas including CO), then diffusion barrier material 50Ta is etched;as an example, BCl may be used, for example, by etching the diffusion barrier material 50Ta using conventional RIE3/Cl2Etching gas by generating TaCl5Is pumped away and has a chemical formula of Ta + Cl2→TaCl5+ Cl. Note that the 50Ta etch of the diffusion barrier material can also be removed with ALE (Cl) in example 12/Ar)。
Then, as shown in fig. 6e, the remaining patterned photoresist layer and the remaining second sacrificial layer 72 are removed. Since the oxygen plasma is typically used to remove the remaining patterned photoresist layer and the remaining sacrificial layer 72, the top surface of the first metal structure 11 (e.g., Cu or Al) exposed at the bottom of the trench (trench a and the first opening) is oxidized and remains, and thus, the exposed top surface of the first metal structure 11 and the exposed top surface of the oxide layer need to be removed before forming the second metal structure 6. For example, Ar plasma bombardment may be used to remove the residue and the oxide layer on the top surface of the first metal structure 11, but other suitable plasmas may be used for the treatment, and not limited thereto, and H is introduced at the same time2The top surface of the first metal structure 11 is prevented from being oxidized.
Finally, as shown in fig. 6f, forming a second metal structure 6 in the trench (trench a and first opening) where the diffusion barrier layer 5 is formed, for example, depositing a Cu seed layer 61 on the inner wall of the trench (trench a and first opening) where the diffusion barrier layer 5 is formed, electroplating Cu, and forming a Cu filled via structure (second metal structure 6), although electroless plating and other feasible processes may also be used to form the second metal structure 6, which is not limited thereto; the CMP process stops at layer 230 and the structure is formed as shown in figure 6f, with the sidewalls of the second metal structure 6 all in contact with the diffusion barrier 5.
Example 4
As shown in fig. 2a-2b and 7a-7c, this embodiment provides a method for fabricating a semiconductor structure, which specifically includes the following steps.
First, a structure as shown in fig. 2b is provided, and please refer to the description in the foregoing for a detailed forming process, which is not described herein again; the thickness of the second stop layer 4 is 200% -250% of the thickness of the first stop layer 2, which is to prevent the second stop layer 4 from being etched through when the subsequent second stop layer 4 is used as a mask to remove the bottom of the first stop layer 2 and the diffusion barrier layer 5, thereby exposing and damaging the underlying interlayer dielectric layer 3.
Next, as shown in fig. 7a, a layer of diffusion barrier material 50 is formed in the inner wall of the trench a as shown in fig. 2b, and the diffusion barrier material 50 may be selected from Si3N4WN, TiN, Ta, TaN, Ru, for example Ta.
Then, as shown in fig. 7b, the etched second stop layer 4 and the diffusion barrier layer material 50 on the surface thereof are used as masks to sequentially etch the diffusion barrier layer material 50 at the bottom of the trench a and the first stop layer 2 downward, so as to form the first opening in the first stop layer 2, wherein the first opening exposes the top surface of the first metal structure 11.
As an example, Si may be used for the first stop layer 23N4The diffusion barrier layer 5 may be Ta, and the diffusion barrier layer material 50 and the first stop layer 2 at the bottom of the trench a are removed by one-time etching by using conventional dry etching or ALE, and only the diffusion barrier layer material 50 on the sidewall of the trench a is retained, and at least one first opening is formed in the first stop layer 2. For example, CF can be used4And CH2F2Etching the diffusion barrier material 50 and the first stop layer 2 by adjusting CH2F2The etching selectivity is adjusted. F + Ta → TaF5，F*+Si3N4→SiF4。
Finally, as shown in fig. 7c, forming a second metal structure 6 in the trench (trench a and first opening) where the diffusion barrier layer 5 is formed, for example, depositing a Cu seed layer 61 on the inner wall of the trench (trench a and first opening) where the diffusion barrier layer 5 is formed, electroplating Cu, and forming a Cu filled via structure (second metal structure 6), although electroless plating and other feasible processes may also be used to form the second metal structure 6, which is not limited thereto; the CMP process stops at layer 230 to form the structure shown in fig. 7c, and the portion of the sidewall of the second metal structure 6 located on the first stop layer 2 is directly in contact with the first stop layer 2, and the upper portion of the first stop layer 2 is in contact with the diffusion barrier layer 5.
Example 5
As shown in fig. 2a-2b, 8a-8f, this embodiment provides a method for fabricating a semiconductor structure, which specifically includes the following steps.
First, a structure as shown in fig. 2b is provided, and please refer to the description in the foregoing for a detailed forming process, which is not described herein again. Wherein the thickness of the first stop layer 2 is between 40 and 70 nm; the thickness of the interlayer dielectric layer 3 is between 250nm and 300 nm; the thickness of the second stop layer 4 is 200% -250% of the thickness of the first stop layer 2, which is to prevent the second stop layer 4 from being etched through when the subsequent second stop layer 4 is used as a mask to remove the bottom of the first stop layer 2 and the diffusion barrier layer 5, thereby exposing and damaging the underlying interlayer dielectric layer 3.
As shown in fig. 8a, a diffusion barrier material 50 is formed on the inner wall of the trench a of the structure shown in fig. 2 b; the diffusion barrier material 50 may also be selected from Si3N4WN, TiN, Ta, TaN, Ru, for example Ta.
Next, as shown in fig. 8b, filling a second sacrificial layer 72 into the trench a having the diffusion barrier material 50 formed on the inner wall thereof, wherein the top surface of the second sacrificial layer 72 is higher than the top surface of the diffusion barrier material 50; a patterned first photoresist layer 93 is formed on the second sacrificial layer 72, and the patterned first photoresist layer 93 has at least one second opening as a window for subsequently etching the diffusion barrier material 50 located at the bottom of the trench a.
Next, as shown in fig. 8c, the second sacrificial layer 72 and the diffusion barrier layer 50 are sequentially etched down by using the patterned photoresist layer as a mask until the first stop layer 2 is exposed. As an example, the second anti-reflection (etching gas including CF4), the second sacrificial layer 72 (etching gas including CO), and the diffusion barrier layer are sequentially etched50Ta of material; as an example, BCl may be used, for example, by etching the diffusion barrier material 50Ta using conventional RIE3/Cl2Etching gas by generating TaCl5Is pumped away and has a chemical formula of Ta + Cl2→TaCl5+ Cl. Note that the 50Ta etch of the diffusion barrier material can also be removed with ALE (Cl) in example 12/Ar)。
From this point, as shown in fig. 8d, the remaining patterned photoresist layer and the remaining second sacrificial layer 72 are removed, exposing the diffusion barrier material 50 on the second stop layer 4. .
Next, as shown in fig. 8e, the first stop layer 2 is etched down by using the second stop layer 4 and the diffusion barrier material 50 on the surface thereof as a mask, so as to form the first opening in the first stop layer 2, wherein the first opening exposes the top surface of the first metal structure 11. As an example, Si may be used for the first stop layer 23N4Using CF4And CH2F2Etching the diffusion barrier material 50 and the first stop layer 2 by adjusting CH2F2Amount of (2), adjusting Si3N4Etch selectivity to Ta, only for Si3N4The time is ongoing and Ta is not etched or the etch rate is low.
Finally, as shown in fig. 8f, forming a second metal structure 6 in the trench (trench a and first opening) where the diffusion barrier layer 5 is formed, for example, depositing a Cu seed layer 61 on the inner wall of the trench (trench a and first opening) where the diffusion barrier layer 5 is formed, electroplating Cu, and forming a Cu filled via structure (second metal structure 6), although electroless plating and other feasible processes may be used to form the second metal structure 6, which is not limited thereto; the CMP process stops at layer 230 to form the structure shown in fig. 7c, and the portion of the sidewall of the second metal structure 6 located on the first stop layer 2 is directly in contact with the first stop layer 2, and the upper portion of the first stop layer 2 is in contact with the diffusion barrier layer 5.
Example 6
As shown in fig. 2a-2g, 9a-8f, this embodiment provides a method for fabricating a semiconductor structure, which specifically includes the following steps.
First, a structure as shown in fig. 2g is provided, and the detailed forming process is described with reference to the foregoing description, which is not repeated herein, wherein the thickness of the interlayer dielectric layer 3 may be 500-550 nm.
Next, as shown in fig. 9a, a diffusion barrier material 50 is formed on the inner wall of the trench B of the structure shown in fig. 2 g; the diffusion barrier material 50 may also be selected from Si3N4WN, TiN, Ta, TaN, Ru, for example Ta.
Thirdly, as shown in fig. 9B, filling a second sacrificial layer 72 into the trench B having the diffusion barrier material 50 formed on the inner wall thereof, wherein the top surface of the second sacrificial layer 72 is higher than the top surface of the diffusion barrier material 50; a patterned first photoresist layer 93 is formed on the second sacrificial layer 72, and the patterned first photoresist layer 93 has at least one second opening as a window for subsequently etching the diffusion barrier material 50 located at the bottom of the trench B.
Next, as shown in fig. 9c and 9d, the second sacrificial layer 72, the diffusion barrier material 50 and the first stop layer 2 are sequentially etched down by using the patterned first photoresist layer 93 as a mask, so as to form the first opening in the first stop layer 2, wherein the top surface of the first metal structure 11 is exposed by the first opening.
As an example, Ta is used as the diffusion barrier layer 5, and Si is used as the first stop layer 23N4When, CF can be used4And CH2F2The diffusion barrier material 50 and the first stop layer 2 are etched in one step by adjusting CH2F2The etching selectivity is adjusted. F + Ta → TaF5，F*+Si3N4→SiF4。
Finally, as shown in fig. 9e, the remaining patterned first photoresist layer 93 and the remaining second sacrificial layer 72 are removed.
Since the remaining patterned first photoresist layer 93 and the remaining second sacrificial layer are removed72, the oxygen plasma is typically used, which causes the top surface of the first metal structure 11 exposed at the bottom of the first opening to be oxidized and the residue to remain, so that the residue and the oxide layer on the top surface of the first metal structure 11 exposed need to be removed before forming the second metal structure 6. For example, Ar plasma bombardment may be used to remove the residue and the oxide layer on the top surface of the first metal structure 11, but other suitable plasmas may be used for the treatment, and not limited thereto, and H is introduced at the same time2The top surface of the first metal structure 11 is prevented from being oxidized, the process parameters are as follows, the pressure of the cavity is 20-100 mTorr, the radio frequency bias voltage is 10-100W, and the etching gas can be H2/Ar。
Examples 7 to 12
Examples 7-12 correspond to examples 1-6, respectively, and the fabrication flow process is substantially identical, except that instead of using a conductive diffusion barrier 5 with an insulating diffusion barrier 5,
by way of example, the material of the diffusion barrier layer 5 may be silicon nitride or silicon oxynitride, but other suitable insulating materials may also be used without limitation.
In summary, the present invention provides a semiconductor structure, a method for fabricating a semiconductor structure and a use thereof, the method comprising providing a substrate having at least one first metal structure embedded therein; the top surface of the first metal structure and the top surface of the substrate are positioned on the same plane; forming an interlayer dielectric layer on the substrate; forming at least one groove in the interlayer dielectric layer, wherein the groove exposes the top surface of the first metal structure; forming a diffusion barrier layer on the side wall of the groove; and forming a second metal structure in the groove formed with the diffusion barrier layer, wherein the second metal structure is directly jointed with the first metal structure to realize electric connection. By utilizing the invention, the diffusion barrier layer at the contact part of the metal interconnection structure is removed by etching, so that the interconnection contact resistance between the upper and lower layers of metal structures can be reduced, the RC delay is reduced, the speed of a semiconductor device is improved, and the reliability of the device is ensured; by using the method, the diffusion barrier layer material at the bottom of the Damascus structure is removed, and the interlayer dielectric layer is protected, so that the filling quality of the through hole is improved, and the electrical property stability and the device reliability of the semiconductor device are improved; by the method, the diffusion barrier layer between the first metal structure and the second metal structure is removed, and the first metal structure and the second metal structure can be directly jointed to realize electric connection, so that the diffusion barrier layer material is selected only by considering the diffusion resistance of the diffusion barrier layer material to the second metal material (such as Cu) and not considering the conductive characteristic of the diffusion barrier layer material, and therefore an insulating material with better diffusion resistance to the second metal material (such as Cu) can be selected for the diffusion barrier layer, and the electrical property stability and the device reliability of the semiconductor device are further improved. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value. The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112018077A (en) * | 2020-07-29 | 2020-12-01 | 复旦大学 | A copper interconnect structure and its manufacturing method |
| CN113539941A (en) * | 2020-04-13 | 2021-10-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113782486A (en) * | 2020-06-10 | 2021-12-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113921386A (en) * | 2020-07-10 | 2022-01-11 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN116759383A (en) * | 2023-08-17 | 2023-09-15 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI244160B (en) * | 2004-08-17 | 2005-11-21 | Taiwan Semiconductor Mfg | Method for manufacturing dual damascene structure with a trench formed first |
| CN101369535A (en) * | 2007-08-17 | 2009-02-18 | 中芯国际集成电路制造(上海)有限公司 | Method for improving defect of insulation dielectric layer and forming dual damascene structure |
| CN101692437A (en) * | 2009-10-15 | 2010-04-07 | 复旦大学 | Method for selectively depositing diffusion barrier for copper interconnection |
| CN208938962U (en) * | 2018-09-21 | 2019-06-04 | 长鑫存储技术有限公司 | Semiconductor structure |
-
2018
- 2018-09-21 CN CN201811117587.9A patent/CN110943070A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI244160B (en) * | 2004-08-17 | 2005-11-21 | Taiwan Semiconductor Mfg | Method for manufacturing dual damascene structure with a trench formed first |
| CN101369535A (en) * | 2007-08-17 | 2009-02-18 | 中芯国际集成电路制造(上海)有限公司 | Method for improving defect of insulation dielectric layer and forming dual damascene structure |
| CN101692437A (en) * | 2009-10-15 | 2010-04-07 | 复旦大学 | Method for selectively depositing diffusion barrier for copper interconnection |
| CN208938962U (en) * | 2018-09-21 | 2019-06-04 | 长鑫存储技术有限公司 | Semiconductor structure |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113539941A (en) * | 2020-04-13 | 2021-10-22 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113782486A (en) * | 2020-06-10 | 2021-12-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113782486B (en) * | 2020-06-10 | 2024-02-02 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| CN113921386A (en) * | 2020-07-10 | 2022-01-11 | 长鑫存储技术有限公司 | Semiconductor device and method for manufacturing the same |
| CN112018077A (en) * | 2020-07-29 | 2020-12-01 | 复旦大学 | A copper interconnect structure and its manufacturing method |
| CN116759383A (en) * | 2023-08-17 | 2023-09-15 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
| CN116759383B (en) * | 2023-08-17 | 2023-11-03 | 合肥晶合集成电路股份有限公司 | Semiconductor structure and preparation method thereof |
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