CN110911424B - Array substrate, preparation method thereof and display panel - Google Patents

Abstract

The present application discloses an array substrate, a preparation method thereof, and a display panel, which are used to prevent the semiconductor region of the active layer of the thin film transistor from being exposed to light, improve the working stability of the thin film transistor, avoid uneven display images, and improve the display effect. The array substrate provided by the present application includes: a base substrate, a light-shielding layer on the base substrate, a buffer layer on the light-shielding layer, an active layer on the buffer layer, and a light-shielding portion; the buffer layer has a groove; The active layer includes: a semiconductor region, a first conductive region and a second conductive region connected to the semiconductor region; the semiconductor region and the light shielding portion fill the groove; the shape of the orthographic projection of the light shielding portion on the substrate is annular, and the semiconductor region The side surface of the shading portion is completely surrounded by the shading portion, and the first conducting region and the second conducting region are located on the shading portion and the semiconductor region; the orthographic projection of the light shielding layer on the base substrate covers the orthographic projection of the semiconductor region on the base substrate.

Description

Array substrate and preparation method thereof, and display panel

technical field

The present application relates to the field of display technology, and in particular, to an array substrate, a preparation method thereof, and a display panel.

Background technique

At present, organic light-emitting diode (Organic Light-Emitting Diode, OLED) display products have the advantages of large screen brightness, wide color gamut, low power consumption, and large viewing angle, and have been vigorously developed. OLED display panels include thin film transistors (Thin Film Transistor, TFT), and TFTs in pixel circuits usually use oxide semiconductor materials as active layers, such as indium gallium zinc oxide (Indium Gallium Zinc Oxide, IGZO). The structure of the display panel in the prior art is shown in FIG. 1 . FIG. 1 only shows the base substrate 1 , the light shielding layer 2 , the buffer layer 3 , the semiconductor region 4 of the active layer, the gate insulating layer 5 and the gate 6 . As can be seen in FIG. 1 , the semiconductor region 4 of the active layer is easily affected by light irradiated from the side, resulting in poor TFT stability, easily leading to a phenomenon of start-up voltage drift, resulting in uneven display images.

To sum up, in the display panel of the prior art, the semiconductor region of the active layer of the thin film transistor is easily affected by light, and the phenomenon of start-up voltage drift is prone to occur, resulting in poor TFT stability, resulting in uneven display images and affecting display effects.

SUMMARY OF THE INVENTION

The embodiments of the present application provide an array substrate, a preparation method thereof, and a display panel, which are used to prevent the semiconductor region of the active layer of the thin film transistor from being exposed to light, improve the working stability of the thin film transistor, avoid uneven display images, and improve the display effect .

An array substrate provided by an embodiment of the present application includes: a base substrate, a light-shielding layer on the base substrate, and a buffer layer on the light-shielding layer, on the buffer layer The active layer, and the light shielding part; the buffer layer has a groove;

The active layer includes: a semiconductor region, a first conductive region and a second conductive region connected to the semiconductor region;

The semiconductor region and the light shielding portion fill the groove; the shape of the orthographic projection of the light shielding portion on the base substrate is a ring shape, the side surface of the semiconductor region is completely surrounded by the light shielding portion, and the first A conductive region and the second conductive region are located on the light shielding portion and the semiconductor region;

The orthographic projection of the light shielding layer on the base substrate covers the orthographic projection of the semiconductor region on the base substrate.

In the array substrate provided by the embodiments of the present application, since the light shielding portion is provided to surround the side surface of the semiconductor region of the active layer, and the light shielding portion shields the side surface of the semiconductor region to avoid the problem of threshold voltage drift caused by light irradiation from the side surface of the semiconductor region, it can be Improve the working stability of thin film transistors, avoid uneven display images, improve display effects, and improve user experience. Moreover, since the buffer layer has grooves, the semiconductor region is located in the grooves, that is, after the entire buffer layer is deposited, the buffer layer needs to be patterned, and then the active layer is formed, so as to avoid film formation due to the buffer layer deposition process. Short circuit between active layer and gate caused by layer lift or puncture to avoid bright and dark spots.

Optionally, the thickness of the light shielding portion is equal to the thickness of the semiconductor region.

Optionally, the groove is divided into a first area and a second area, the thickness of the first area is greater than the thickness of the second area, the first area exposes the light shielding layer, and the light shielding portion is filled with The first region, the semiconductor region fills the second region.

In the array substrate provided by the embodiments of the present application, the light shielding portion can not only shield the side surface of the semiconductor region, but also prevent light from being irradiated into the semiconductor region of the active layer from the side surface. It will be reflected to the semiconductor area through the shading layer, thereby further improving the working stability of the thin film transistor, avoiding uneven display images, improving the display effect, and improving the user experience.

Optionally, the light shielding layer is a conductor; the buffer layer further has a first via hole exposing the light shielding layer;

The array substrate further includes: a conductive connection pad disposed on the same layer as the active layer, an interlayer insulating layer on the active layer, and a source-drain electrode layer on the interlayer insulating layer;

the conductive connection pad is in contact with the light shielding layer at the first via hole;

The interlayer insulating layer has a second via hole through its thickness, and the source-drain electrode layer is electrically connected to the conductive connection pad through the second via hole and the first via hole.

In the array substrate provided by the embodiment of the present application, in the area of the first via hole, the conductive connection pad is in contact with the light shielding layer, and then in the etching process of the interlayer insulating layer, there is no need to worry about damaging the conductive connection pad, and the etching rate can be adjusted. The regulation is performed to avoid the occurrence of etching residues of the insulating layer, so as to avoid bad black spots caused by the inability of the source-drain electrode layer and the light shielding layer to overlap, avoid product scrap due to etching residues, and save costs.

Optionally, the buffer layer further has a third via hole exposing the base substrate;

The array substrate further includes: a gate insulating layer on the active layer, a gate on the gate insulating layer, and a buffer pad layer in contact with the base substrate at the third via hole , and a first capacitor electrode located on the buffer layer;

The buffer pad layer and the gate insulating layer are arranged in the same layer, and the first capacitor electrode and the gate are arranged in the same layer.

In the array substrate provided by the embodiment of the present application, the buffer pad layer and the first capacitor electrode are disposed in the via holes of the buffer layer, so that the subsequently formed interlayer insulating layer will not form steps on the first capacitor electrode, ensuring that the interlayer The flatness of the surface of the insulating layer, so that the source and drain electrode layers are formed on a flat surface, and there will be no failure to climb and disconnect.

An embodiment of the present application provides a method for preparing an array substrate, the method comprising:

forming a pattern of the light shielding layer on the base substrate;

forming a buffer layer on the light shielding layer;

forming grooves in the buffer layer;

A pattern of a light-shielding portion and a pattern of an active layer are formed, wherein the active layer includes a semiconductor region, a first conductive region and a second conductive region connected to the semiconductor region, the light-shielding portion and the The semiconductor region fills the groove, the shape of the orthographic projection of the light shielding portion on the base substrate is annular, the side surface of the semiconductor region is completely surrounded by the light shielding portion, the first conductive region and the A second conductive region is located over the light shielding portion and the semiconductor region.

In the method for fabricating an array substrate provided in this embodiment of the present application, a groove is formed in the buffer layer, then the light shielding layer and the semiconductor region of the active layer are filled in the groove, and the light shielding portion surrounds the side surface of the semiconductor region of the active layer, so that the light shielding portion can Blocking the side of the semiconductor region to avoid the problem of threshold voltage drift caused by light irradiation from the side of the semiconductor region can improve the working stability of the thin film transistor, avoid uneven display images, improve the display effect, and enhance the user experience. In addition, in the preparation method of the array substrate provided by the embodiment of the present application, the buffer layer needs to be patterned to form grooves before the active layer is formed, so as to avoid problems caused by film lifting or piercing during the deposition of the buffer layer. The source layer and the gate are shorted to avoid bright and dark spots.

Optionally, the forming a groove in the buffer layer specifically includes:

The buffer layer is patterned by a halftone mask process, and a part of the buffer layer is thinned to form grooves.

Optionally, the forming a groove in the buffer layer specifically includes:

The buffer layer is patterned by a halftone mask process, the entire buffer layer is removed in a first area to expose the light shielding layer, and the buffer layer is thinned in a second area, where the first area is The orthographic projection of the base substrate surrounds the orthographic projection of the second region on the base substrate;

The pattern of forming the light-shielding portion and the pattern of the active layer specifically includes:

forming a pattern of the light-shielding portion in the first region;

A pattern of the active layer is formed on the light shielding portion and the buffer layer in the second region, wherein the semiconductor region fills the groove in the second region.

Optionally, while the buffer layer forms the groove, the method further includes:

forming a first via hole exposing the light shielding layer;

The pattern for forming the active layer specifically includes:

depositing a semiconductor material, using a patterning process to form a pattern of the active layer, and forming a pattern of conductive connection pads in contact with the light shielding layer in the first via hole;

After forming the pattern of the active layer, the method further includes:

conducting a conductorization process on the active layer and the conductive connection pads, and forming the first conductorization region and the second conductorization region on the active layer;

an interlayer insulating layer formed over the active layer;

patterning the interlayer insulating layer, exposing the conductive link pads, and forming a second via hole penetrating the interlayer insulating layer;

A pattern of a source-drain electrode layer is formed on the interlayer insulating layer, and the source-drain electrode layer is electrically connected to the conductive connection pad through the second via hole and the first via hole.

In the preparation method of the array substrate provided in the embodiment of the present application, before the active layer is formed, a first via hole exposing the light shielding layer is formed in the buffer layer, and a conductive connection pad in contact with the light shielding layer is formed in the area of the first via hole, In this way, even if the conductive connection pads are etched, it will not affect the electrical connection between the source-drain electrode layer and the light shielding layer through the conductive connection pads. Therefore, in the subsequent etching process of the interlayer insulating layer, there is no need to worry about damaging the conductive connection pads. The etching rate can be adjusted to remove all the interlayer insulating layers above the conductive connection pads, so as to avoid the etching residue of the insulating layer, so as to avoid the bad black spots caused by the inability of the source and drain electrode layers and the light shielding layer to overlap, and avoid the etching Product scrap caused by corrosion residues can save costs.

Optionally, while the buffer layer forms the groove, the method further includes:

forming a third via hole exposing the base substrate;

After forming the pattern of the active layer, the method further includes:

A gate insulating layer material and a gate material are sequentially deposited on the active layer, and a patterning process is used to form a pattern of the gate insulating layer on the active layer and a pattern of the gate on the gate insulating layer and forming a pattern of a buffer pad layer in contact with the base substrate and a pattern of a first capacitor electrode located on the buffer pad layer in the third via hole.

In the method for fabricating an array substrate provided in the embodiment of the present application, a third via hole exposing the base substrate is formed in the buffer layer, and a buffer pad layer and a first capacitor electrode are subsequently formed in the third via hole, so that the subsequently formed interlayer insulating layer is No steps are formed on the first capacitor electrode, which ensures the surface flatness of the interlayer insulating layer. In this way, the source and drain electrode layers are formed on a flat surface, and there will be no failure to climb and disconnect.

A display panel provided by an embodiment of the present application includes the array substrate provided by an embodiment of the present application.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application more clearly, the following briefly introduces the drawings used in the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

1 is a schematic structural diagram of a display product provided by the prior art;

FIG. 2 is a schematic structural diagram of an array substrate according to an embodiment of the present application;

3 is a schematic diagram of a light shielding portion and a semiconductor region in an array substrate according to an embodiment of the present application;

FIG. 4 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

FIG. 5 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

FIG. 6 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

7 is a schematic structural diagram of an array substrate provided by the prior art;

FIG. 8 is a schematic structural diagram of another array substrate provided by an embodiment of the present application;

9 is a schematic structural diagram of an array substrate provided in the prior art;

FIG. 10 is a schematic diagram of a method for preparing an array substrate according to an embodiment of the present application;

FIG. 11 and FIG. 12 are schematic diagrams of another method for fabricating an array substrate according to an embodiment of the present application.

Detailed ways

An embodiment of the present application provides an array substrate. As shown in FIG. 2 , the array substrate includes a base substrate 1 , a light shielding layer 2 located on the base substrate 1 , and a light shielding layer 2 located on the light shielding layer 2 . The buffer layer 3, the active layer 8 located on the buffer layer 3, and the light shielding portion 11; the buffer layer 3 has a groove 12;

The active layer 8 includes: a semiconductor region 4, and a first conductive region 9 and a second conductive region 10 of the semiconductor region 4;

The semiconductor region 4 and the light shielding portion 11 fill the groove 12 ; as shown in FIG. 3 , the shape of the orthographic projection of the light shielding portion 11 on the base substrate 1 is annular, and the The side surface is completely surrounded by the light-shielding portion 11 , and the first conductive region 9 and the second conductive region 10 are located above the light-shielding portion 11 and the semiconductor region 4 ;

The orthographic projection of the light shielding layer 2 on the base substrate 1 covers the orthographic projection of the semiconductor region 4 on the base substrate 1 .

In the array substrate provided by the embodiments of the present application, since the light shielding portion is provided to surround the side surface of the semiconductor region of the active layer, and the light shielding portion shields the side surface of the semiconductor region to avoid the problem of threshold voltage drift caused by light irradiation from the side surface of the semiconductor region, it can be Improve the working stability of thin film transistors, avoid uneven display images, improve display effects, and improve user experience. Moreover, since the buffer layer has grooves, the semiconductor region is located in the grooves, that is, after the entire buffer layer is deposited, the buffer layer needs to be patterned, and then the active layer is formed, so as to avoid film formation due to the buffer layer deposition process. Short circuit between active layer and gate caused by layer lift or puncture to avoid bright and dark spots.

Optionally, as shown in FIG. 2 , the thickness of the light shielding portion 11 is equal to the thickness of the semiconductor region 4 .

Optionally, as shown in FIG. 4 , the groove is divided into a first area 13 and a second area 14 , the thickness of the first area 13 is greater than the thickness of the second area 14 , and the shading portion 11 is filled with The first region 13 and the semiconductor region 4 fill the second region 14 .

Optionally, as shown in FIG. 5 , the first region 13 exposes the light shielding layer 2 . That is, the light shielding portion is in contact with the light shielding layer. When the light shielding layer is a conductor, the material of the light shielding portion is an insulating material.

In the array substrate provided by the embodiments of the present application, since the light-shielding portion is in contact with the light-shielding layer, the light-shielding portion can not only shield the side of the semiconductor region, but also prevent light from irradiating into the semiconductor region of the active layer from the side, and the light incident from the side is blocked by the light-shielding portion. It will be reflected to the semiconductor area through the shading layer, thereby further improving the working stability of the thin film transistor, avoiding uneven display images, improving the display effect, and improving the user experience.

Optionally, as shown in FIG. 6 , the light shielding layer 2 is a conductor, and the buffer layer 3 further has a first via hole 17 exposing the light shielding layer 2 ;

The array substrate further includes: a conductive connection pad 7 disposed on the same layer as the active layer 8 , an interlayer insulating layer 15 located on the active layer 8 , and an interlayer insulating layer 15 located on the interlayer insulating layer 15 . source-drain electrode layer 16;

The conductive connection pad 7 is in contact with the light shielding layer 2 at the first via hole 17;

The interlayer insulating layer 15 has a second via hole 18 through its thickness, and the source-drain electrode layer 16 is electrically connected to the conductive connection pad 7 through the second via hole 18 and the first via hole 17 .

It should be noted that, in the prior art, after the interlayer insulating layer is formed, the interlayer insulating layer and the buffer layer need to be etched to form via holes exposing the light shielding layer. However, due to the thick interlayer insulating layer, In the patterning process, if it is necessary to ensure that the light-shielding layer will not be damaged, it is difficult to control the etching rate, and the etching residue of the insulating layer is prone to occur, that is, as shown in FIG. , the etching residue results in that there are still some materials of the buffer layer 3 on the light-shielding layer 2, and the source-drain electrode layer 16 formed subsequently cannot be overlapped with the light-shielding layer 2, resulting in that the pixels with poor etching residues cannot be lit, and there are black Bad spots, and bad etching residues cannot be detected in the preparation process. Only when large black spots appear in the lighting test stage of the display product, it is determined that the source and drain electrode layers are not overlapped with the light-shielding layer. At this time, only the display The product is scrapped, resulting in waste. However, in the array substrate provided by the embodiment of the present application, in the area of the first via hole, the conductive connection pad is in contact with the light shielding layer, and then in the etching process of the interlayer insulating layer, there is no need to worry about damaging the conductive connection pad, and the etching process can be The rate is regulated to avoid the occurrence of etching residues of the insulating layer, so as to avoid bad black spots caused by the inability of the source-drain electrode layer and the light shielding layer to overlap, avoid product scrap due to etching residues, and save costs.

In the array substrate shown in FIG. 6 provided by the embodiment of the present application, the interlayer insulating layer 15 further has a fourth via hole 20 exposing the first conductive region 9 and a fifth via hole 19 exposing the second conductive region 10 , The source-drain electrode layer 16 includes: a source electrode 25 electrically connected to the first conductorized region 9 through a fourth via hole 20, and a drain electrode 26 electrically connected to the second conductorized region 10 through a fifth via hole 19. The drain electrode 26 extends through the second via hole 18 and the first via hole 17 to be electrically connected to the conductive connection pad 7 .

Optionally, as shown in FIG. 8 , the buffer layer 3 further has a third via hole 21 exposing the base substrate 1 ;

The array substrate further includes: a gate insulating layer 5 on the active layer 8 , a gate 6 on the gate insulating layer 5 , and the third via hole 21 and the base substrate. 1 contacting the buffer pad layer 22, and the first capacitor electrode 23 located on the buffer pad layer 22;

The buffer pad layer 22 and the gate insulating layer 5 are arranged in the same layer, and the first capacitor electrode 23 and the gate electrode 6 are arranged in the same layer.

In the array substrate shown in FIG. 8 in the embodiment of the present application, the source-drain electrode layer further includes a second capacitor electrode 24 that forms a capacitor with the first capacitor electrode 23 .

It should be noted that, in the prior art, as shown in FIG. 9 , the buffer layer 22 is arranged on the buffer layer 3 , the first capacitor electrode 23 is arranged on the buffer layer 22 , and the interlayer insulating layer 15 is arranged on the first capacitor electrode Steps are formed on the top of 23, and the source-drain electrode layer 16 formed subsequently is prone to poor climbing and disconnection at the steps. However, in the array substrate provided by the embodiment of the present application, the buffer pad layer and the first capacitor electrode are arranged in the via holes of the buffer layer, so that the subsequently formed interlayer insulating layer will not form steps on the first capacitor electrode, which ensures that the layer The flatness of the surface of the inter-insulating layer, so that the source and drain electrode layers are formed on a flat surface, and there will be no failure to climb and disconnect.

Based on the same inventive concept, an embodiment of the present application also provides a method for preparing an array substrate, as shown in FIG. 10 , the method includes:

S101, forming a pattern of a light shielding layer on a base substrate;

S102, forming a buffer layer on the light shielding layer;

S103, forming a groove in the buffer layer;

S104 , forming a pattern of a light-shielding portion and a pattern of an active layer, wherein the active layer includes: a semiconductor region, a first conductive region and a second conductive region connected to the semiconductor region, the light-shielding portion and the The semiconductor region fills the groove, the shape of the orthographic projection of the light shielding portion on the base substrate is annular, the side surface of the semiconductor region is completely surrounded by the light shielding portion, the first conductive region and The second conductive region is located over the light shielding portion and the semiconductor region.

In the method for fabricating an array substrate provided in this embodiment of the present application, a groove is formed in the buffer layer, then the light shielding layer and the semiconductor region of the active layer are filled in the groove, and the light shielding portion surrounds the side surface of the semiconductor region of the active layer, so that the light shielding portion can Blocking the side of the semiconductor region to avoid the problem of threshold voltage drift caused by light irradiation from the side of the semiconductor region can improve the working stability of the thin film transistor, avoid uneven display images, improve the display effect, and enhance the user experience. In addition, in the preparation method of the array substrate provided by the embodiment of the present application, the buffer layer needs to be patterned to form grooves before the active layer is formed, so as to avoid problems caused by film lifting or piercing during the deposition of the buffer layer. The source layer and the gate are shorted to avoid bright and dark spots.

Optionally, step S103 forms a groove in the buffer layer, which specifically includes:

The buffer layer is patterned by using a halftone mask process, and a part of the buffer layer is thinned to form grooves.

Optionally, the buffer layer is patterned by a halftone mask process, and a part of the buffer layer is thinned to form grooves, which specifically includes:

Coating photoresist on the buffer layer;

The photoresist is exposed and developed by a halftone mask process, and the photoresist is thinned in the area covering the groove to form a photoresist thinning area;

The photoresist in the photoresist thinning area is removed by an ashing process, and the buffer layer is etched to form grooves.

Optionally, step S103 forms a groove in the buffer layer, which specifically includes:

The buffer layer is patterned by a halftone mask process, the entire buffer layer is removed in a first area to expose the light shielding layer, and the buffer layer is thinned in a second area, where the first area is The orthographic projection of the base substrate surrounds the orthographic projection of the second region on the base substrate;

The pattern of forming the light-shielding portion and the pattern of the active layer specifically includes:

forming a pattern of the light-shielding portion in the first region;

A pattern of the active layer is formed on the light shielding portion and the buffer layer in the second region, wherein the semiconductor region fills the groove in the second region.

That is, in the first region, the light-shielding portion is in contact with the light-shielding layer. In the method for fabricating an array substrate provided in the embodiment of the present application, the light-shielding portion can not only shield the side of the semiconductor region, but also prevent light from irradiating into the semiconductor region of the active layer from the side. When the shading layer is in contact, the light incident on the side is blocked by the shading part and will not be reflected to the semiconductor region through the shading layer, thereby further improving the working stability of the thin film transistor, avoiding uneven display images, improving the display effect and improving the user experience.

Optionally, a halftone mask process is used to pattern the buffer layer, all the buffer layers are removed in the first area to expose the light shielding layer, and the buffer layer is thinned in the second area, specifically including:

Coating photoresist on the buffer layer;

The photoresist is exposed and developed using a halftone mask process, all the photoresist covering the first area is removed, and part of the photoresist covering the second area is removed;

performing an etching process to remove the buffer layer in the first region, exposing the light shielding layer, and forming the first region of the groove;

using an ashing process to remove the photoresist covering the second region;

An etching process is performed to remove part of the buffer layer in the second region to form the second region of the groove.

Optionally, when the buffer layer forms the groove in step S103, the method further includes:

forming a first via hole exposing the light shielding layer;

The pattern for forming the active layer specifically includes:

depositing a semiconductor material, using a patterning process to form a pattern of the active layer, and forming a pattern of conductive connection pads in contact with the light shielding layer in the first via hole;

After forming the pattern of the active layer, the method further includes:

conducting a conductorization process on the active layer and the conductive connection pads, and forming the first conductorization region and the second conductorization region on the active layer;

an interlayer insulating layer formed over the active layer;

patterning the interlayer insulating layer, exposing the conductive link pads, and forming a second via hole penetrating the interlayer insulating layer;

A pattern of a source-drain electrode layer is formed on the interlayer insulating layer, and the source-drain electrode layer is electrically connected to the conductive connection pad through the second via hole and the first via hole.

The patterning process for the interlayer insulating layer may include, for example, photoresist coating, exposure, development, and etching processes.

In the preparation method of the array substrate provided in the embodiment of the present application, before the active layer is formed, a first via hole exposing the light shielding layer is formed in the buffer layer, and a conductive connection pad in contact with the light shielding layer is formed in the area of the first via hole, In this way, even if the conductive connection pads are etched, it will not affect the electrical connection between the source-drain electrode layer and the light shielding layer through the conductive connection pads. Therefore, in the subsequent etching process of the interlayer insulating layer, there is no need to worry about damaging the conductive connection pads. The etching rate can be adjusted to remove all the interlayer insulating layers above the conductive connection pads, so as to avoid the etching residue of the insulating layer, so as to avoid the bad black spots caused by the inability of the source and drain electrode layers and the light shielding layer to overlap, and avoid the etching Product scrap caused by corrosion residues can save costs.

In specific implementation, the interlayer insulating layer is patterned, and after exposure and development processes, an overetching process may be performed on the interlayer insulating layer, thereby ensuring that all the interlayer insulating layers above the conductive connection pads are removed.

Optionally, when the buffer layer forms the groove in step S103, the method further includes:

forming a third via hole exposing the base substrate;

After forming the pattern of the active layer, the method further includes:

A gate insulating layer material and a gate material are sequentially deposited on the active layer, and a patterning process is used to form a pattern of the gate insulating layer on the active layer and a pattern of the gate on the gate insulating layer and forming a pattern of a buffer pad layer in contact with the base substrate and a pattern of a first capacitor electrode located on the buffer pad layer in the third via hole.

In the method for fabricating an array substrate provided in the embodiment of the present application, a third via hole exposing the base substrate is formed in the buffer layer, and a buffer pad layer and a first capacitor electrode are subsequently formed in the third via hole, so that the subsequently formed interlayer insulating layer is No steps are formed on the first capacitor electrode, which ensures the surface flatness of the interlayer insulating layer. In this way, the source and drain electrode layers are formed on a flat surface, and there will be no failure to climb and disconnect.

Next, the method for fabricating the array substrate provided by the embodiment of the present application is illustrated by taking the contact between the light-shielding portion in the array substrate and the light-shielding layer as an example. As shown in FIG. 11 to FIG. 12 , the fabrication method for the array substrate includes the following steps:

S201, depositing the material of the light-shielding layer 2 on the base substrate 1, and using a patterning process to form a pattern of the light-shielding layer 2;

The material of the light-shielding layer can be, for example, molybdenum (Mo) or an aluminum/molybdenum (Al/Mo) alloy; the thickness of the material of the light-shielding layer can be deposited, for example,

S202, deposit the material of the buffer layer on the whole surface to form the buffer layer 3, and coat the photoresist 27 (PR glue) on the buffer layer;

The material of the buffer layer can be, for example, silicon oxide (SiO _x ), and the thickness of the buffer layer can be, for example,

S203, using a halftone mask process to pattern the PR glue 27, removing all the photoresist covering the first via area, covering the third via area and covering the first area, and removing part of the photoresist covering the second area engraving;

In a specific implementation, the width of the first region may be, for example, 3 micrometers (μm) to 5 μm;

S204, using a dry etching process to process the buffer layer 3 to form a first via hole 17 exposing the light shielding layer, a third via hole 21 exposing the base substrate, and a first region 13 exposing the groove of the light shielding layer;

S205, adopting an ashing process to remove the PR glue 27 covering the second region;

S206, using a dry etching process to thin the buffer layer 3 to form the second region 14 of the groove;

厚度的缓冲层；In specific implementation, for example, it can be thinned

Thickness of the buffer layer;

S207, remove the PR glue on the buffer layer 3;

S208, coating a light-shielding material, and forming a pattern of the light-shielding portion 11 in the first region of the groove through an exposure and development process;

The light-shielding material may be, for example, a black light-shielding material, such as a material of a pixel definition layer or a black matrix.

S209, depositing a semiconductor material, forming a pattern of the active layer 8 and a pattern of the conductive connection pad 7 through a patterning process, and the active layer 8 is divided into a semiconductor region 4, a first conductive region 9 and a second conductive region 10;

The semiconductor material may be, for example, Indium Gallium Zinc Oxide (IGZO);

S210, depositing insulating material and metal material, and forming a pattern of gate insulating layer 5, a pattern of buffer pad layer 22, a pattern of gate 6 and a pattern of first capacitor electrode 23 through a patterning process;

The insulating material may be, for example, SiO ₂ ; the metal material may be, for example, copper (Cu), and the thickness of the gate material deposition may be, for example,

S211 , conducting conductorization processing on the first conductive region 9 , the second conductive region 10 and the conductive connection pad 7 ;

S212, depositing an insulating material to form an interlayer insulating layer 15, and forming a second via hole 18, a fourth via hole 20 and a fifth via hole 19 through a patterning process;

图形化工艺例如包括PR胶涂覆、曝光、显影以及刻蚀工艺；The material of the interlayer insulating layer can be, for example, silicon oxide SiO ₂ , and the thickness of the interlayer insulating layer can be, for example,

Patterning processes include, for example, PR glue coating, exposure, development, and etching processes;

S213, depositing a source and drain material, and forming a pattern of the source and drain electrode layers 16 through a patterning process;

The source-drain electrode layer 16 includes: a second capacitor electrode 24, a source electrode 25 electrically connected to the first conductive region 9, and a drain electrode 26 electrically connected to the second conductive region 10; the drain electrode 26 extends through the second conductive region 10. The holes 18 and the first via holes 17 are electrically connected to the conductive connection pads 7 .

If the array substrate is applied to an OLED display product, after step S213, the passivation layer and the film layers of the OLED device may also be fabricated.

The embodiments of the present application provide a display panel, which includes the above-mentioned array substrate provided by the embodiments of the present application.

To sum up, in the array substrate, the preparation method thereof, and the display panel provided by the embodiments of the present application, the side surface of the semiconductor region of the active layer is surrounded by the light shielding portion, and the light shielding portion shields the side surface of the semiconductor region to prevent light from passing through the semiconductor region. The problem of threshold voltage drift caused by side irradiation of the semiconductor region can improve the working stability of thin film transistors, avoid uneven display images, improve display effects, and improve user experience. And before the active layer is formed, the buffer layer needs to be patterned to form grooves, so as to avoid the short circuit between the active layer and the gate caused by film lifting or piercing during the deposition process of the buffer layer. Highlights and Darkness.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims (11)

1. An array substrate, characterized in that, the array substrate comprises: a base substrate, a light-shielding layer located on the base substrate, a buffer layer located on the light-shielding layer, and a buffer layer located between the buffer layers. The active layer on the upper part, and the light shielding part; the buffer layer has a groove; The active layer includes: a semiconductor region, a first conductive region and a second conductive region connected to the semiconductor region; The semiconductor region and the light shielding portion fill the groove; the shape of the orthographic projection of the light shielding portion on the base substrate is a ring shape, the side surface of the semiconductor region is completely surrounded by the light shielding portion, and the first A conductive region and the second conductive region are located on the light shielding portion and the semiconductor region; The orthographic projection of the light shielding layer on the base substrate covers the orthographic projection of the semiconductor region on the base substrate. 2 . The array substrate of claim 1 , wherein the thickness of the light shielding portion is equal to the thickness of the semiconductor region. 3 . 3 . The array substrate according to claim 1 , wherein the groove is divided into a first area and a second area, the thickness of the first area is greater than that of the second area, and the first area is thicker than the second area. 4 . A region exposes the light shielding layer, the light shielding portion fills the first region, and the semiconductor region fills the second region. 4 . The array substrate according to claim 1 , wherein the light shielding layer is a conductor, and the buffer layer further has a first via hole exposing the light shielding layer; 5 . The array substrate further includes: a conductive connection pad disposed on the same layer as the active layer, an interlayer insulating layer on the active layer, and a source-drain electrode layer on the interlayer insulating layer; the conductive connection pad is in contact with the light shielding layer at the first via hole; The interlayer insulating layer has a second via hole through its thickness, and the source-drain electrode layer is electrically connected to the conductive connection pad through the second via hole and the first via hole. 5. The array substrate according to claim 1, wherein the buffer layer further has a third via hole exposing the base substrate; The array substrate further includes: a gate insulating layer on the active layer, a gate on the gate insulating layer, and a buffer pad layer in contact with the base substrate at the third via hole , and a first capacitor electrode located on the buffer layer; The buffer pad layer and the gate insulating layer are arranged in the same layer, and the first capacitor electrode and the gate are arranged in the same layer. 6. A method for preparing an array substrate, wherein the method comprises: forming a pattern of the light shielding layer on the base substrate; forming a buffer layer on the light shielding layer; forming grooves in the buffer layer; A pattern of a light shielding portion and a pattern of an active layer are formed, wherein the active layer includes a semiconductor region, a first conductive region and a second conductive region connected to the semiconductor region, the light shielding portion and the The semiconductor region fills the groove, the shape of the orthographic projection of the light shielding portion on the base substrate is annular, the side surface of the semiconductor region is completely surrounded by the light shielding portion, the first conductive region and the A second conductive region is located over the light shielding portion and the semiconductor region. 7. The method according to claim 6, wherein the forming a groove in the buffer layer specifically comprises: The buffer layer is patterned by a halftone mask process, and a part of the buffer layer is thinned to form grooves. 8. The method according to claim 6, wherein the forming a groove in the buffer layer specifically comprises: The buffer layer is patterned by a halftone mask process, the entire buffer layer is removed in a first area to expose the light shielding layer, and the buffer layer is thinned in a second area, where the first area is The orthographic projection of the base substrate surrounds the orthographic projection of the second region on the base substrate; The pattern of forming the light-shielding portion and the pattern of the active layer specifically includes: forming a pattern of the light-shielding portion in the first region; A pattern of the active layer is formed on the light shielding portion and the buffer layer in the second region, wherein the semiconductor region fills the groove in the second region. 9 . The method according to claim 6 , wherein when the buffer layer forms the groove, the method further comprises: 10 . forming a first via hole exposing the light shielding layer; The pattern for forming the active layer specifically includes: depositing a semiconductor material, using a patterning process to form a pattern of the active layer, and forming a pattern of conductive connection pads in contact with the light shielding layer in the first via hole; After forming the pattern of the active layer, the method further includes: conducting a conductorization process on the active layer and the conductive connection pads, and forming the first conductorization region and the second conductorization region on the active layer; an interlayer insulating layer formed over the active layer; patterning the interlayer insulating layer, exposing the conductive connection pads, and forming a second via hole penetrating the interlayer insulating layer; A pattern of a source-drain electrode layer is formed on the interlayer insulating layer, and the source-drain electrode layer is electrically connected to the conductive connection pad through the second via hole and the first via hole. 10 . The method according to claim 7 , wherein when the buffer layer forms the groove, the method further comprises: 10 . forming a third via hole exposing the base substrate; After forming the pattern of the active layer, the method further includes: A gate insulating layer material and a gate material are sequentially deposited on the active layer, and a patterning process is used to form a pattern of the gate insulating layer on the active layer and a pattern of the gate on the gate insulating layer and forming a pattern of a buffer pad layer in contact with the base substrate and a pattern of a first capacitor electrode located on the buffer pad layer in the third via hole. 11. A display panel, comprising the array substrate according to any one of claims 1 to 5.

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