CN110729313B - Display panel, display panel manufacturing method, and display device - Google Patents

Abstract

The application discloses a display panel, a display device and a preparation method of the display panel. The light shielding layer is composed of a plurality of light shielding units, each light shielding unit corresponds to the thin film transistor one by one and is positioned at one side of the thin film transistor, which is close to the direction of the substrate; the light shielding unit comprises a first light shielding area and a second light shielding area, and the second light shielding area is arranged to surround the first light shielding area; according to the technical scheme provided by the application, due to the existence of the first shading area of the shading unit, the shading function of the shading layer can not be influenced on one hand, so that the active layer is protected; meanwhile, on the other hand, even if the interlayer insulating layer via hole extends to the shading layer due to the technical problem, the short circuit caused by the conductive path between the source and the drain and the first electrode is not formed, so that poor bright point can not be caused when the voltage is applied to the drain, and the display effect and the product quality can be effectively improved.

Description

Display panel, display panel manufacturing method, and display device

Technical Field

The present invention relates to the field of display technology, and in particular to a display panel, a method for preparing a display panel, and a display device.

Background technique

Thin Film Transistor (TFT) is a field effect transistor with multiple functional thin film layers made of transparent glass as the substrate. It plays a very important role in the working performance of display devices. TFT display screen is a type of active matrix liquid crystal display device. Each of its liquid crystal pixels is driven by a thin film transistor array integrated behind the pixel. Thin film transistor array technology is often used in the process to improve the picture quality. Therefore, it is widely used in electronic display devices such as mobile phones, tablets, computer monitors, and televisions.

Top-gate TFT is a type of TFT. It has the characteristics of short channel, which can effectively improve the on-state current when it is working. In addition, the overlapping area between the gate and the source and drain of the top-gate TFT is small, so the parasitic capacitance generated is small, which can significantly improve the display effect and effectively reduce power consumption. Due to the above-mentioned significant advantages of top-gate TFT, it has attracted more and more attention. At present, most top-gate TFTs use IGZO (indium gallium zinc oxide) semiconductors with high carrier mobility as the active layer.

Summary of the invention

The present invention provides a display panel, a method for preparing the display panel, and a display device.

The technical solution adopted is a display panel, comprising:

a substrate substrate, and

A light shielding layer and a plurality of thin film transistors arranged in an array on the substrate;

The light shielding layer is composed of a plurality of light shielding units, each of which corresponds to the thin film transistor one by one and is located on a side of the thin film transistor close to the substrate;

A buffer layer is arranged on the substrate in a direction away from the light shielding layer;

The thin film transistor comprises an active layer, a gate insulating layer, a gate, an interlayer insulating layer, and a source and drain electrode layer which are sequentially arranged in a direction away from the buffer layer;

The active layer includes a conductive region where projections of the active layer and the gate insulating layer on the substrate do not overlap, and a channel region where projections of the active layer and the gate insulating layer on the substrate overlap;

The source-drain layer includes a first electrode and a second electrode;

The shading unit includes a first shading area and a second shading area, and the second shading area is arranged to surround the first shading area;

The projection of the channel region on the base substrate is located within the projection of the second light shielding region on the base substrate;

The thin film transistor is sequentially provided with a passivation layer and an anode in a direction away from the substrate.

Optionally, the interlayer insulating layer includes a first via hole and a second via hole;

There is at least a partial overlap between the first light-shielding area and a projection area of the first via hole on the light-shielding layer;

The second light-shielding area and the projection area of the second via hole on the light-shielding layer at least partially overlap.

Optionally, at least a portion of the first electrode is located in the first via hole; the first light-shielding area completely overlaps with a projection area of the first via hole on the light-shielding layer, and contacts the first electrode through the first via hole.

Optionally, at least a portion of the second electrode is located in the second via hole; the second light-shielding area is located outside a projection area of the first via hole on the light-shielding layer, and is in contact with the second electrode through the second via hole.

Optionally, in the shading unit, the first shading area and the second shading area are isolated from each other by a gap and are not connected to each other.

Optionally, a projection of the gap on the substrate completely falls outside a projection area of the channel region on the substrate.

Optionally, the materials of the first shading area and the second shading area include metal conductive materials such as aluminum, molybdenum or aluminum-molybdenum-niobium alloy, and the thickness is 0.20-0.25 um.

Optionally, the first shading area and the second shading area may be seamlessly connected as one.

Optionally, the first light-shielding area is made of insulating material, and the second light-shielding area is made of conductive material.

Optionally, the insulating material of the first shading area is metal oxide or metal nitride, and the conductive material of the second shading area is metal materials such as aluminum, molybdenum or aluminum-molybdenum-niobium alloy, with a thickness of 0.20 to 0.25 um.

The present invention provides a display device, characterized by comprising any one of the technical features of the above-mentioned display panel.

The present invention provides a method for preparing a display panel, comprising:

providing a substrate substrate, and

Composing and depositing a plurality of light shielding units in the light shielding layer, forming a first light shielding area and a second light shielding area on the light shielding units, wherein the second light shielding area is configured to surround the first light shielding area;

Depositing a buffer layer, patterning and depositing to form an active layer, depositing a gate insulating layer, patterning and depositing to form a gate, depositing an interlayer insulating layer, patterning and depositing to form a source and drain;

Preferably, when forming a plurality of the light shielding units, gaps are prepared by coating photoresist, exposing, developing, and dry etching processes, so that the first light shielding area is surrounded by the second light shielding area and isolated from the second light shielding area by the gaps;

The first light-shielding area and the second light-shielding area are both made of metal conductive material.

Preferably, a buffer layer is deposited on the light shielding unit, and a photoresist is used to pattern the buffer layer to form an active layer pattern, and a gate insulating layer pattern is patterned on the active layer, and a metal gate is patterned on the gate insulating layer;

Without stripping off the photoresist used for patterning above the gate, the gate insulating layer is etched by a self-alignment process, and the edge of the active layer is exposed and subjected to a conductor process;

Depositing an interlayer insulating layer, patterning to form a pattern to be etched, and forming a first via hole and a second via hole by plasma dry etching;

Preferably, when forming a plurality of the shading units, it includes:

Using a half-tone mask to perform an exposure and development process, completely retaining the photoresist in the opaque area corresponding to the second light-shielding area, partially retaining the photoresist in the semi-transparent area corresponding to the first light-shielding area, developing and removing the photoresist in the completely transparent area, and performing an etching process to form a first light-shielding layer pattern;

Performing an ashing process on the remaining photoresist on the light shielding layer pattern so that the photoresist in the semi-transparent area is removed by ashing;

Performing oxidation or nitridation treatment on the exposed portion of the first light shielding area corresponding to the semi-transparent area to form an insulator;

Stripping off all photoresists to form the light shielding layer

Wherein, the shading unit is configured as an integrated structure, wherein the first shading area and the second shading area are configured to be seamlessly connected;

The first light shielding area is configured as a metal oxide or metal nitride material, and the second light shielding area is configured as a metal material;

Depositing an interlayer insulating layer, patterning to form a pattern to be etched, and forming a first via hole and a second via hole by plasma dry etching;

The display panel and display device of the present invention include a substrate, a light shielding layer on the substrate, and a plurality of thin film transistors arranged in an array. The light shielding layer is composed of a plurality of light shielding units, each of which corresponds to the thin film transistor one by one and is located on the side of the thin film transistor close to the substrate; the light shielding unit includes a first light shielding area and a second light shielding area, and the second light shielding area is arranged to surround the first light shielding area. According to the technical solution provided by the present application, due to the existence of the first light shielding area of the light shielding unit, on the one hand, the light shielding function of the light shielding layer can be not affected, so that the active layer can be protected; on the other hand, it can ensure that even if the via hole of the interlayer insulating layer extends to the light shielding layer due to process problems, a conductive path between the source and drain and the first electrode will not be formed to cause a short circuit, so that when a voltage is applied to the drain, no bad bright spot will be caused, which can effectively improve the display effect and product quality.

BRIEF DESCRIPTION OF THE DRAWINGS

Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

FIG1 is a schematic diagram of a cross-sectional structure of a display panel where a thin film transistor is located;

FIG2 is a schematic diagram of sub-pixel circuit connection in an embodiment of the present invention;

FIG3 is a schematic diagram of a cross-sectional structure of a display panel;

FIG4 is a schematic diagram of a shading unit structure;

FIG5 is a schematic diagram of another cross-sectional structure of a display panel;

FIG6 is a schematic diagram of another shading unit structure;

FIG. 7 is a schematic diagram of a process flow for manufacturing a display panel;

Detailed ways

The present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the invention are illustrated in the accompanying drawings.

It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

FIG1 is a schematic diagram of a cross-sectional structure of a display panel where a thin film transistor is located;

As shown in the figure, a display panel is provided, which includes a substrate 10 and a plurality of thin film transistors prepared thereon, including an active layer 40, a gate 60, and a source-drain electrode layer 80; the projection area of the active layer 40 on the substrate has overlapping and non-overlapping parts with the projection area of the gate on the substrate. The active layer may be made of semiconductor materials such as amorphous silicon, polycrystalline silicon, and metal oxide.

Optionally, the material selected in this embodiment is IGZO (indium gallium zinc oxide); the non-overlapping portion can become a conductor region 401 by doping metal ions for electrical connection; and the overlapping portion constitutes an active region in the thin film transistor, namely, a channel region 402.

A metal shading layer 20 deposited on the base substrate 10 is also included between the base substrate 10 and the thin film transistor; the shading unit 20 is a shading metal layer, which is composed of a plurality of shading units corresponding to a plurality of thin film transistors one by one, and the projection of each of the shading units on the base substrate at least overlaps with the projection of each of the thin film transistors on the base substrate, so as to protect the active layer structure in the thin film transistor thereon from direct exposure to light, thereby avoiding failure or weakening of the function of the transistor.

The display panel also includes multiple functional layers, wherein: a buffer layer 30 is arranged between the light-shielding layer 20 and the active layer 40, and is used to alleviate the influence of external stress on the inside of the display panel; a gate insulating layer 50 is arranged between the active layer 40 and the gate 60, and is used to prevent the active layer and the gate from being electrically connected; an interlayer insulating layer 70 is arranged inside the thin film transistor to prevent the source and drain from being electrically connected to other connecting lines in the display panel, and a passivation layer 90 is arranged to cover the thin film transistor in a direction away from the substrate; wherein the source and drain of the thin film transistor on the display panel are connected to the conductor area 401 of the active layer 40 through a first via hole 701 arranged in the interlayer insulating layer 70; the source and drain of the thin film transistor on the display panel are connected to the light-shielding layer 40 through a second via hole 702 arranged through the interlayer insulating layer 70 and the buffer layer 30; the source/drain of the thin film transistor on the display panel is electrically connected to the anode layer 100 through the passivation layer, and the material of the anode layer is the transparent electrode ITO.

In the circuit design of AMOLED products, a sub-pixel circuit connection diagram in an embodiment of the present invention is adopted as shown in FIG2 : the basic structure of the sub-pixel circuit is shown by taking an N-type transistor as an example. Specifically, the sub-pixel circuit includes a driving transistor T3, a first switching transistor T1, a second switching transistor T2 and a light-emitting element.

The first electrode of the first switch transistor T1 is connected to the data line DATA, the second electrode of the first switch transistor T2 is connected to the gate of the driving transistor T3, and the gate of the first switch transistor T1 is connected to the first scan line G1. The first electrode of the driving transistor T3 is connected to the first power supply terminal VDD, the second electrode of the driving transistor T3 is connected to the anode of the light emitting element, the cathode of the light emitting element is connected to the second power supply terminal VSS, the first electrode of the second switch transistor T2 is connected to the second electrode of the driving transistor T3, the second electrode of the second switch transistor T2 is connected to the sensing line Sense, and the gate of the second switch transistor T2 is connected to the second scan line G2.

In this embodiment, IGZO semiconductor is used as the active layer. The process flow includes: using a chemical vapor deposition process (hereinafter referred to as deposition) on the substrate, and using an optical mask to form a light shielding layer through processes such as coating (photoresist PR), exposure, and development (hereinafter referred to as patterning), further depositing a buffer layer, further patterning and depositing to form an active layer, further depositing a gate insulating layer, further patterning and depositing to form a gate, further not stripping the PR glue above the pattern, further using a self-alignment process to perform a high-energy gas dry etching process on the lower gate insulating layer, further performing a conductor process for the active layer, further depositing an interlayer insulating layer and patterning to continue dry etching to form a first via and a second via, further patterning and depositing to form a source/drain, and finally depositing a passivation layer and an anode. Among them, the signal line connected to the source 801 passes through the first power supply terminal VDD signal; the drain 802 and the anode 100 are overlapped with each other; the drain 802 is electrically connected to the shielding layer 20 through the second via 702, and the electrical signal is accessed through the source and drain layer;

Optionally, the conductor area 401 in the non-channel part of the active layer 20 and the shielding unit together form a storage capacitor. The storage capacitor formed by the light shielding layer 20 and the conductor area 401 in the active layer 40 as two electrodes can store more charge and has excellent working performance because they are only separated by the buffer layer 30 and are close to each other.

In the actual process of preparing thin-film transistors, due to the non-uniformity of large-area dry etching, the gate insulating layer in the pixel area will be unevenly etched, and some positions will be etched to the buffer layer below, resulting in uneven light extraction efficiency of the display device; secondly, since the buffer layer is etched to different degrees at different positions, the process is difficult to control during the subsequent etching of the interlayer insulating layer, which can easily cause etching damage to the grating shielding layer pattern layer below; in addition, since the etching amount is difficult to control when preparing vias, over-etching often causes short circuits, making some pixels of the display device unable to light up normally, resulting in bad pixels. Based on the above defects and shortcomings of the prior art, it is necessary to propose a new display panel structure design and display panel preparation method in actual process operations, so as to improve the display quality of the product.

In the actual process, since the strength of the dry etching in the process when forming the first via is difficult to control, a large amount of over-etching is likely to occur; and the active layer is generally formed thinner in the actual process, which makes some parts easy to be missing or dry-etched, resulting in the first via being punched all the way to the shading unit of the shading layer below, thereby causing the subsequent drain to be short-circuited with the shading unit in the shading layer, forming a path of source → shading unit → drain → anode ITO, thereby causing a bright spot when voltage is applied to the drain.

The following examples illustrate a number of embodiments, which can effectively solve the problem of high occurrence of bright spots due to short circuit between the drain and the light shielding unit, thereby significantly improving the display quality of the product.

Embodiment 1:

FIG3 is a schematic diagram of a cross-sectional structure of a display panel;

The display panel includes a substrate 10, and a plurality of thin film transistors prepared thereon, including an active layer 40, a gate 60, and a source-drain electrode layer 80; the projection area of the active layer 40 on the substrate has overlapping and non-overlapping parts with the projection area of the gate on the substrate. Generally speaking, the optional material of the active layer is a semiconductor material such as amorphous silicon, polycrystalline silicon, and metal oxide. Optionally, the material selected in this embodiment is IGZO (indium gallium zinc oxide); the non-overlapping part can be made into a conductor area 401 by doping metal ions for electrical connection; and the overlapping part constitutes the active area 402 in the thin film transistor.

A metal shading layer 20 deposited on the base substrate 10 is also included between the base substrate 10 and the thin film transistor; the shading unit 20 is a shading metal layer, which is composed of a plurality of shading units corresponding to a plurality of thin film transistors one by one, and the projection of each of the shading units on the base substrate at least overlaps with the projection of each of the thin film transistors on the base substrate, so as to protect the active layer structure of the thin film transistor thereon from direct exposure to light, thereby avoiding failure or weakening of the function of the transistor.

The display panel also includes multiple functional layers, wherein: a buffer layer 30 is arranged between the light-shielding layer 20 and the active layer 40, and is used to alleviate the influence of external stress on the inside of the display panel; a gate insulating layer 50 is arranged between the active layer 40 and the gate 60, and is used to prevent the active layer and the gate from being electrically connected; an interlayer insulating layer 70 is arranged inside the thin film transistor to prevent the source and drain electrodes from being electrically connected to other connecting lines in the display panel, and a passivation layer 90 is arranged to cover the thin film transistor in a direction away from the substrate; wherein the source/drain level in the thin film transistor on the display panel is connected to the conductor area 401 of the active layer 40 through a first via hole 701 arranged in the interlayer insulating layer 70; the source/drain level in the thin film transistor on the display panel is connected to the light-shielding layer 40 through a second via hole 702 arranged through the interlayer insulating layer 70 and the buffer layer 30; the source and drain level in the thin film transistor on the display panel is electrically connected to the anode layer 100 through the passivation layer, and the anode layer material is a transparent electrode ITO.

In the display panel, the light shielding unit corresponding to the thin film transistor includes a first light shielding area 201 and a second light shielding area 202, the second light shielding area is arranged to surround the first light shielding area, and the light shielding layer 20 is designed to be a partially hollow structure;

The first light shielding area is located within a projection area of the first via hole on the light shielding area, and is in contact with a source or a drain in the first via hole;

The second light shielding area is located outside the projection area of the first via hole on the light shielding layer, and is in contact with the drain or source in the second via hole;

FIG4 is a schematic diagram of a shading unit structure;

In the shading unit, the first shading area is surrounded by the second shading area, wherein, in the shading unit, the first shading area and the second shading area are isolated from each other by a slit and are not connected to each other; the projection of the slit on the substrate completely falls outside the projection area of the active layer channel area on the substrate. In this way, the slit causes the two areas to be disconnected and does not overlap with the active layer channel area, thereby preventing ambient light from irradiating the active area in the thin film transistor through the slit and affecting the device life.

The first light shielding area and the second light shielding area are configured with conductive materials, generally metal materials such as iron, aluminum, silver, or nanomaterials with high conductivity. This will not affect the light shielding function of the light shielding layer, and at the same time ensure that even if the first via is in contact with the light shielding unit due to process problems, the first light shielding area will become an island structure due to the existence of the isolation gap, and will not form a path between the drain and the anode ITO, thereby avoiding the occurrence of bad bright spots when voltage is applied to the drain.

The method for preparing a display panel in an embodiment of the present invention comprises the steps of: providing a substrate, and sequentially patterning and depositing a light shielding layer, depositing a buffer layer, patterning and depositing to form an active layer, depositing a gate insulating layer, patterning and depositing to form a gate, depositing an interlayer insulating layer, and patterning and depositing to form a source and a drain;

The light-shielding layer includes a plurality of light-shielding units; a first light-shielding area and a second light-shielding area are formed on the light-shielding units, and the second light-shielding area is arranged to surround the first light-shielding area.

Preferably, the display panel manufacturing method further comprises: when forming a plurality of the light shielding units, preparing gaps by coating photoresist, masking, exposure, development, and dry etching processes, so that the first light shielding area is surrounded by the second light shielding area and isolated from the second light shielding area by the gap; the materials of the first light shielding area and the second light shielding area are both configured as metal conductive materials;

Optionally, the material is configured as a metal conductive material such as aluminum, molybdenum or aluminum-molybdenum-niobium alloy, with a thickness of 0.20 to 0.25 um.

Preferably, a method for manufacturing a display panel further comprises: depositing a buffer layer on the light shielding unit, patterning the buffer layer to form an active layer pattern using a photoresist, patterning the active layer to form a gate insulating layer pattern, and patterning the gate insulating layer to form a metal gate;

Without stripping off the photoresist used for patterning above the gate, the gate insulating layer is etched by a self-alignment process, and the edge of the active layer is exposed and subjected to a conductor process;

Depositing an interlayer insulating layer, patterning to form a pattern to be etched, and forming a first via hole and a second via hole by plasma dry etching;

The projection area of the first light-shielding area on the light-shielding layer and the projection area of the first via hole on the light-shielding layer at least partially overlap;

A projection area of the second light-shielding region on the light-shielding layer and a projection area of the second via hole on the light-shielding layer at least partially overlap.

In this way, the light shielding function of the light shielding unit is not affected, and at the same time, even if the interlayer insulating layer via hole is etched too much and etches onto the light shielding layer due to process problems, a path of source → light shielding unit → drain → anode ITO will not be formed, so that when the drain is supplied with voltage, no bright spot defect will be caused. The solution of this embodiment can significantly reduce the incidence of bright spot defects, thereby significantly improving the display quality of the product.

Embodiment 2:

FIG5 is a schematic diagram of another cross-sectional structure of a display panel;

This example provides a display panel, which includes a substrate 10, and a plurality of thin film transistors prepared thereon, including an active layer 40, a gate 60, and a source/drain electrode layer 80; the projection area of the active layer 40 on the substrate has overlapping and non-overlapping parts with the projection area of the gate on the substrate. Generally speaking, the optional material of the active layer is a semiconductor material such as amorphous silicon, polycrystalline silicon, and metal oxide. Optionally, the material selected in this embodiment is IGZO (indium gallium zinc oxide); the non-overlapping part can be made into a conductor area 401 by doping metal ions for electrical connection; and the overlapping part constitutes the active area in the thin film transistor, that is, the channel area 402.

A metal shading layer 20 deposited on the base substrate 10 is also included between the base substrate 10 and the thin film transistor; the shading unit 20 is a shading metal layer, which is composed of a plurality of shading units corresponding to a plurality of thin film transistors one by one, and the projection of each of the shading units on the base substrate at least overlaps with the projection of each of the thin film transistors on the base substrate, so as to protect the active layer structure in the thin film transistor thereon from direct exposure to light, thereby avoiding failure or weakening of the function of the transistor.

The display panel also includes multiple functional layers, wherein: a buffer layer 30 is arranged between the light-shielding layer 20 and the active layer 40, and is used to alleviate the influence of external stress on the inside of the display panel; a gate insulating layer 50 is arranged between the active layer 40 and the gate 60, and is used to avoid electrical connection between the active layer and the gate; an interlayer insulating layer 70 is arranged inside the thin film transistor to prevent the source and drain electrodes from being electrically connected to other connecting lines in the display panel, and a passivation layer 90 is arranged to cover the thin film transistor in a direction away from the substrate; wherein the source and drain of the thin film transistor on the display panel are connected to the conductor area 401 of the active layer 40 through a first via hole 701 arranged in the interlayer insulating layer 70; the source and drain of the thin film transistor on the display panel are connected to the light-shielding layer 40 through a second via hole 702 arranged through the interlayer insulating layer 70 and the buffer layer 30; the source and drain of the thin film transistor on the display panel are electrically connected to the anode layer 100 through the passivation layer, and the material of the anode layer is a transparent electrode ITO.

In the display panel, the shading unit corresponding to the thin film transistor includes a first shading area 201 and a second shading area 202, and the second shading area is arranged to surround the first shading area; preferably, the shading unit is designed to be a partially insulated structure;

The first light shielding area is located within a projection area of the first via hole on the light shielding area, and is in contact with a source or a drain in the first via hole;

The second light shielding area is located outside the projection area of the first via hole on the light shielding layer, and is in contact with the drain or source in the second via hole;

FIG6 is a schematic diagram of another shading unit structure;

In the shading unit, the first shading area is surrounded by the second shading area; the shading unit is an integrated structure, wherein the first shading unit and the second shading unit are connected to each other;

The first light shielding unit is configured as an insulating material, and the second light shielding unit is configured as a conductive material; the insulating material can be a metal oxide or a metal nitride; the conductive material can be a metal conductive material such as iron, aluminum, silver, molybdenum or aluminum-molybdenum-niobium alloy, or a nanomaterial with a high conductivity coefficient. This will not affect the light shielding function of the light shielding layer, and at the same time ensure that even if the first via is in contact with the light shielding unit due to process problems, due to the existence of the first light shielding area, the over-etched area corresponding to the light shielding layer is an insulating area, and a path between the drain and the anode ITO will not be formed, thereby avoiding the occurrence of bad bright spots when voltage is applied to the drain.

FIG. 7 is a schematic diagram of a process flow for manufacturing a display panel;

The method for preparing a display panel comprises the steps of: providing a substrate, and sequentially patterning and depositing a light shielding layer, depositing a buffer layer, patterning and depositing to form an active layer, depositing a gate insulating layer, patterning and depositing to form a gate, depositing an interlayer insulating layer, and patterning and depositing to form a source and a drain;

The light shielding layer includes a plurality of light shielding units; a first light shielding area and a second light shielding area are formed on the light shielding units, and the first light shielding area and the second light shielding area are arranged to be staggered with each other;

Forming a plurality of thin film transistors correspondingly on the plurality of light shielding units;

Preferably, when forming the plurality of light shielding units, the process includes: performing an exposure and development process using a half-tone mask, completely retaining the photoresist in the opaque area corresponding to the second light shielding area, partially retaining the photoresist in the semi-transparent area corresponding to the first light shielding area, removing the photoresist in the completely transparent area by development, and performing an etching process to form a first light shielding layer pattern;

Performing an ashing process on the remaining photoresist on the light shielding layer pattern so that the photoresist in the semi-transparent area is removed by ashing;

Performing oxidation or nitridation treatment on the exposed portion of the first light shielding area corresponding to the semi-transparent area to form an insulator;

Stripping off all photoresists to form the light shielding layer

Wherein, the shading unit is configured as an integrated structure, wherein the first shading area and the second shading area are configured to be directly connected to each other;

The first light shielding area is configured as a metal oxide or metal nitride material, and the second light shielding area is configured as a metal material;

Depositing an interlayer insulating layer, patterning to form a pattern to be etched, and forming a first via hole and a second via hole by plasma dry etching;

The projection area of the first light-shielding area on the light-shielding layer and the projection area of the first via hole on the light-shielding layer at least partially overlap;

A projection area of the second light-shielding region on the light-shielding layer and a projection area of the second via hole on the light-shielding layer at least partially overlap.

This will not affect the shading function of the shading unit, and at the same time ensure that even if the interlayer insulation layer hole is punched on the shading layer due to process problems, a path of source → shading unit → drain → anode ITO will not be formed, so that no bright spot will be caused when the drain is supplied with voltage.

The use of this technical solution can effectively solve the problem of high incidence of bright spots caused by short circuit between the source/drain and the light shielding layer, thereby significantly improving the display quality of the product, and this technical proposal does not add any exposure process.

Embodiment 3:

This embodiment provides a display device, which includes the display panel described in Embodiment 1 or Embodiment 2. The display device can be any product or component with a display function, such as an OLED panel, a mobile phone, a tablet computer, a digital photo frame, a laptop computer, a monitor, a television, a navigator, a vehicle-mounted multifunctional rearview mirror device, etc.

The display device of this embodiment has the display panel in Embodiment 1 or 2, so its preparation process is simple and the process reliability is high, and the adverse problems caused by local short circuits can be solved, which can effectively improve the display effect and product quality.

Of course, the display device of this embodiment may also include other conventional structures, such as a power supply unit, a display driving unit, a light emitting unit, a packaging unit, and a frame structure.

In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

It is understood that the above description is only an exemplary embodiment of the present application and an explanation of the technical principles, structures and process steps used. For those of ordinary skill in the art, it should be understood that the scope of the invention involved in this application is not limited to the technical solution formed by a specific combination of the above-mentioned technical features, but also should cover other technical solutions formed by any combination of the above-mentioned technical features or their equivalent features without departing from the inventive concept. For example, the above-mentioned features are replaced with the technical features with similar functions disclosed in this application (but not limited to) and the technical solution formed.

Claims (14)

1. A display panel, characterized by comprising:

a substrate base, and

A shading layer and a plurality of thin film transistors arranged in an array on the substrate;

the light shielding layer is composed of a plurality of light shielding units, each light shielding unit corresponds to the thin film transistor one by one and is positioned at one side of the thin film transistor, which is close to the direction of the substrate base plate;

A buffer layer is arranged on the substrate base plate in the direction away from the shading layer;

The thin film transistor comprises an active layer, a gate insulating layer, a gate, an interlayer insulating layer and a source drain layer which are sequentially arranged in the direction away from the buffer layer;

The active layer comprises a conductive region which is not overlapped with the projection of the active layer and the gate insulating layer on the substrate, and a channel region which is overlapped with the projection of the active layer and the gate insulating layer on the substrate;

The source-drain electrode layer comprises a first electrode and a second electrode;

the light shielding unit comprises a first light shielding area and a second light shielding area, and the second light shielding area is arranged surrounding the first light shielding area;

The projection of the channel region on the substrate is positioned in the projection of the second shading region on the substrate;

The thin film transistor is sequentially provided with a passivation layer and an anode in a direction away from the substrate,

The anode is electrically connected to the second electrode, wherein,

The interlayer insulating layer comprises a first via hole and a second via hole;

at least part of the projection area of the first shading area and the first via hole on the shading layer has an overlapping area;

and at least part of the projection area of the second shading area and the second through hole on the shading layer has an overlapping area.

2. The display panel of claim 1, wherein,

At least a portion of the first electrode is located within the first via; the first shading area is completely overlapped with the projection area of the first via hole on the shading layer, and is contacted with the first electrode through the first via hole.

3. The display panel of claim 1, wherein,

At least a portion of the second electrode is located within the second via; the second shading area is positioned outside the projection area of the first via hole on the shading layer and is contacted with the second electrode through the second via hole.

4. The display panel according to claim 1, wherein the first light shielding region and the second light shielding region are isolated from each other by a slit within the light shielding unit, and are not connected to each other.

5. The display panel of claim 4, wherein a projection of the slit onto the substrate falls entirely outside a projection area of the channel region onto the substrate.

6. The display panel of claim 4, wherein the first and second light shielding regions comprise a metal conductive material such as aluminum, molybdenum or aluminum molybdenum niobium alloy, and have a thickness of 0.20-0.25 um.

7. The display panel of claim 1, wherein the first light-shielding region and the second light-shielding region are integrally seamlessly connected.

8. The display panel of claim 6, wherein the first light shielding region is an insulating material and the second light shielding region is configured as a conductive material.

9. The display panel according to claim 8, wherein the insulating material of the first light shielding region is a metal oxide or a metal nitride, and the conductive material of the second light shielding region is a metal material such as aluminum, molybdenum or an aluminum molybdenum niobium alloy, and has a thickness of 0.20 to 0.25um.

10. A display device comprising the display panel of any one of claims 1-9.

11. A method of manufacturing a display panel, comprising:

providing a substrate base plate, and

Patterning and depositing a plurality of light shielding units forming a light shielding layer, forming a first light shielding region and a second light shielding region on the light shielding units, the second light shielding region being configured to surround the first light shielding region;

depositing a buffer layer, patterning and depositing to form an active layer, depositing a gate insulating layer, patterning and depositing to form a gate, depositing an interlayer insulating layer, patterning and depositing to form a source drain layer,

The interlayer insulating layer comprises a first via hole and a second via hole;

at least part of the projection area of the first shading area and the first via hole on the shading layer has an overlapping area;

and at least part of the projection area of the second shading area and the second through hole on the shading layer has an overlapping area.

12. The manufacturing method of the display panel according to claim 11, comprising:

when a plurality of light shielding units are formed, preparing gaps through photoresist coating, exposure, development and dry etching processes, so that the first light shielding area is surrounded by the second light shielding area and is isolated from the second light shielding area through the gaps;

The first light shielding region and the second light shielding region are both made of metal conductive materials.

13. The display panel manufacturing method according to claim 12, comprising:

Depositing a buffer layer on the light shielding unit, patterning the buffer layer by using photoresist to form an active layer, patterning the active layer to form a gate insulating layer, and patterning the gate insulating layer to form a metal gate;

the photoresist used in the process of patterning above the grid electrode is reserved, a self-alignment process is adopted to etch the grid electrode insulating layer, the edge of the active layer is exposed, and a conductor process is carried out on the edge of the active layer;

And depositing an interlayer insulating layer, patterning to form a pattern to be etched, and forming the first via hole and the second via hole through plasma dry etching.

14. The display panel manufacturing method according to claim 11, when forming a plurality of the light shielding units, comprising:

Performing exposure development process by using a half-tone mask, completely reserving photoresist of an opaque region corresponding to the second shading region, partially reserving photoresist of a semi-transparent region corresponding to the first shading region, developing to remove photoresist of the completely transparent region, and performing etching process to form a first shading layer pattern;

Ashing the residual photoresist on the light shielding layer pattern to remove the photoresist in the semi-transparent area;

oxidizing or nitriding the exposed part of the first shading area corresponding to the semi-transparent area to form an insulator;

Stripping all the photoresist to form the shading layer;

Wherein the light shielding units are configured as an integral structure, and the first light shielding area and the second light shielding area are configured as seamless connection;

The first light shielding region is configured as a metal oxide or metal nitride material, and the second light shielding region is configured as a metal material;

And depositing an interlayer insulating layer, patterning to form a pattern to be etched, and forming the first via hole and the second via hole through plasma dry etching.