CN110838451A - Semiconductor device and three-dimensional packaging method - Google Patents

Abstract

The invention provides a semiconductor device and a three-dimensional packaging method, wherein the three-dimensional packaging method comprises the following steps: s1, forming a through hole connected to the front side bonding pad on the back side of the bare chip; s2, forming a circuit connected to the bonding pad on the back side of the bare chip and the through hole; s3, forming a protective cover which closes the opening and extends to the inside of the through hole at the opening of the through hole; and S4, forming a solder mask layer covering the protective cover on the back surface of the bare chip. In the three-dimensional packaging method, after the circuit is formed and before the solder mask is formed, the protective cover for closing the opening of the through hole is formed on the back surface of the chip, and the protective cover is arranged, so that the problem that the solder mask is filled into the through hole when the solder mask is formed in the prior art, and the bonding pad on the front surface of the chip is crushed is effectively avoided.

Description

Semiconductor device and three-dimensional packaging method

technical field

The present invention relates to the technical field of semiconductors, and in particular, to a semiconductor device and a three-dimensional packaging method.

Background technique

With the development of semiconductor manufacturing technology, the integration degree of semiconductor chips has been continuously improved. However, with the gradual failure of Moore's Law, in order to meet the needs of chip miniaturization, three-dimensional packaging technology has become a key point to break through chip integration.

Compared with the two-dimensional packaging technology, the three-dimensional packaging technology is to stack the chips in the Z-axis direction. At present, the three-dimensional packaging technology based on the through silicon via (TSV) is the most promising three-dimensional packaging method. Compared with other packaging methods, TSV-based 3D packaging technology has the advantages of high integration, short interconnect spacing, and can greatly reduce the RC delay caused by packaging. MEMS) and even passive devices are integrated together to achieve a versatile system-in-package (SiP).

However, by forming TSVs on the back of the chip to connect to the front-side pads, forming a solder mask by pressing a dry film, and in reliability tests (especially temperature cycling tests), the pads at the bottom of the TSV holes will be formed. Cracks and delamination failures, especially for chips with ultra-thin pads, MEMS with special pad structures, and stack chips. Therefore, it is necessary to propose further solutions for the above-mentioned problems.

SUMMARY OF THE INVENTION

The present invention aims to provide a semiconductor device and a three-dimensional packaging method to overcome the deficiencies in the prior art.

For solving the above-mentioned technical problems, the technical scheme of the present invention is:

A three-dimensional packaging method, comprising the steps of:

S1, forming a through hole connected to the front pad on the backside of the die;

S2, forming lines connected to the pads on the backside of the die and in the through holes;

S3, forming a protective cover at the opening of the through hole that closes the opening and extends to the inside of the through hole;

S4. A solder resist layer covering the protective cover is formed on the backside of the bare chip.

As an improvement of the three-dimensional packaging method of the present invention, before forming the lines connected to the pads, the method further includes: forming an insulating layer on the backside of the bare chip and on the hole walls of the through holes.

As an improvement of the three-dimensional packaging method of the present invention, the step S3 includes:

S31 , forming a photoresist layer at the opening of the through hole on the back side of the bare chip by means of spin coating liquid glue;

S32, before the photoresist layer is cured, stand still, so that the photoresist layer overhanging the opening of the through hole extends to the inside of the through hole.

As an improvement of the three-dimensional packaging method of the present invention, the step S3 further includes:

S33, preliminarily curing the photoresist layer to form a shape after standing;

S34, removing the photoresist layer in the area other than the opening of the through hole by exposure and development;

S35, performing secondary curing and shaping on the remaining photoresist layer after exposure and development.

As an improvement of the three-dimensional packaging method of the present invention, the photoresist layer is preliminarily cured by means of soft baking, and the photoresist layer is subjected to secondary curing and shaping by means of hard baking.

As an improvement of the three-dimensional packaging method of the present invention, the materials of the protective cover and the solder resist layer are inconsistent.

For solving the above-mentioned technical problems, the technical scheme of the present invention is:

A semiconductor device, comprising: a chip, a pad, an interconnection layer, a protective cover and a solder resist layer;

The chip has a front side and a back side, the front side of the chip is provided with the pad, the back side of the chip is provided with a through hole connected to the pad, and the interconnect layer is located on the back side of the chip and is connected to the pad. hole and connected to the pad, the protective cover is fastened to the opening formed on the back of the through hole, and closes the opening, the solder resist layer is arranged on the back of the chip and covers the solder mask of the protective cover.

As an improvement of the semiconductor device of the present invention, the protective cover extends into the through hole.

As an improvement of the semiconductor device of the present invention, an insulating layer is further provided between the interconnection layer and the chip.

As an improvement of the semiconductor device of the present invention, the materials of the protective cover and the solder resist layer are inconsistent.

As an improvement of the semiconductor device of the present invention, a hollow area is further provided on the solder resist layer, and solder balls are arranged at the hollow area, and the solder balls are connected to the interconnection layer.

Compared with the prior art, the beneficial effect of the present invention is: in the three-dimensional packaging method of the present invention, after the circuit is formed and before the solder resist layer is formed, a protective cover is formed on the back of the chip to close the opening of the through hole, and by setting the protective cover This effectively avoids that when the solder resist layer is formed in the prior art, the solder resist material is filled into the through hole, thereby crushing the pad on the front side of the chip.

Description of drawings

In order to explain the embodiments of the present invention or the technical solutions in the prior art more clearly, the following briefly introduces the accompanying drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments described in the present invention. For those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

1 is a top view of a wafer having a plurality of chips thereon;

2 to 4 are process schematic diagrams in the AA ^' cross-sectional direction in FIG. 1 . specifically:

FIG. 2 is a schematic diagram of the process of suspending a photoresist layer of a certain thickness on the surface of the bare chip and the through hole;

3 is a schematic diagram of a process for extending the photoresist layer suspended at the opening of the through hole to the interior of the through hole by standing;

4 is a schematic diagram of a process for removing the photoresist layer outside the opening of the through hole by exposure and development;

5 is a schematic diagram of a process of forming a solder resist layer covering a protective cover on the backside of a bare chip, and is also a schematic structural diagram of a semiconductor device;

FIG. 6 is an electron microscope image of forming a protective cover at the opening of the through hole.

Detailed ways

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, but not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

In order to solve the problems of cracking and delamination of the pads mentioned in the background art, the present invention proposes a solder resist layer protective cover on a hole with a controllable cavity size in a vertical through-silicon hole formed by spin coating. On the basis, other processes such as spin coating, spray coating and dry film can be used to form the solder mask, which can effectively improve the damage to the pad at the bottom of the hole when forming the solder mask, and can greatly reduce the delamination of the pad in the temperature cycle test. The tensile stress effectively improves the reliability of the package.

Because, compared with filling the hole with glue, forming the protective cover can avoid the accumulation of a large amount of glue in the hole, which can avoid different materials in the hole bottom, especially glue and pad, in reliability tests such as temperature cycling. The stress caused by the CTE mismatch.

In a word, the function of the protective cover is to avoid the direct contact between other substances other than the interconnect metal and the pad at the bottom of the hole in the process and to avoid the stress caused by the local CTE mismatch in the reliability test, so as to protect the pad.

As shown in FIGS. 1 to 6 , the three-dimensional packaging method of the present invention includes the following steps:

S1, forming a through hole connected to the front pad 11 on the backside of the die 10;

S2, forming lines 14 connected to the pads 11 on the backside of the die 10 and in the through holes;

S3, forming a protective cover at the opening of the through hole that closes the opening and extends to the inside of the through hole;

S4 , forming a solder resist layer covering the protective cover on the backside of the bare chip 10 .

In addition, before forming the lines 14 connected to the pads 11 , the method further includes: forming an insulating layer 13 on the backside of the bare chip 10 and the hole walls of the through holes.

Further, in order to form the protective cover, in one embodiment, the photoresist layer 100 with a certain thickness is suspended on the surface of the bare chip 10 and the through hole by spin coating liquid glue.

Specifically, the step S3 includes:

S31 , forming a layer of photoresist layer 100 at the opening of the backside through hole of the bare chip 10 by spin coating liquid glue;

S32, before the photoresist layer 100 is cured, stand still, so that the photoresist layer 100 overhanging the opening of the through hole extends to the inside of the through hole.

Therefore, by controlling the standing time, the amount of photoresist entering the through hole can be controlled, and the size of the formed cavity can be further controlled to form a target cavity of a required size. Among them, the purpose of controlling the size of the cavity is that since the mechanism of the destruction of the pad is caused by local stress, it should be required that the cavity where the pad is located should not be filled with glue, but if the cavity is too small, it will cause The glue does not match the stress of the metal traces, which in turn transmits the stress to the underlying pads. At the same time, the formed cavity should not be too large, that is, the thickness of the protective cover or the thickness of the glue above the hole should not be too small, otherwise the bubbles in the hole may burst and the effect of water vapor cannot be blocked. Therefore, it is of great significance to realize the purpose of the present invention by controlling the standing time.

In order that the protective cover is only provided at the opening of the through hole on the back side of the chip, the step S3 further includes:

S33, preliminarily curing the photoresist layer 100 to form the morphology after standing;

S34, removing the photoresist layer 100 in areas other than the opening of the through hole by exposure and development to form a protective cover shape with a controllable shape and size;

S35 , performing secondary curing and shaping on the photoresist layer 100 remaining after exposure and development, that is, to obtain a protective cover permanently remaining at the aperture.

In one embodiment, the photoresist layer 100 is preliminarily cured by means of soft baking, and the photoresist layer 100 is subjected to secondary curing and shaping by means of hard baking.

The materials of the protective cover and the solder resist layer can be inconsistent. This arrangement is based on the consideration that the function of the formed protective cover is to prevent the material for the subsequent formation of the solder resist layer from entering the through holes, and different materials will not cause other packaging. Therefore, different materials and different process methods for forming the solder resist layer can be selected, so that the packaging method of the present invention is universal.

Finally, the three-dimensional packaging method of the present invention further includes: cutting the wafer 1 where the bare chip 10 is located to form a single package.

Based on the same inventive concept, the present invention also provides a semiconductor device.

As shown in FIG. 5 , the semiconductor device includes: a chip 10 , a pad 11 , an interconnection layer 14 , a protective cover 15 and a solder resist layer 16 .

The chip 10 has a front side and a back side, the front side of the chip 10 is provided with the pads 11 , and the back side of the chip 10 is provided with through holes connected to the pads 11 . The interconnection layer 14 is located on the backside of the chip 10 and in the through hole and connected to the pad 11 , and an insulating layer 13 is also disposed between the interconnection layer 14 and the chip 10 .

The protective cover 15 is fastened to the opening formed on the back of the through hole, and closes the opening. The solder resist layer 16 is disposed on the back of the chip 10 and covers the resistance of the protective cover 15 . Solder layer 16 . In this way, by providing the protective cover 15 , it is effectively avoided that when the solder resist layer 16 is formed in the prior art, the solder resist material is filled into the through holes, thereby crushing the pads 11 on the front side of the chip 10 .

The protective cover 15 extends into the through hole, and forms a cavity inside the through hole with the pad 11 . In this way, by controlling the length of the protective cover 15 extending into the through hole, the size of the formed cavity is further controlled, so as to obtain the target cavity of the required size.

The materials of the protective cover 15 and the solder resist layer 16 may be inconsistent. This arrangement is based on the consideration that the function of the formed protective cover is to prevent the material for forming the solder resist layer from entering the through hole, and different materials will not cause For other packaging problems, different materials and different process methods for forming the solder resist layer can be selected, so that the packaging method of the present invention is universal.

In addition, the solder resist layer 16 is further provided with a hollow area, and solder balls 17 are disposed at the hollow area, and the solder balls 17 are connected to the interconnection layer 14 .

To sum up, in the three-dimensional packaging method of the present invention, after the circuit is formed and before the solder resist layer is formed, a protective cover is formed on the back of the chip to close the opening of the through hole. When the solder mask layer is applied, the solder mask material is filled into the through hole, and then the pad on the front side of the chip is crushed.

It will be apparent to those skilled in the art that the present invention is not limited to the details of the above-described exemplary embodiments, but that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments are to be regarded in all respects as illustrative and not restrictive, and the scope of the invention is to be defined by the appended claims rather than the foregoing description, which are therefore intended to fall within the scope of the claims. All changes within the meaning and scope of the equivalents of , are included in the present invention. Any reference signs in the claims shall not be construed as limiting the involved claim.

In addition, it should be understood that although this specification is described in terms of embodiments, not each embodiment only includes an independent technical solution, and this description in the specification is only for the sake of clarity, and those skilled in the art should take the specification as a whole , the technical solutions in each embodiment can also be appropriately combined to form other implementations that can be understood by those skilled in the art.

Claims (10)

1. A three-dimensional packaging method is characterized by comprising the following steps:

s1, forming a through hole connected to the front side bonding pad on the back side of the bare chip;

s2, forming a circuit connected to the bonding pad on the back side of the bare chip and the through hole;

s3, forming a protective cover which closes the opening and extends to the inside of the through hole at the opening of the through hole;

and S4, forming a solder mask layer covering the protective cover on the back surface of the bare chip.

2. The three-dimensional packaging method according to claim 1, further comprising, before forming the wiring connected to the pad: an insulating layer is formed on the back side of the die and the walls of the vias.

3. The three-dimensional packaging method according to claim 1, wherein the step S3 includes:

s31, forming a photoresist layer at the opening of the through hole on the back of the bare chip by spin coating liquid glue;

and S32, standing the photoresist layer before the photoresist layer is solidified, so that the photoresist layer suspended at the opening of the through hole extends to the inside of the through hole.

4. The three-dimensional packaging method according to claim 3, wherein the step S3 further comprises:

s33, primarily curing the photoresist layer to form a shape after standing;

s34, removing the photoresist layer in the area except the opening of the through hole by means of exposure and development;

and S35, carrying out secondary curing and shaping on the photoresist layer left after exposure and development.

5. The three-dimensional packaging method according to claim 4, wherein the photoresist layer is primarily cured by soft baking, and the photoresist layer is secondarily cured and shaped by hard baking.

6. The three-dimensional packaging method according to any one of claims 1 to 5, wherein the protective cover and the solder resist layer are made of different materials.

7. A semiconductor device, characterized in that the semiconductor device comprises: the chip comprises a chip, a bonding pad, an interconnection layer, a protective cover and a solder mask layer;

the chip is provided with a front side and a back side, the bonding pad is arranged on the front side of the chip, a through hole communicated to the bonding pad is formed in the back side of the chip, the interconnection layer is located in the back side of the chip and the through hole and connected to the bonding pad, the protective cover is buckled at an opening formed in the back side of the through hole and seals the opening, and the solder mask is arranged on the back side of the chip and covers the solder mask of the protective cover.

8. The semiconductor device of claim 6, wherein the protective cap extends into the via.

9. The semiconductor device according to claim 6, wherein an insulating layer is further provided between the interconnect layer and the chip.

10. The semiconductor device according to any one of claims 7 to 9, wherein the protective cover and the solder resist layer are made of different materials.

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