TWI719670B - Integrated circuit package and method of manufacturing the same - Google Patents

Abstract

In an embodiment, a device includes: an integrated circuit die; an encapsulant at least partially encapsulating the integrated circuit die; a conductive via extending through the encapsulant; a redistribution structure on the encapsulant, the redistribution structure including: a metallization pattern electrically coupled to the conductive via and the integrated circuit die; a dielectric layer on the metallization pattern, the dielectric layer having a first thickness of 10 μm to 30 μm; and a first under-bump metallurgy (UBM) having a first via portion extending through the dielectric layer and a first bump portion on the dielectric layer, the first UBM being physically and electrically coupled to the metallization pattern, the first via portion having a first width, a ratio of the first thickness to the first width being from 1.33 to 1.66.

Description

Integrated circuit packaging body and manufacturing method thereof

The disclosed embodiment relates to an integrated circuit package and a manufacturing method thereof.

The semiconductor industry has experienced rapid development due to the continuous improvement of the integrated density of various electronic components (for example, transistors, diodes, resistors, capacitors, etc.). Generally, the improvement in integrated density comes from a gradual reduction in the minimum feature size, which allows more components to be integrated into a given area. As the demand for shrinking electronic components has grown, the need for smaller and more creative semiconductor die packaging technology has emerged. An example of this type of packaging system is Package-on-Package (PoP) technology. In PoP devices, the top semiconductor package is stacked on top of the bottom semiconductor package to provide a high level of integration and component density. PoP technology generally enables the production of semiconductor components with enhanced functionality and a small footprint on a printed circuit board (PCB).

The embodiment of the present disclosure provides an integrated circuit package including: an integrated circuit die; a sealing body that at least partially seals the integrated circuit die; a via hole extending through Sealing body; rewiring structure, located on the sealing body, rewiring structure including: metallization pattern, electrically coupled to the via hole and integrated circuit die; dielectric layer, located on the metallization pattern, the dielectric layer has a diameter of 10 microns to A first thickness of 30 microns; and a first under-bump metal having a first through hole portion extending through the dielectric layer and a first bump portion on the dielectric layer, the first under-bump metal is physically coupled and Electrically coupled to the metallization pattern, the first through hole portion has a first width, and the ratio of the first thickness to the first width is 1.33 to 1.66

The embodiment of the present disclosure provides a method for manufacturing an integrated circuit package, including: forming a conductive through hole extending from a carrier substrate; placing an integrated circuit die adjacent to the conductive through hole; sealing the integrated circuit die and conduction with a sealing body Through holes; deposit a first dielectric layer on the sealing body; pattern a plurality of first openings in the first dielectric layer, thereby exposing the integrated circuit die and conductive vias; in the plurality of first openings and A metallization pattern is formed along the first dielectric layer, and the metallization pattern electrically couples the via hole and the integrated circuit die; a second dielectric layer is deposited on the metallization pattern, and the second dielectric layer has a thickness of 10 μm to 30 μm. A thickness; the second opening is patterned in the second dielectric layer to expose the metallization pattern, the second opening has a first width, and the ratio of the first thickness to the first width is 1.33 to 1.66; and in the second opening A first under-bump metal is formed in and along the second dielectric layer, and the first under-bump metal is physically and electrically coupled to the metallization pattern.

The embodiment of the present disclosure provides a method for manufacturing an integrated circuit package, including: forming a via hole extending from a carrier substrate; placing an integrated circuit die adjacent to the via hole; and sealing the integrated circuit die and the via hole with a sealing body; Forming a metallization pattern to electrically couple the via and the integrated circuit die; depositing a dielectric layer on the metallization pattern; patterning a plurality of first openings in the dielectric layer to expose the landing pads of the metallization pattern, Each of the plurality of first openings has a different width; and a cover is formed over the dielectric layer The mask has a second opening exposing each of the plurality of first openings; and the plurality of first openings and the second openings are plated with under-bump metal, and the under-bumps in the plurality of first openings The multiple portions of the metal each have a first shape in a plan view, and a portion of the metal under the bump in the second opening has a second shape in a plan view, and the second shape is different from the first shape.

10A: Zone 1

10B: Zone 2

50: Integrated circuit die

52: Semiconductor substrate

54: Components

56: Interlayer dielectric

58: conductive plug

60: Internal wiring structure

62: pad

64: Passivation film

66: Die connector

68, 108, 112, 124, 128, 132, 136: Dielectric layer

100: The first package component

100A: The first package area

100B: second packaging area

102: carrier substrate

104: release layer

106: Back-side wiring structure

110, 126, 130, 134: metallization pattern

114, 140, 146: opening

116: Piercing

118: Adhesive

120: Seal body

122: Front focus on wiring structure

138: Metal under bump

138A: Through hole part

138B: bump part

142: Seed Layer

144: photoresist

148: conductive material

150, 152: conductive connector

200: The second package component

202: Base

204, 206, 304: bonding pad

208: Via

210, 210A, 210B: stacked die

212: Wire Bonding

214: Molding material

300: Package base

302: Base Core

306: Solder resist

D ₁ : Depth

D ₂ : Merging depth

T ₁ , T ₂ , T ₃ : thickness

T _C : combined thickness

W ₁ , W ₂ : average width

W _1A , W _1C : first width

W _1B , W _1D : second width

The aspects of the present invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that according to standard practices in the industry, various features are not drawn to scale. In fact, for clarity of discussion, the size of various features can be arbitrarily increased or decreased.

Figure 1 shows a cross-sectional view of an integrated circuit die according to some embodiments.

2 to 20 show cross-sectional views of intermediate steps during a process for forming a packaged component according to some embodiments.

Figures 21 and 22 illustrate the formation and implementation of element stacks according to some embodiments.

Figure 23 shows a stack of elements according to some other embodiments.

The following disclosure provides many different embodiments or examples for implementing different features of the present invention. Specific examples of components and configurations are described below to simplify the present invention. Of course, these components and configurations are only examples and are not intended to be limiting. For example, in the following description, the formation of the first feature on or on the second feature may include an embodiment in which the first feature and the second feature are formed in direct contact, and may also include additional features An embodiment may be formed between the first feature and the second feature such that the first feature and the second feature may not directly contact. In addition, the present invention may repeat graphical element symbols and/or letters in various examples. This repetition is for the purpose of simplification and clarity, and does not itself specify the relationship between the various embodiments and/or configurations discussed.

In addition, spatially relative terms such as "below", "below", "lower", "above", "upper" and similar terms can be used in this text to describe The relationship between one element or feature and another element or feature(s) as illustrated in the drawings. In addition to the orientations depicted in the drawings, spatially relative terms are intended to cover different orientations of elements in use or operation. The device can be oriented in other ways (rotated by 90 degrees or in other orientations), and the spatial relative descriptors used in this article can also be interpreted accordingly.

According to some embodiments, under-bump metallurgies (UBM) are formed for the rewiring structure, and external connectors are formed to physically and electrically couple the UBM. The UBM has a through hole portion extending through the topmost dielectric layer of the rewiring structure, and a bump portion on which an external connector is formed. The through hole portion has a small width and a large height-to-width ratio. In addition, the topmost dielectric layer has a large thickness. Forming a UBM with a large height to width ratio allows the UBM of the rewiring structure and the topmost dielectric layer to buffer mechanical stress, thereby improving the reliability of the rewiring structure during testing or operation.

FIG. 1 illustrates a cross-sectional view of an integrated circuit die 50 according to some embodiments. The integrated circuit die 50 will be packaged in subsequent processing to form an integrated circuit package. The integrated circuit die 50 may be a logic die (for example, a central processing unit (CPU), a graphics processing unit; GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, etc.), memory die (for example, dynamic random access memory (dynamic random access memory) access memory; DRAM) dies, static random access memory (SRAM) dies, etc.), power management dies (for example, power management integrated circuit (PMIC) dies) , Radio frequency (RF) die, sensor die, micro-electro-mechanical-system (MEMS) die, signal processing die (for example, digital signal processing (digital signal processing; DSP) ) Die), front-end die (for example, analog front-end (AFE) die), the like, or a combination thereof.

The integrated circuit die 50 may be formed in a wafer, and the wafer may include different device regions that are singulated in a subsequent step to form a plurality of integrated circuit die. The integrated circuit die 50 may be processed according to applicable manufacturing processes to form an integrated circuit. For example, the integrated circuit die 50 includes an active layer such as a semiconductor substrate 52 of doped silicon or undoped silicon, or a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate 52 may include other semiconductor materials, such as germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP and/or GaInAsP; or a combination thereof. Other substrates can also be used, such as a multi-layer substrate or a gradient substrate. The semiconductor substrate 52 has an active surface sometimes referred to as the front side (for example, the surface facing upward in FIG. 1) and an inactive surface sometimes referred to as the back side (for example, the downward facing surface in FIG. 1).

The element 54 may be formed at the front surface of the semiconductor substrate 52. Element 54 can These are active components (for example, transistors, diodes, etc.), capacitors, resistors, etc. An inter-layer dielectric (ILD) 56 is located above the front surface of the semiconductor substrate 52. The interlayer dielectric 56 surrounds the element 54 and can cover the element 54. The interlayer dielectric 56 may include one or more dielectric layers formed of materials such as: Phospho-Silicate Glass (PSG), Boro-Silicate Glass (BSG), Boron-Doped Phospho-Silicate Glass (BPSG), undoped Silicate Glass (USG) or the like.

The conductive plug 58 extends through the interlayer dielectric 56 to electrically and physically couple the element 54. For example, when the element 54 is a transistor, the conductive plug 58 can be coupled to the gate and source/drain regions of the transistor. The conductive plug 58 may be formed of tungsten, cobalt, nickel, copper, silver, gold, aluminum, the like, or a combination thereof. The interconnect structure 60 is located above the interlayer dielectric 56 and the conductive plug 58. The interconnect structure 60 is interconnected with the element 54 to form an integrated circuit. The interconnect structure 60 may be formed by, for example, a plurality of metallization patterns in a plurality of dielectric layers on the interlayer dielectric 56. The metallization pattern includes a plurality of metal lines and a plurality of through holes formed in one or more dielectric layers. The metallization pattern of the interconnect structure 60 is electrically coupled to the element 54 through the conductive plug 58.

The integrated circuit die 50 further includes a plurality of pads 62, such as aluminum pads, for external connection to the pads 62. The pad 62 is located on the active side of the integrated circuit die 50, such as in the interconnect structure 60 and/or on the interconnect structure 60. One or more passivation films 64 are located on the integrated circuit die 50, such as on the interconnection structure 60 and the pad 62. A plurality of openings extend through the passivation film 64 to the pad 62. A plurality of die connectors 66 such as conductive pillars (for example, formed of a metal such as copper) extend through the openings in the passivation film 64, and are physically and electrically coupled to the phase of the pad 62 Should be. The die connecting member 66 may be formed by, for example, plating or the like. The die connector 66 electrically couples the individual integrated circuits of the integrated circuit die 50.

Optionally, multiple solder regions (for example, multiple solder balls or multiple solder bumps) may be disposed on the pad 62. The solder balls can be used to perform chip probe (CP) testing on the integrated circuit die 50. A CP test can be performed on the integrated circuit die 50 to determine whether the integrated circuit die 50 is a known good die (KGD). Therefore, only the integrated circuit die 50 as a KGD that undergoes subsequent processing is packaged, and the die that fails the CP test is not packaged. After the test, the solder area can be removed in subsequent processing steps.

The dielectric layer 68 may (or may not) be located on the active side of the integrated circuit die 50, such as on the passivation film 64 and the die connector 66. The dielectric layer 68 laterally seals the die connector 66, and the dielectric layer 68 is laterally connected to the integrated circuit die 50. First, the dielectric layer 68 can bury the die connection member 66 such that the topmost surface of the dielectric layer 68 is above the topmost surface of the die connection member 66. In some embodiments, where the solder area is disposed on the die connector 66, the dielectric layer 68 can also bury the solder area. Alternatively, the solder area can be removed before the dielectric layer 68 is formed.

The dielectric layer 68 may be a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB) or the like; nitride, such as silicon nitride or the like ; Oxide, such as silicon oxide, PSG, BSG, BPSG or the like; the like, or a combination thereof. The dielectric layer 68 can be formed, for example, by spin coating, lamination, chemical vapor deposition (CVD) or the like. In some embodiments, during the formation of the integrated circuit die 50, the die connector 66 is exposed through the dielectric layer 68. In some embodiments, the die connector 66 remains buried and is It is exposed during the subsequent process of packaging the integrated circuit die 50. The exposure of the die connector 66 can remove any solder regions that may be present on the die connector 66.

In some embodiments, the integrated circuit die 50 is a stacked device including a plurality of semiconductor substrates 52. For example, the integrated circuit die 50 may be a memory device including a plurality of memory dies, such as a hybrid memory cube (HMC) module, a high bandwidth memory (HBM) module Or similar. In such embodiments, the integrated circuit die 50 includes a plurality of semiconductor substrates 52 interconnected by through-substrate vias (TSV). Each of the semiconductor substrates 52 may (or may not) have an interconnect structure 60.

2 to 20 illustrate cross-sectional views of intermediate steps during the process for forming the first package assembly 100 according to some embodiments. A first packaging area 100A and a second packaging area 100B are shown, and one or more of the integrated circuit die 50 is packaged to form an integrated circuit package in each of the packaging area 100A and the packaging area 100B . The integrated circuit package can also be called an integrated fan-out (InFO) package.

In FIG. 2, a carrier substrate 102 is provided, and a release layer 104 is formed on the carrier substrate 102. The carrier substrate 102 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 102 can be a wafer, so that multiple packages can be formed on the carrier substrate 102 at the same time. The release layer 104 may be formed of a polymer material, and the polymer material together with the carrier substrate 102 may be removed from the overlying structure to be formed in a subsequent step. In some embodiments, the release layer 104 is an epoxy-based heat release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 104 may be an ultraviolet (ultra-violet; UV) adhesive that loses its adhesive properties when exposed to UV light. glue. The release layer 104 may be applied and cured in a liquid form, may be a laminated film laminated to the carrier substrate 102, or may be the like. The top surface of the release layer 104 can be leveled, and the top surface can have a high degree of planarity.

In FIG. 3, the back side heavy wiring structure 106 may be formed on the release layer 104. In the illustrated embodiment, the backside redistribution structure 106 includes a dielectric layer 108, a metallization pattern 110 (sometimes referred to as multiple redistribution layers or multiple redistributions), and a dielectric layer 112. The back-side-weighted wiring structure 106 is selected as appropriate. In some embodiments, a dielectric layer without a metallization pattern is formed on the release layer 104 instead of the backside heavy wiring structure 106.

The dielectric layer 108 may be formed on the release layer 104. The bottom surface of the dielectric layer 108 may be in contact with the top surface of the release layer 104. In some embodiments, the dielectric layer 108 is formed of a polymer such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, the dielectric layer 108 is formed of: nitride, such as silicon nitride; oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped Phosphosilicate glass (BPSG) or similar; or similar. The dielectric layer 108 may be formed by any acceptable deposition process such as spin coating, CVD, lamination, the like, or a combination thereof.

The metallization pattern 110 is formed on the dielectric layer 108. As an example of forming the metallization pattern 110, a seed layer is formed on the dielectric layer 108. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. For example, physical vapor deposition (PVD) or the like can be used to form the seed layer. Then a photoresist is formed on the seed layer and the photoresist is patterned. The photoresist can be formed by spin coating or similar processes, and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 110. Through patterning, form A plurality of openings through the photoresist to expose the seed layer. The conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as: electro plating or electroless plating or the like. The conductive material may include metals, such as copper, titanium, tungsten, aluminum, or the like. Subsequently, the photoresist and the part of the seed layer where no conductive material is formed are removed. The photoresist can be removed by an acceptable ashing or stripping process, such as the use of oxygen plasma or the like. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. The seed layer and the rest of the conductive material form the metallization pattern 110.

The dielectric layer 112 may be formed on the metallization pattern 110 and the dielectric layer 108. In some embodiments, the dielectric layer 112 is formed of a polymer, which may be a photosensitive material that can be patterned using a lithography mask, such as PBO, polyimide, BCB, or the like. In other embodiments, the dielectric layer 112 is formed of: nitride, such as silicon nitride; oxide, such as silicon oxide, PSG, BSG, BPSG; or the like. The dielectric layer 112 may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer 112 is then patterned to form a plurality of openings 114 to expose portions of the metallization pattern 110. The patterning can be formed by an acceptable process, such as by exposing the dielectric layer 112 to light when the dielectric layer 112 is a photosensitive material, or by using an etching method such as anisotropic etching. If the dielectric layer 112 is a photosensitive material, the dielectric layer 112 can be developed after exposure.

It should be understood that the back-side heavy wiring structure 106 may include any number of dielectric layers and metallization patterns. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed above can be repeated. The metallization pattern may include a plurality of wires and a plurality of via holes. Metallization can be formed in the opening of the underlying dielectric layer during the formation of the metallization pattern The patterned seed layer and conductive material form via holes. The vias can thus interconnect and electrically couple various wires.

In FIG. 4, a plurality of through holes 116 may be respectively formed in the opening 114 and extend away from the top dielectric layer (for example, the dielectric layer 112) of the backside redistribution structure 106. The perforation 116 is optional and can be omitted. For example, in an embodiment where the back-side re-wiring structure 106 is omitted, the through hole 116 may (or may not) be omitted. As an example of forming the through hole 116, a seed layer is formed on the backside redistribution structure 106, such as the dielectric layer 112 and the portion of the metallization pattern 110 exposed by the opening 114. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sub-layers formed of different materials. In one embodiment, the seed layer includes a titanium layer and a copper layer above the titanium layer. For example, PVD or the like can be used to form the seed layer. A photoresist is formed on the seed layer and the photoresist is patterned. The photoresist can be formed by spin coating or similar processes, and can be exposed to light for patterning. The pattern of the photoresist corresponds to the via hole. The patterning forms a plurality of openings through the photoresist to expose the seed layer. The conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as: electroplating or electroless plating or the like. The conductive material may include metals, such as copper, titanium, tungsten, aluminum, or the like. Remove the part of the photoresist and the seed layer where no conductive material is formed. The photoresist can be removed by an acceptable ashing or stripping process, such as the use of oxygen plasma or the like. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. The seed layer and the rest of the conductive material form a through hole 116.

In FIG. 5, the integrated circuit die 50 is adhered to the dielectric layer 112 by the adhesive 118. The required type and number of integrated circuit dies 50 are adhered to each of the packaging area 100A and the packaging area 100B. In the illustrated embodiment, the first integrated body is included The circuit die 50A and the plurality of integrated circuit die 50 of the second integrated circuit die 50B are pasted so as to be adjacent to each other. The first integrated circuit die 50A may be a logic element, such as a central processing unit (CPU), a graphics processing unit (GPU), a system-on-a-chip (SoC), a microcontroller, or the like. The second integrated circuit die 50B can be a memory device, such as dynamic random access memory (DRAM) die, static random access memory (SRAM) die, hybrid memory cube (HMC) module, high bandwidth Memory (HBM) module or similar. In some embodiments, the integrated circuit die 50A and the integrated circuit die 50B may be the same type of die, such as SoC die. The first integrated circuit die 50A and the second integrated circuit die 50B may be formed in the same process of technology node, or may be formed in the process of different technology nodes. For example, the first integrated circuit die 50A may belong to a later (advanced) process node than the second integrated circuit die 50B. The integrated circuit die 50A and the integrated circuit die 50B may have different sizes (for example, different heights and/or surface areas), or may have the same size (for example, the same height and/or surface areas). In particular, when the integrated circuit die 50A and the integrated circuit die 50B include components with a large footprint, such as SoC, the space available for the through holes 116 in the package area 100A and the package area 100B may be limited. When the space available for the through holes 116 in the packaging area 100A and the packaging area 100B is limited, the use of the back-side rewiring structure 106 can achieve an improved interconnection configuration.

The adhesive 118 is located on the back sides of the integrated circuit die 50A and the integrated circuit die 50B, and adheres the integrated circuit die 50A and the integrated circuit die 50B to the backside rewiring structure 106, such as to the dielectric层112。 Layer 112. The adhesive 118 can be any suitable adhesive, epoxy resin, die attach film (DAF) or the like. The adhesive 118 may be applied to the back sides of the integrated circuit die 50A and the integrated circuit die 50B, or may be applied to the surface of the carrier substrate 102. For example, Before singulation to separate the integrated circuit die 50A and the integrated circuit die 50B, the adhesive 118 may be applied to the back sides of the integrated circuit die 50A and the integrated circuit die 50B.

In FIG. 6, the sealing body 120 is formed on and surrounds various components. After being formed, the sealing body 120 seals the through hole 116, the integrated circuit die 50A, and the integrated circuit die 50B. The sealing body 120 may be a molding compound, epoxy resin, or the like. The sealing body 120 may be applied by compression molding, transfer molding, or the like, and may be formed on the carrier substrate 102 so that the through holes 116 and/or the integrated circuit die 50A and the integrated circuit The circuit die 50B is buried or covered by it. If present, the sealing body 120 is further formed in the space between the integrated circuit die 50A and the integrated circuit die 50B. The sealing body 120 may be applied through a liquid or semi-liquid form and then cured.

In FIG. 7, a planarization process is performed on the sealing body 120 to expose the through hole 116 and the die connecting member 66. The planarization process can also remove the material of the through hole 116, the dielectric layer 68, and/or the die connecting member 66 until the die connecting member 66 and the through hole 116 are exposed. After the planarization process, the through hole 116, the die connecting member 66, the dielectric layer 68, and the top surface of the sealing body 120 are coplanar. The planarization process can be, for example, chemical-mechanical polish (CMP), polishing process, or the like. In some embodiments, for example, if the through hole 116 and the die connecting member 66 are exposed, the planarization may be omitted.

In FIGS. 8 to 11, the front-focused wiring structure 122 (see FIG. 11) is formed above the sealing body 120, the through hole 116, the integrated circuit die 50A, and the integrated circuit die 50B. The front-focused wiring structure 122 includes a plurality of dielectric layers, such as a dielectric layer 124, a dielectric layer 128, a dielectric layer 132, and a dielectric layer 136; and a plurality of metallization patterns, for example Such as metallization pattern 126, metallization pattern 130 and metallization pattern 134. The metallization pattern can also be referred to as a rewiring layer or rewiring. The front-focused wiring structure 122 is shown as an example with three metallization pattern layers. More or fewer dielectric layers and metallization patterns can be formed in the front-focused wiring structure 122. If fewer dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be omitted. If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed below can be repeated.

In FIG. 8, the dielectric layer 124 is deposited on the sealing body 120, the through hole 116 and the die connecting member 66. In some embodiments, the dielectric layer 124 is formed of a photosensitive material such as PBO, polyimide, BCB, or the like, and the dielectric layer 124 may be patterned using a lithography mask. The dielectric layer 124 may be formed by spin coating, lamination, CVD, the like, or a combination thereof. The dielectric layer 124 is then patterned. Through the patterning, a plurality of openings are formed to expose the through holes 116 and the plurality of parts of the die connecting member 66. It can be patterned by an acceptable process, such as by exposing the dielectric layer 124 to light when the dielectric layer 124 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 124 is a photosensitive material, the dielectric layer 124 can be developed after exposure.

Then, the metallization pattern 126 is formed. The metallization pattern 126 includes a plurality of circuit portions (also referred to as wires) on the main surface of the dielectric layer 124 and extending along the main surface of the dielectric layer 124. The metallization pattern 126 further includes a plurality of through hole portions (also referred to as vias) extending through the dielectric layer 124 to physically and electrically couple the through holes 116, the integrated circuit die 50A, and the integrated circuit die 50B. As an example of forming the metallization pattern 126, a seed layer is formed above the dielectric layer 124 and in an opening extending through the dielectric layer 124. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. Can be formed using, for example, PVD or the like Seed layer. Then a photoresist is formed on the seed layer and the photoresist is patterned. The photoresist can be formed by spin coating or similar processes, and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 126. Through patterning, a plurality of openings through the photoresist are formed to expose the seed layer. The conductive material is then formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating such as: electroplating or electroless plating or the like. The conductive material may include metals, such as copper, titanium, tungsten, aluminum, or the like. The combination of the conductive material and the underlying portion of the seed layer forms the metallization pattern 126. The part of the photoresist and the seed layer where no conductive material is formed is removed. The photoresist can be removed by an acceptable ashing or stripping process, such as the use of oxygen plasma or the like. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as by wet etching or dry etching.

In FIG. 9, the dielectric layer 128 is deposited on the metallization pattern 126 and the dielectric layer 124. The dielectric layer 128 may be formed in a manner similar to the dielectric layer 124, and may be formed of a material similar to the dielectric layer 124.

Then, the metallization pattern 130 is formed. The metallization pattern 130 includes a plurality of circuit portions on the main surface of the dielectric layer 128 and extending along the main surface of the dielectric layer. The metallization pattern 130 further includes a plurality of via portions extending through the dielectric layer 128 to physically and electrically couple the metallization pattern 126. The metallization pattern 130 may be formed in a similar manner to the metallization pattern 126 and similar materials. In some embodiments, the metallization pattern 130 has a different size from the metallization pattern 126. For example, the wires and/or vias of the metallization pattern 130 may be wider or thicker than the wires and/or vias of the metallization pattern 126. In addition, the metallization pattern 130 may be formed through a larger pitch than the metallization pattern 126.

In FIG. 10, a dielectric layer 132 is deposited on the metallization pattern 130 and the dielectric layer 128 on. The dielectric layer 132 may be formed in a manner similar to the dielectric layer 124 and may be formed of a material similar to the dielectric layer 124.

Then, the metallization pattern 134 is formed. The metallization pattern 134 includes a plurality of circuit portions on the main surface of the dielectric layer 132 and extending along the main surface of the dielectric layer. The metallization pattern 134 further includes a plurality of via portions extending through the dielectric layer 132 to physically and electrically couple the metallization pattern 130. The metallization pattern 134 can be formed in a similar manner to the metallization pattern 126 and similar materials. The metallization pattern 134 is the topmost metallization pattern of the front-focused wiring structure 122. In this way, all the intermediate metallization patterns (for example, the metallization pattern 126 and the metallization pattern 130) of the front-focused wiring structure 122 are disposed between the metallization pattern 134 and the integrated circuit die 50A and the integrated circuit die 50B. In some embodiments, the metallization pattern 134 has a different size from the metallization pattern 126 and the metallization pattern 130. For example, the wires and/or vias of the metallization pattern 134 may be wider or thicker than the wires and/or vias of the metallization pattern 126 and the metallization pattern 130. In addition, the metallization pattern 134 may be formed through a larger pitch than the metallization pattern 130.

In FIG. 11, the dielectric layer 136 is deposited on the metallization pattern 134 and the dielectric layer 132. The dielectric layer 136 may be formed in a similar manner to the dielectric layer 124, and may be formed of a material similar to the dielectric layer 124. The dielectric layer 136 is the top dielectric layer of the front-focused wiring structure 122. In this way, all the metallization patterns (for example, the metallization pattern 126, the metallization pattern 130, and the metallization pattern 134) of the front-focused wiring structure 122 are disposed on the dielectric layer 136 and the integrated circuit die 50A and the integrated circuit die 50B between. In addition, all the intermediate dielectric layers (for example, the dielectric layer 124, the dielectric layer 128, and the dielectric layer 132) of the front-focused wiring structure 122 are arranged on the dielectric layer 136 and the integrated circuit die 50A and the integrated circuit die. Between 50B.

In FIG. 12, a plurality of under-bump metals 138 are formed to be externally connected to the front-focused wiring structure 122. The under-bump metal 138 has a bump portion extending on and along the main surface of the dielectric layer 136, and has a metallization pattern 134 extending through the dielectric layer 136 to physically and electrically couple The through hole part. Thus, the under-bump metal 138 is electrically coupled to the through hole 116, the integrated circuit die 50A, and the integrated circuit die 50B. The under-bump metal 138 may be formed in one of several processes or a combination of several processes.

13A-13C illustrate a method of forming the under-bump metal 138 according to some embodiments. The formation of the single-bump metal 138 is illustrated in the detailed view of the area of the first package component 100. It should be understood that some details are omitted or enlarged for clarity. In addition, multiple under-bump metals 138 may be formed at the same time.

In FIG. 13A, the dielectric layer 136 is patterned to form an opening 140 to expose a portion of the metallization pattern 134. The patterning can be performed by an acceptable process, such as by exposing the dielectric layer 136 to light when the dielectric layer 136 is a photosensitive material, or by etching using, for example, anisotropic etching. If the dielectric layer 136 is a photosensitive material, the dielectric layer 136 can be developed after exposure. The opening 140 has a small average width W ₁ . In some embodiments, width W ₁ of between about 20 microns to about 25 microns, such as about 25 microns. The small width W _{1 of the} opening 140 reduces the amount of contact between the metallization pattern 134 and the under-bump metal 138. In other words, the under-bump metal 138 contacts the smaller landing pad of the metallization pattern 134. The amount of metallization patterns 134 that can be used for signal wiring can therefore be increased.

The dielectric layer 136 has a large thickness, and thus the opening 140 has a large depth D ₁ . The depth D _{1 is} greater than the thickness of the middle dielectric layer of the front-focused wiring structure 122. In some embodiments, the depth D ₁ is at least about 7 microns, such as in the range of about 10 microns to about 30 microns, such as about 15 microns. When the current focus is on attaching the wiring structure 122 to another substrate (discussed further below), the large thickness of the dielectric layer 136 can help reduce the mechanical stress exerted on the metallization pattern 126, the metallization pattern 130, and the metallization pattern 134 . In particular, because the dielectric layer 136 is the top dielectric layer of the front-side redistribution structure 122, the large thickness allows the dielectric layer 136 to buffer the mechanical properties that can be applied to the middle dielectric layer of the front-side redistribution structure 122 in other ways. stress. Therefore, cracking and peeling in the front-focused wiring structure 122 can be avoided. In an experiment, with a depth D _{1 of} about 15 microns, the mechanical stress between the dielectric layer 136 and the metallization pattern 134 is reduced by about 23%, wherein no further cracking occurs during post-processing and stress testing.

In FIG. 13B, the seed layer 142 is formed above the dielectric layer 136 and in the opening 140. In some embodiments, the seed layer 142 is a metal layer, and the metal layer may be a single layer or a composite layer including multiple sub-layers formed of different materials. In some embodiments, the seed layer 142 includes a titanium layer and a copper layer above the titanium layer. The seed layer 142 may be formed using, for example, PVD or the like. Then, a photoresist 144 is formed on the seed layer 142 and the photoresist 144 is patterned. The photoresist 144 can be formed by spin coating or the like. _{In some embodiments, the photoresist 144 is formed to have a thickness T 2} ranging from about 10 microns to about 100 microns, such as about 72 microns. The photoresist 144 may then be exposed to light for patterning. The pattern of the photoresist 144 corresponds to the under bump metal 138. Through patterning, an opening 146 passing through the photoresist 144 is formed to expose the seed layer 142. After the above formation, the opening 140 and the opening 146 have a combined depth D ₂ . In some embodiments, the merge depth D _{2 is in the} range of about 5 microns to about 90 microns, such as about 35 microns.

In FIG. 13C, a conductive material 148 is formed in the opening 146 of the photoresist 144 and on the exposed portion of the seed layer 142. The conductive material 148 may be formed by plating such as: electroplating or electroless plating or the like. The conductive material 148 may include gold Genera, such as copper, titanium, tungsten, aluminum or similar. Subsequently, the photoresist 144 and the portion of the seed layer 142 where the conductive material 148 is not formed are removed. The photoresist 144 can be removed by an acceptable ashing or stripping process, such as the use of oxygen plasma or the like. Once the photoresist 144 is removed, the exposed portion of the seed layer 142 is removed, such as by using an acceptable etching process, such as by wet etching or dry etching. The remaining part of the seed layer 142 and the conductive material 148 forms the under-bump metal 138. In embodiments where the under-bump metal 138 is formed in different ways, more photoresist 144 and patterning steps can be utilized.

After the above formation, the through hole portion 138A of the under-bump metal 138 has a thickness T ₁ , and the thickness T ₁ is equal to the depth D _{1 of the} opening 140. The ratio of the thickness T ₁ to the width W ₁ may be referred to as the aspect ratio of the through hole portion 138A of the under-bump metal 138. In some embodiments, the aspect ratio of the opening 140 is in the range of about 1.33 to about 1.66. In an experiment, the aspect ratio is in the range of about 1.33 to about 1.66, and the mechanical stress applied to the metallization pattern 134 is reduced by about 14%. In addition, in some embodiments, the metallization pattern 134 has a thickness T ₃ ranging from about 0.8 micrometers to about 4 micrometers. In some embodiments, _{the ratio of thickness T 1} to thickness T ₃ is at least 6.

In addition, after the above formation, the bump portion 138B of the under-bump metal 138 has a thickness T _{2 greater than the thickness T 1} . In some embodiments, the thickness T _{2 is in the} range of about 10 microns to about 40 microns, such as about 30 microns. Such a thickness T ₂ can also help reduce the mechanical stress exerted on the metallization pattern 134. In an experiment, a thickness T _{2 of} about 30 microns reduces the mechanical stress exerted on the metallization pattern 134 by about 10%. The ratio of the thickness T ₂ to the thickness T _{1 is large.} In some embodiments, _{the ratio of thickness T 2} to thickness T ₁ is at least 1.5, such as in the range of about 1.5 to about 2.33.

In addition, after the above formation, the through hole portion 138A of the under-bump metal 138 has the same width W ₁ as the opening 140. The bump portion 138B of the under bump metal 138 has a small average width W ₂ . In some embodiments, the width W ₂ is at least 50 microns, such as in the range of about 70 microns to about 105 microns. In an experiment, the width W _{2 of} about 82 microns reduces the mechanical stress exerted on the metallization pattern 134 by about 10%. The width W _{2 is} greater than the width W ₁ . The small average width W ₂ allows the distance between the under bump metal 138 adjacent to each other to increase. The risk of solder bridging (solder bridging) between the under-bump metal 138 due to the subsequently formed conductive connections can therefore be reduced. The ratio of the width W ₂ to the width W _{1 is large.} In some embodiments, _{the ratio of width W 2} to width W ₁ is at least 2.5, such as in the range of about 2.5 to about 3.6. In addition, after the above formation, the under-bump metal 138 has a combined thickness T _C , which is the sum of the thickness T ₁ and the thickness T _2. In some embodiments, the combined thickness T _C ranges from about 20 microns to about 70 microns. The ratio of the combined thickness T _C to the width W _{1 is large.} In some embodiments, _{the ratio of the combined thickness T C} to the width W ₁ is at least 0.2, such as in the range of about 0.2 to about 3.3. In one experiment, a width W of about 15 microns thickness T _C of the combined composition ₁ and about 50 microns to mechanical stress exerted on the metallized pattern 134 is reduced by about 15%.

As noted above, the various values and ratios of the under-bump metal 138 allow the mechanical reliability of the front-focused wiring structure 122 to be enhanced. In an experiment, the combination of the aspect ratio of the opening 140 is in the range of about 1.33 to about 1.66, _{the ratio of the thickness T 1} to the thickness T ₃ is in the range of about 3.5 to about 10, and the ratio of the thickness T ₂ to the thickness T ₁ The ratio is in the range of about 1.5 to about 2.33, allowing the under-bump metal 138 to undergo more than 2000 thermal stress tests without component failure.

FIG. 14 illustrates the under-bump metal 138 according to some other embodiments. A detailed view of the first area 10A and the second area 10B of the first package component 100 shows a plurality of under-bump metals 138. It should be understood that some details are omitted or enlarged for clarity. In this embodiment, the bump portion 138B of the under bump metal 138 has the same width W ₂ and thickness T _{2 in} both the first region 10A and the second region 10B. In addition, the through hole portion 138A of the under-bump metal 138 has the same thickness T _{1 in} both the first region 10A and the second region 10B. However, the through hole portion 138A of the under-bump metal 138 has different widths in the first region 10A and the second region 10B. For example, the through hole portion 138A of the under bump metal 138 has a first width W _1A in the first region 10A, and the through hole portion 138A of the under bump metal 138 has a second width W _{1B in the second region 10B} . The width W _1A and the width W _1B differ by a relatively large amount. In some embodiments, _{the difference between the width W 1A} and the width W _1B is at least 5 microns, such as in the range of about 25 microns to about 45 microns. The narrower width of the through hole portion is formed in the area under higher mechanical stress. For example, when the mechanical stress of the first zone 10A is higher than the mechanical stress of the second zone 10B, the width W _{1A is} smaller than the width W _1B .

FIG. 15 illustrates the under-bump metal 138 according to some other embodiments. The single under-bump metal 138 is shown in the detailed view of the area of the first package assembly 100. It should be understood that some details are omitted or enlarged for clarity of illustration. In addition, multiple under-bump metals 138 may be formed at the same time. In this embodiment, the under-bump metal 138 has a plurality of through hole portions 138A, and each of the plurality of through hole portions 138A has the same width W ₁ . Each of the plurality of through hole portions 138A of a given under-bump metal 138 contacts the same landing pad in the metallization pattern 134. The under-bump metal 138 may have any number of through hole portions 138A, such as a number in the range of 2 to 4. The additional via portion 138A can help buffer mechanical stress that may be imposed on the middle metallization pattern of the front-focused wiring structure 122 in other ways. Cracking and peeling in the front-focused wiring structure 122 can therefore be avoided.

FIG. 16 illustrates the under-bump metal 138 according to some other embodiments. The single under-bump metal 138 is shown in the detailed view of the area of the first package assembly 100. It should be understood that some details are omitted or enlarged for clarity of illustration. In addition, multiple under-bump metals 138 may be formed at the same time. In this embodiment, the under-bump metal 138 has a plurality of through hole portions 138A, each of which has a different width. For example, the under-bump metal 138 may have a first _{through hole portion with a first width W 1C} and a second through hole portion with a second width W _1D . The width W _1C and the width W _1D may be different. In some embodiments, _{the difference between the width W 1C} and the width W _1D is at least 5 microns, such as in the range of about 25 microns to about 45 microns.

FIGS. 17A to 17O are top views of the under-bump metal 138 according to the embodiment of FIGS. 15 and 16. The through hole portion 138A and the bump portion 138B of the under-bump metal 138 may have several possible shapes in a top view. In addition, the through hole portion 138A and the bump portion 138B of the under-bump metal 138 may have the same shape in the top view, or may have different shapes in the top view. The through hole portion 138A may have a circular shape (see FIGS. 17A to 17E), a quadrilateral/square shape (see FIGS. 17F to 17J), and/or an octagonal shape (see FIGS. 17K to 17O). A single under-bump metal 138 may include a plurality of through hole portions 138A of different shapes. Similarly, the bump portion 138B may have a circular shape (see FIGS. 17A, 17F, and 17K), an oval shape (see FIGS. 17B, 17G, and 17L), and an octagonal shape (see FIGS. 17C, 17H). And Fig. 17M), hexagonal shape (see Fig. 17D, Fig. 17I and Fig. 17N) and/or quadrilateral/square shape (see Fig. 17E, Fig. 17J and Fig. 17O). In addition, the under-bump metal 138 having bump portions 138B of different shapes can be combined on the same package.

In FIG. 18, a plurality of conductive connections 150 are formed on the under bump metal 138, respectively. The conductive connector 150 can be a ball grid array (BGA) connector, solder ball, metal pillar, or controlled collapse chip connection (controlled collapse chip). connection; C4) bumps, microp bumps, bumps formed by electroless nickel-electroless palladium-immersion gold technique (ENEPIG) or the like. The conductive connection member 150 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive connection member 150 is formed by first forming a solder layer through evaporation, electroplating, printing, solder transfer, bumping, or the like. After the solder layer has been formed on the structure, reflow can be performed to mold the material into the desired bump shape. In another embodiment, the conductive connection member 150 includes a metal pillar (such as a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillar may not have solder and have substantially vertical sidewalls. In some embodiments, the metal cap layer is formed on top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by a plating process.

In FIG. 19, carrier substrate stripping is performed to separate (or "peel") the carrier substrate 102 from the backside redistribution wiring structure 106 (eg, the dielectric layer 108). According to some embodiments, the peeling method includes emitting light, such as laser light or UV light, to the release layer 104 so that the release layer 104 is decomposed under the heat of the light, and the carrier substrate 102 is removed. Then turn the above structure over and place it on a tape.

In FIG. 20, a plurality of conductive connections 152 are formed to extend through the dielectric layer 108 to contact the metallization pattern 110. A plurality of openings are formed through the dielectric layer 108 to expose portions of the metallization pattern 110. The opening can be formed using, for example, laser drilling, etching, or the like. The conductive connection 152 is formed in the opening. In some embodiments, the conductive connector 152 includes solder and is formed in a solder dipping process. In some embodiments, the conductive connection member 152 includes such as solder paste, silver Paste or similar conductive paste, and is dispensed during the printing process. In some embodiments, the conductive connector 152 is formed in a manner similar to the conductive connector 150, and may be formed of a material similar to the conductive connector 150.

Figures 21 and 22 illustrate the formation and implementation of element stacks according to some embodiments. The component stack is formed by the integrated circuit package formed in the first package assembly 100. The device stack can also be referred to as a package on package (PoP) structure. Since the PoP structure includes an integrated fan-out (InFO) package, it can also be referred to as an InFO-PoP structure.

In FIG. 21, a plurality of second packaging components 200 are coupled to the first packaging component 100. One of the plurality of second packaging components 200 is coupled to one of the packaging area 100A and the packaging area 100B to form an integrated circuit element stack in each area of the first packaging component 100.

The second package component 200 includes a substrate 202 and one or more stacked dies 210 (including a stacked die 210A and a stacked die 210B) coupled to the substrate 202. Although a set of stacked dies 210 (including stacked dies 210A and stacked dies 210B) is shown, in other embodiments, a plurality of stacked dies 210 (each having one or more stacked dies) may be arranged side by side Thereby coupling to the same surface of the substrate 202. The substrate 202 may be made of semiconductor materials such as silicon, germanium, diamond, or the like. In some embodiments, compound materials can also be used, such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphate, gallium indium phosphide, combinations of these, and the like By. In addition, the substrate 202 may be a silicon on insulating layer (SOI) substrate. Generally, the SOI substrate includes a semiconductor material layer, such as epitaxial silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI) or a combination thereof. In an alternative embodiment, the substrate 202 is based on insulation such as a glass fiber reinforced resin core. Insulating core. An example core material is glass fiber resin, such as FR4. Alternatives to core materials include bismaleimide-triazine (BT) resin, or alternatively, other printed circuit board (PCB) materials or films. A build-up film such as Ajinomoto build-up film (ABF) or other laminates may also be used for the substrate 202.

The substrate 202 may include active devices and passive devices (not shown). The structural and functional requirements for the design of the second package assembly 200 can be generated by using various elements such as transistors, capacitors, resistors, combinations of these, and the like. The element can be formed using any suitable method.

The substrate 202 may also include a plurality of metallization layers (not shown) and a plurality of via holes 208. The metallization layer can be formed on the active device and the passive device, and is designed to connect various devices to form functional circuitry. The metallization layer may be composed of multiple alternating layers of dielectric (for example, low-k dielectric material) and conductive material (for example, copper), and multiple through holes interconnecting the conductive material layer, and it may pass through any suitable It is formed by a process (such as deposition, damascene, dual damascene, or the like). In some embodiments, the substrate 202 contains substantially no active devices and passive devices.

The substrate 202 may have a plurality of bonding pads 204 on the first side of the substrate 202 to be coupled to the stacked die 210, and a plurality of bonding pads 206 on the second side of the substrate 202 to be coupled to the conductive connections 152, the substrate The second side of 202 is opposite to the first side. In some embodiments, the bonding pad 204 and the bonding pad 206 are formed by forming a plurality of recesses in a dielectric layer (not shown) on the first side and the second side of the substrate 202. The recess may be formed to allow the bonding pad 204 and the bonding pad 206 to be embedded in the dielectric layer. In other embodiments, the recess is omitted because the bonding pad 204 and the bonding pad 206 can be formed on the dielectric layer. In some embodiments, the bonding pad 204 and the bonding pad 206 include A thin seed layer made of copper, titanium, nickel, gold, palladium, the like or a combination thereof. The conductive material of the bonding pad 204 and the bonding pad 206 can be deposited over the thin seed layer. The conductive material can be formed by an electrochemical plating process, an electroless plating process, CVD, atomic layer deposition (ALD), PVD, the like, or a combination thereof. In one embodiment, the conductive material of the bonding pad 204 and the bonding pad 206 is copper, tungsten, aluminum, silver, gold, the like, or a combination thereof.

In one embodiment, the bonding pad 204 and the bonding pad 206 are under bump metal including three conductive material layers (such as a titanium layer, a copper layer, and a nickel layer). Other materials and film configurations, such as chromium/chromium-copper alloy/copper/gold configuration, titanium/titanium tungsten/copper configuration, or copper/nickel/gold configuration can also be used to form bonding pads 204 and bonding垫206. Any suitable material or material layer that can be used for the bonding pad 204 and the bonding pad 206 is also completely included in the scope of the current application. In some embodiments, a plurality of vias 208 extend through the substrate 202 and couple at least one of the bonding pads 204 to at least one of the bonding pads 206.

In the illustrated embodiment, although the stacked die 210 is coupled to the substrate 202 by wire bonds 212, other connections, such as conductive bumps, may be used. In one embodiment, the stacked die 210 is a stacked memory die. For example, the stacked die 210 may be a memory die such as a low-power (LP) double data rate (DDR) memory module, such as LPDDR1, LPDDR2, LPDDR3, LPDDR4, or the like Memory module.

The stacked die 210 and the wire bond 212 can be sealed by the molding material 214. The molding material 214 may be molded on the stacked die 210 and the wire bond 212 using compression molding, for example. In some embodiments, the molding material 214 is a molding compound, polymer, epoxy, silica filler material, the like, or a combination thereof. Executable The chemical process is used to cure the molding material 214; the curing process can be thermal curing, UV curing, the like, or a combination thereof.

In some embodiments, the stacked die 210 and the wire bond 212 are buried in the molding material 214, and after curing the molding material 214, a planarization step such as grinding is performed to remove the excess part of the molding material 214 and is The second packaging component 200 provides a substantially flat surface.

After the second packaging component 200 is formed, the second packaging component 200 is mechanically and electrically bonded to the first packaging component 100 by means of the conductive connectors 152, the bonding pads 206, and the backside heavy wiring structure 106. In some embodiments, the stacked die 210 can be coupled to the wire bond 212, the bond pad 204 and the bond pad 206, the via 208, the conductive connector 152, the back-side heavy wiring structure 106, the through hole 116, and the front-side heavy wiring structure 122. Integrated circuit die 50A and integrated circuit die 50B.

In some embodiments, a solder resist is formed on the opposite side of the substrate 202 and the stacked die 210. The conductive connectors 152 may be disposed in a plurality of openings in the solder resist to electrically and mechanically couple to conductive features in the substrate 202 (eg, bond pads 206). The solder resist can be used to protect multiple areas of the substrate 202 from external damage.

In some embodiments, the conductive connector 152 may be formed with epoxy flux before its reflow, wherein at least some of the epoxy flux in the epoxy flux is in the second package assembly 200 It is retained after being attached to the first packaging component 100.

In some embodiments, an underfill is formed between the first packaging component 100 and the second packaging component 200 so as to surround the conductive connector 152. The underfill can reduce stress and protect joints created by the reflow of the conductive connector 152. bottom The partial filler may be formed by a capillary flow process after attaching the second packaging component 200, or may be formed by a suitable deposition method before attaching the second packaging component 200. In the embodiment where the epoxy resin flux is formed, the epoxy resin flux may serve as an underfill.

In FIG. 22, the singulation process is performed by sawing along, for example, a scribe line region between the first packaging area 100A and the second packaging area 100B. By sawing, the first packaging area 100A and the second packaging area 100B are singulated. The resulting singulated device stack comes from one of the first packaging area 100A or the second packaging area 100B. In some embodiments, the singulation process is performed after the second packaging component 200 is coupled to the first packaging component 100. In other embodiments, the singulation process is performed before the second package component 200 is coupled to the first package component 100, such as after the carrier substrate 102 is peeled off and the conductive connector 152 is formed.

Each singulated first packaging component 100 is then mounted to the packaging substrate 300 using conductive connectors 150. The package substrate 300 includes a substrate core 302 and a plurality of bonding pads 304 on the substrate core 302. The substrate core 302 may be made of a semiconductor material such as silicon, germanium, diamond, or the like. Alternatively, compound materials such as silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide, silicon germanium carbide, gallium arsenide phosphate, gallium indium phosphide, combinations of these, and the like can also be used. In addition, the substrate core 302 may be an SOI substrate. Generally, the SOI substrate includes a layer of semiconductor material, such as epitaxial silicon, germanium, silicon germanium, SOI, SGOI, or a combination thereof. In an alternative embodiment, the base core 302 is based on an insulating core such as a glass fiber reinforced resin core. An example of the core material is glass fiber resin, such as FR4. Alternatives to core materials include bismaleimide triazine (BT) resin, or other PCB materials or film layers. Cumulative films such as ABF or other laminates can also be used as the base core 302.

The substrate core 302 may include active components and passive components (not shown). As those with ordinary knowledge in the art understand, the structural and functional requirements for the element stack design can also be generated by using various elements such as transistors, capacitors, resistors, combinations of these, and the like. The element can be formed using any suitable method.

The base core 302 may also include a plurality of metallization layers and a plurality of through holes (not shown), wherein the bonding pad 304 is physically and/or electrically coupled to the metallization layer and the through holes. The metallization layer can be formed on the active device and the passive device, and is designed to connect various devices to form a functional circuit. The metallization layer can be composed of alternating layers of dielectric (e.g., low-k dielectric material) and conductive material (e.g., copper) and via holes connecting the conductive material layer, and can be formed by any suitable process (such as deposition). , Mosaic, double mosaic or the like). In some embodiments, the substrate core 302 contains substantially no active components and passive components.

In some embodiments, the conductive connector 150 is reflowed to bond the first package component 100 to the bonding pad 304. The conductive connector 150 electrically and/or physically couples the package substrate 300 (the metallization layer included in the substrate core 302) to the first package component 100. In some embodiments, the solder resist 306 is formed on the substrate core 302. The conductive connector 150 may be disposed in a plurality of openings in the solder resist 306 to be electrically and mechanically coupled to the bonding pad 304. The solder resist 306 can be used to protect multiple areas of the substrate core 302 from external damage.

The conductive connector 150 may be formed with an epoxy resin flux before its reflow, wherein at least some of the epoxy resin part of the epoxy resin flux is retained after the first package component 100 is attached to the package substrate 300. The remaining epoxy resin part can act as an underfill to reduce the stress caused by reflowing the conductive connection 150 and protect the joints caused by the reflow of the conductive connection 150. In some embodiments, the underfill 308 may be formed between the first packaging component 100 and the packaging substrate 300 and surround the conductive connector 150. The underfill 308 may be formed by a capillary flow process after bonding the first package component 100, or may be formed by a suitable deposition method before bonding the first package component 100.

In some embodiments, passive components (for example, surface mount devices (SMD), not shown) may also be attached to the first package component 100 (for example, attached to the under-bump metal 138) or It is attached to the package substrate 300 (for example, attached to the bonding pad 304). For example, the passive element can be bonded to the same surface of the first packaging component 100 or the packaging substrate 300 and the conductive connector 150. The passive component may be attached to the packaging component 100 before the first packaging component 100 is mounted on the packaging substrate 300, or may be attached to the packaging substrate 300 before or after the first packaging component 100 is mounted on the packaging substrate 300.

It should be understood that the first package assembly 100 may be implemented in other device stacks. For example, a PoP structure is shown, but the first package assembly 100 can also be implemented in a flip chip ball grid array (FCBGA) package. In such embodiments, the first packaging component 100 is mounted to a substrate such as the packaging substrate 300, but the second packaging component 200 is omitted. Alternatively, a lid or a heat spreader may be attached to the first package component 100. When the second package assembly 200 is omitted, the back-side re-wiring structure 106 and the through hole 116 can also be omitted.

It can also include other characteristics and processes. For example, a test structure may be included to facilitate verification testing of 3D packages or 3DIC components. The test structure may include, for example, test pads formed in the redistribution layer or on the substrate, which allow testing of 3D packages or 3DIC, the use of probes and/or probe cards, and the like. Verification tests can be performed on the intermediate structure and the final structure. In addition, the structure and method disclosed in this article can be combined The test method of intermediate verification of the die is used to improve the yield and reduce the cost.

Figure 23 illustrates a stack of elements according to some other embodiments. In this embodiment, the back-side re-wiring structure 106, the through hole 116, and the second packaging component 200 are omitted. In addition, the first package assembly 100 includes a first integrated circuit die 50A (for example, a logic device) and a plurality of second integrated circuit die 50B (for example, a memory device). In this embodiment, the second integrated circuit die 50B is a stacked device including a plurality of semiconductor substrates 52 and interconnect structures 60, such as a memory cube.

The above-described embodiment can achieve a number of advantages. The first packaging component 100 and the packaging substrate 300 may have unmatched coefficients of thermal expansion (CTE). This difference value can be large. For example, in some embodiments, the first packaging component 100 may have a CTE in the range of 10 ppm to 30 ppm, and the packaging substrate 300 may have a CTE in the range of 3 ppm to 17 ppm. A large CTE difference value will generate mechanical stress on the front-focused wiring structure 122 during testing or operation. The increased thickness of the dielectric layer 136 allows the dielectric layer 136 to buffer mechanical stress. Cracking and peeling in the front-focused wiring structure 122 can therefore be avoided, and the average width of the under-bump metal 138 can be reduced. By reducing the average width of the under-bump metal 138, the amount of contact between the metallization pattern 134 and the under-bump metal 138 can be reduced. The amount of metallization patterns 134 that can be used for signal wiring can therefore be increased. Reducing the width of the under-bump metal 138 also reduces the risk of solder bridging between the under-bump metal 138 through the conductive connector 150.

In one embodiment, a component includes: an integrated circuit die; a sealing body at least partially sealing the integrated circuit die; a via hole extending through the sealing body; a redistribution structure located on the sealing body, a redistribution structure Including: metallization pattern, electrically coupled to the via hole and integrated circuit die; dielectric layer, located on the metallization pattern, the dielectric layer has 10 A first thickness of 30 microns to 30 microns; and a first under-bump metal having a first through hole portion extending through the dielectric layer and a first bump portion on the dielectric layer, a first under-bump metal entity Coupled and electrically coupled to the metallization pattern, the first through hole portion has a first width, and the ratio of the first thickness to the first width is 1.33 to 1.66.

In some embodiments of the above elements, the first bump portion has a second width, and the ratio of the second width to the first width is at least 2.5. In some embodiments of the aforementioned element, the first width is 20 to 25 microns. In some embodiments of the above element, the second width is 70 to 105 microns. In some embodiments of the aforementioned element, the first bump portion has a second thickness, and the ratio of the second thickness to the first thickness is at least 1.5. In some embodiments of the above element, the second thickness is 10 to 40 microns. In some embodiments of the aforementioned element, the metallization pattern has a third thickness, and the ratio of the first thickness to the third thickness is at least 6. In some embodiments of the above element, the third thickness is 0.8 micrometers to 4 micrometers. In some embodiments of the above device, the rewiring structure further includes: a second under-bump metal having a second through hole portion extending through the dielectric layer and a second bump portion on the dielectric layer, the second The metal under bump is physically and electrically coupled to the metallization pattern, and the second through hole portion has a second width, and the second width is greater than the first width by at least 5 microns. In some embodiments of the above device, the first under-bump metal further has a second through hole portion extending through the dielectric layer, and a part of the dielectric layer is between the first through hole portion and the second through hole portion And the first through hole portion and the second through hole portion of the first under-bump metal contact the same landing pad in the metallization pattern. In some embodiments of the aforementioned elements, the second through hole portion has the same width as the first through hole portion. In some embodiments of the above element, the second through hole portion has a second width, and the second width is greater than the first width by at least 5 micrometers. In some embodiments of the above-mentioned elements, the first bump portion, the first through hole portion and the second portion of the metal under the first bump The through hole portion has the same shape in a plan view. In some embodiments of the above-mentioned elements, the first bump portion of the first under-bump metal has a first shape in a top view, and the first through hole portion and the second through-hole portion of the first under bump metal are in a top view Has a second shape, and the first shape is different from the second shape.

In one embodiment, a method includes: forming a conductive through hole extending from a carrier substrate; placing an integrated circuit die adjacent to the conductive through hole; sealing the integrated circuit die and the conductive through hole with a sealing body; Depositing a first dielectric layer on top; patterning a plurality of first openings in the first dielectric layer, thereby exposing the integrated circuit die and conductive vias; in the plurality of first openings and along the first dielectric layer Form a metallization pattern, the metallization pattern electrically couples the via hole and the integrated circuit die; deposit a second dielectric layer on the metallization pattern, the second dielectric layer has a first thickness of 10 to 30 microns; the patterned first Two openings are in the second dielectric layer to expose the metallization pattern, the second opening has a first width, and the ratio of the first thickness to the first width is 1.33 to 1.66; and in the second opening and along the second dielectric The electrical layer forms a first under-bump metal, and the first under-bump metal is physically and electrically coupled to the metallization pattern.

In some embodiments, the method further includes: patterning the third opening in the second dielectric layer to expose the metallization pattern, and forming the first under-bump metal further includes forming a first opening in the third opening. Metal under bump. In some embodiments, the method further includes: patterning the third opening on the second dielectric layer to expose the metallization pattern, the third opening has a second width, and the second width is smaller than the first width; and A second under-bump metal is formed in the three openings and along the second dielectric layer, and the second under-bump metal is physically and electrically coupled to the metallization pattern.

In one embodiment, a method includes: forming a via hole extending from a carrier substrate; placing an integrated circuit die adjacent to the via hole; and sealing the integrated circuit die with a sealing body Particles and vias; forming a metallization pattern to electrically couple the vias and integrated circuit die; depositing a dielectric layer on the metallization pattern; patterning a plurality of first openings in the dielectric layer to expose the metallization pattern In the landing pad, each of the plurality of first openings has a different width; and forming a mask over the dielectric layer, the mask having a second opening exposing each of the plurality of first openings; and The plurality of first openings and the second openings are plated with under-bump metal, the plurality of portions of the under-bump metal in the plurality of first openings each have a first shape in a plan view, and the under-bump metal in the second opening A part of has a second shape in plan view, and the second shape is different from the first shape.

In some embodiments of the above method, the dielectric layer has a first thickness of 10 μm to 30 μm. In some embodiments of the above method, the ratio of the first thickness to the width of each of the plurality of first openings is 1.33 to 1.66.

The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the aspects of the present invention. Those skilled in the art should understand that they can easily use the present invention as a basis for designing or modifying other manufacturing processes and structures for achieving the same purpose and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that these equivalent structures do not depart from the spirit and scope of the present invention, and those skilled in the art can make various changes in this text without departing from the spirit and scope of the present invention. Replacement and change.

60: Internal wiring structure

62: pad

64: Passivation film

66: Die connector

68, 124, 128, 132, 136: Dielectric layer

126, 130, 134: Metallization pattern

122: Front focus on wiring structure

138: Metal under bump

138A: Through hole part

138B: bump part

142: Seed Layer

148: conductive material

T ₁ , T ₂ , T ₃ : thickness

T _C : combined thickness

W ₁ , W ₂ : average width

Claims (10)

An integrated circuit package includes: an integrated circuit die; a sealing body at least partially sealing the integrated circuit die; a via hole extending through the sealing body; and a redistribution structure located in the sealing body On the body, the redistribution structure includes: a metallization pattern electrically coupled to the via hole and the integrated circuit die; a dielectric layer on the metallization pattern, the dielectric layer having a thickness of 10 microns To a first thickness of 30 microns; and a first under-bump metal having a first through hole portion extending through the dielectric layer and a first bump portion on the dielectric layer, the first The under-bump metal is physically and electrically coupled to the metallization pattern, the first through hole portion has a first width, and the ratio of the first thickness to the first width is 1.33 to 1.66. The integrated circuit package according to claim 1, wherein the first bump portion has a second width, and the ratio of the second width to the first width is at least 2.5. The integrated circuit package according to claim 1, wherein the first bump portion has a second thickness, and the ratio of the second thickness to the first thickness is at least 1.5. The integrated circuit package according to claim 3, wherein the metallization pattern has a third thickness, and the ratio of the first thickness to the third thickness is at least 6. The integrated circuit package as described in claim 1, wherein the rewiring structure further includes: a second under-bump metal having a second through hole portion extending through the dielectric layer and The second bump portion on the dielectric layer, the second under bump metal is physically and electrically coupled to the metallization pattern, the second through hole portion has a second width, and the second width It is at least 5 microns larger than the first width. The integrated circuit package according to the first item of the patent application, wherein the first under-bump metal further has a second through hole portion extending through the dielectric layer, and a part of the dielectric layer intervenes Between the first through hole portion and the second through hole portion, and the first through hole portion and the second through hole portion of the first under-bump metal contact the metallization pattern The same landing pad. A method for manufacturing an integrated circuit package includes: forming a via hole extending from a carrier substrate; placing an integrated circuit die adjacent to the via hole; and sealing the integrated circuit die and the via hole with a sealing body Depositing a first dielectric layer on the sealing body; patterning a plurality of first openings in the first dielectric layer, the plurality of first openings exposing the integrated circuit die and the conduction Holes; in the plurality of first openings and along the first dielectric layer to form a metallization pattern, the metallization pattern electrically couples the via hole and the integrated circuit die; in the metallization A second dielectric layer is deposited on the pattern, the second dielectric layer has a first thickness of 10 to 30 microns; a second opening is patterned in the second dielectric layer, and the second opening exposes the The metallization pattern, the second opening has a first width, and the first thickness is the same as the The ratio of the first width is 1.33 to 1.66; and a first under-bump metal is formed in the second opening and along the second dielectric layer, and the first under-bump metal is physically and electrically coupled to the述metallized pattern. The manufacturing method described in item 7 of the scope of patent application further includes: patterning a third opening in the second dielectric layer, the third opening exposing the metallization pattern, and the first protrusion is formed therein. The under-bump metal further includes forming the first under-bump metal in the third opening. According to the manufacturing method described in item 7 of the scope of the patent application, further comprising: patterning a third opening in the second dielectric layer, the third opening exposing the metallization pattern, and the third opening has a Two widths, the second width is smaller than the first width; and a second under-bump metal is formed in the third opening and along the second dielectric layer, and the second under-bump metal is physically coupled And electrically coupled to the metallization pattern. A method for manufacturing an integrated circuit package includes: forming a via hole extending from a carrier substrate; placing an integrated circuit die adjacent to the via hole; and sealing the integrated circuit die and the via hole with a sealing body Forming a metallization pattern that electrically couples the via hole and the integrated circuit die; depositing a dielectric layer on the metallization pattern; patterning a plurality of first openings in the dielectric layer, the A plurality of first openings expose the landing pads of the metallization pattern, each of the plurality of first openings has a different width; a mask is formed above the dielectric layer, and the mask has exposed The second opening of each of the plurality of first openings; and Plating an under-bump metal in the plurality of first openings and the second opening, and a plurality of portions of the under-bump metal in the plurality of first openings each have a first shape in a plan view, A portion of the under-bump metal in the second opening has a second shape in the top view, and the second shape is different from the first shape.

Images