CN110828376A - Method for forming semiconductor device - Google Patents

Abstract

The present disclosure provides a method for forming a semiconductor device. In the process of forming a fin transistor structure and a corresponding conductive connection structure on a semiconductor substrate in a first region in an embodiment of the present disclosure, multiplexing at least part of a second region A process of forming a fin transistor structure and a corresponding conductive connection structure to form at least one capacitor structure. Therefore, a high-density capacitor structure is formed while the fin transistor structure is formed, the process process is reduced, and the production efficiency is improved. The capacitor structure formed by the method of the embodiment of the present disclosure has the advantages of small volume and large capacitance.

Description

A method of forming a semiconductor device

technical field

The present invention relates to the technical field of semiconductors, and in particular, to a method for forming a semiconductor device.

Background technique

A capacitor is a device that holds electric charge. Any two conductors that are insulated from each other and spaced in close proximity form a capacitor. In integrated circuits, capacitors have always taken up considerable chip area throughout the circuit layout due to the limited capacitance per unit area. However, with the improvement of the degree of integration of electronic products, there is an urgent need for a high-density capacitor that occupies a small area and has a large capacitance.

SUMMARY OF THE INVENTION

In view of this, the present disclosure provides a method for forming a semiconductor device to increase the capacitance of a capacitor in an integrated circuit and reduce the area of the capacitor.

The method for forming a semiconductor device provided by the present disclosure includes:

providing a semiconductor substrate on which a plurality of fins are formed;

in the process of forming the fin transistor structure and the corresponding conductive connection structure on the semiconductor substrate in the first region, multiplexing at least part of the process in the second region to form at least one capacitor structure;

Wherein, multiplexing at least part of the process to form at least one capacitor structure includes at least one of the following processes:

The first capacitor structure is formed by multiplexing the process of forming the source-drain region and the gate conductive structure on the fin;

forming the second capacitance structure by multiplexing the processes of forming the source-drain conductive structure and forming the conductive pattern on the gate;

forming a third capacitor structure by multiplexing the process of forming the first metal layer;

forming a fourth capacitor structure by multiplexing the process of forming the second metal layer; and

The fifth capacitor structure is formed by multiplexing the process of forming the third metal layer.

Further, forming the first capacitor structure by multiplexing the process of forming the source-drain region and the gate conductive structure on the fin includes:

When the source and drain regions are formed in the first region, ion implantation is performed on the corresponding positions of the fins in the second region to form the first electrode of the first capacitor structure;

When the gate dielectric layer is formed in the first region, the first dielectric layer is formed at the first position of the fin in the second region;

While the gate conductive structure is formed in the first region, a first conductive structure is formed across the fin to form the second electrode of the first capacitive structure.

Further, forming the second capacitance structure by multiplexing the processes of forming the source-drain conductive structure and forming the conductive pattern on the gate includes:

When the source-drain conductive structure is formed in the first region and the conductive pattern on the gate is formed, second conductive structures parallel to each other are formed in the second region;

A part of the second conductive structure is used as the first electrode of the second capacitor structure, and another part of the second conductive structure is used as the second electrode of the second capacitor structure.

Further, forming the third capacitor structure by multiplexing the process of forming the first metal layer includes:

When the first metal layer is formed in the first region, a plurality of third conductive structures arranged in parallel are formed in the second region;

Wherein, a part of the third conductive structure is used as the first electrode of the third capacitance structure, and another part of the second conductive structure is used as the second electrode of the third capacitance structure.

Further, forming the fourth capacitor structure by multiplexing the process of forming the second metal layer includes:

When the second metal layer is formed in the first region, a plurality of fourth conductive structures arranged in parallel are formed in the second region;

A part of the fourth conductive structure is used as the first electrode of the fourth capacitance structure, and another part of the second conductive structure is used as the second electrode of the fourth capacitance structure.

Further, forming the fifth capacitor structure by multiplexing the process of forming the third metal layer includes:

When the third metal layer is formed in the first region, a plurality of fifth conductive structures arranged in parallel are formed in the second region;

A part of the fifth conductive structure is used as the first electrode of the fifth capacitor structure, and another part of the fifth conductive structure is used as the second electrode of the fifth capacitor structure.

Further, multiplexing at least part of the process includes:

forming the first capacitor structure by multiplexing the process of forming the source-drain region and the gate conductive structure on the fin; and

forming the second capacitance structure by multiplexing the processes of forming the source-drain conductive structure and forming the conductive pattern on the gate;

Wherein, forming the first capacitor structure by multiplexing the process of forming the source-drain region and the gate conductive structure on the fin includes:

When the source and drain regions are formed in the first region, ion implantation is performed on the corresponding positions of the fins in the second region to form the first electrode of the first capacitor structure;

while forming the gate dielectric layer in the first region, forming a first dielectric layer at the first position of the fin in the second region; and

while forming the gate conductive structure in the first region, forming a first conductive structure across the fin to form a second electrode of the first capacitance structure;

Forming the second capacitance structure by multiplexing the processes of forming the source-drain conductive structure and forming the conductive pattern on the gate includes:

When the source-drain conductive structure and the conductive pattern on the gate are formed in the first region, a plurality of second conductive structures arranged in parallel and not connected to each other are formed in the second region;

Wherein, a part of the second conductive structure is electrically connected to the second position of the fin to serve as the first electrode of the second capacitance structure, and another part of the second conductive structure is electrically connected to the first conductive structure across the fin The structure is used as the second electrode of the second capacitance structure.

Further, multiplexing at least part of the process includes:

forming the second capacitance structure by multiplexing the processes of forming the source-drain conductive structure and forming the conductive pattern on the gate; and

forming a third capacitor structure by multiplexing the process of forming the first metal layer;

Wherein, forming the second capacitance structure by multiplexing the processes of forming the source-drain conductive structure and forming the conductive pattern on the gate includes:

When the source-drain conductive structure is formed in the first region and the conductive pattern on the gate is formed, a plurality of second conductive structures arranged in parallel are formed in the second region;

Wherein, a part of the second conductive structure is used as the first electrode of the second capacitance structure, and another part of the second conductive structure is used as the second electrode of the second capacitance structure;

Wherein, forming the third capacitor structure by multiplexing the process of forming the first metal layer includes:

When the first metal layer is formed in the first region, a plurality of third conductive structures arranged in parallel are formed in the second region, and the first through holes and the second through holes in the lower layers of the third conductive structures;

wherein a part of the third conductive structure is electrically connected as the first electrode of the third capacitance structure to the second conductive structure as the first electrode of the second capacitance structure through the first through hole, and

Another part of the third conductive structure as the second electrode of the third capacitance structure is electrically connected to the second conductive structure as the second electrode of the second capacitance structure through a second through hole.

Further, multiplexing at least part of the process includes:

forming a third capacitor structure by multiplexing the process of forming the first metal layer; and

forming a fourth capacitor structure by multiplexing the process of forming the second metal layer;

Wherein, forming the third capacitor structure by multiplexing the process of forming the first metal layer includes:

When the first metal layer is formed in the first region, a plurality of third conductive structures arranged in parallel are formed in the second region;

Wherein, a part of the third conductive structure is used as the first electrode of the third capacitance structure, and another part of the third conductive structure is used as the second electrode of the third capacitance structure;

Wherein, forming the fourth capacitor structure by multiplexing the process of forming the second metal layer includes:

When the second metal layer is formed in the first region, a plurality of fourth conductive structures arranged in parallel are formed in the second region, and third through holes and fourth through holes in the lower layer of the fourth conductive structure;

wherein a part of the fourth conductive structure is electrically connected as the first electrode of the fourth capacitance structure to the third conductive structure as the first electrode of the third capacitance structure through a third through hole, and

A part of the fourth conductive structure as the second electrode of the fourth capacitance structure is electrically connected to the third conductive structure as the second electrode of the third capacitance structure through a fourth through hole.

Further, multiplexing at least part of the process includes:

forming a fourth capacitor structure by multiplexing the process of forming the second metal layer; and

A fifth capacitor structure is formed by multiplexing the process of forming the third metal layer;

Wherein, forming the fourth capacitor structure by multiplexing the process of forming the second metal layer includes:

When the second metal layer is formed in the first region, a plurality of fourth conductive structures arranged in parallel are formed in the second region;

Wherein, a part of the fourth conductive structure is used as the first electrode of the fourth capacitance structure, and another part of the fourth conductive structure is used as the second electrode of the fourth capacitance structure;

Wherein, forming the fifth capacitor structure by multiplexing the process of forming the third metal layer includes:

When the third metal layer is formed in the first region, a plurality of fifth conductive structures arranged in parallel are formed in the second region, and fifth through holes and sixth through holes are formed in the lower layer of the fifth conductive structure;

wherein a part of the fifth conductive structure is electrically connected as the first electrode of the fifth capacitance structure to the fourth conductive structure as the first electrode of the fourth capacitance structure through a fifth through hole, and

A part of the fifth conductive structure as the second electrode of the fifth capacitance structure is electrically connected to the fourth conductive structure as the second electrode of the fourth capacitance structure through a sixth through hole.

Further, the first conductive structure is perpendicular to the fin.

Further, the second conductive structure is perpendicular to the first conductive structure.

Further, the third conductive structure is perpendicular to the second conductive structure, and the first through hole is located at the intersection of the first electrode of the second capacitor structure and the first electrode of the third capacitor structure. The two through holes are located at the intersection of the second electrode of the second capacitor structure and the second electrode of the third capacitor structure.

Further, the fourth conductive structure is perpendicular to the third conductive structure, and the third through hole is located at the intersection of the first electrode of the third capacitor structure and the first electrode of the fourth capacitor structure. The four through holes are located at the intersection of the second electrode of the third capacitor structure and the second electrode of the fourth capacitor structure.

Further, the fifth conductive structure is perpendicular to the fourth conductive structure, and the fifth through hole is located at the intersection of the first electrode of the fifth capacitor structure and the first electrode of the fourth capacitor structure. The six through holes are located at the intersection of the second electrode of the fifth capacitor structure and the second electrode of the fourth capacitor structure.

In the process of forming the fin transistor structure and the corresponding conductive connection structure on the semiconductor substrate in the first region according to the embodiment of the present disclosure, at least part of the fin transistor structure and the corresponding conductive connection structure are multiplexed in the second region. process to form at least one capacitive structure. Therefore, a high-density capacitor structure is formed while the fin transistor structure is formed, the process process is reduced, and the production efficiency is improved. The capacitor structure formed by the method of the embodiment of the present disclosure has the advantages of small volume and large capacitance.

Description of drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

FIG. 1 is a flowchart of a method for forming a semiconductor device according to an embodiment of the present disclosure;

FIG. 2 is a flowchart of a method for forming first to fifth capacitor structures in parallel with each other according to an embodiment of the present disclosure;

3-24 are three-dimensional structural diagrams and schematic cross-sectional views formed by each step of the method for forming a semiconductor device according to an embodiment of the present disclosure.

Detailed ways

The present invention is described below based on examples, but the present invention is not limited to these examples only. In the following detailed description of the invention, some specific details are described in detail. The present invention can be fully understood by those skilled in the art without the description of these detailed parts. Well-known methods, procedures, procedures, components and circuits have not been described in detail in order to avoid obscuring the essence of the present invention.

Furthermore, those of ordinary skill in the art will appreciate that the drawings provided herein are for illustrative purposes and are not necessarily drawn to scale.

Unless clearly required by the context, words such as "including", "comprising" and the like throughout the specification and claims should be construed in an inclusive rather than an exclusive or exhaustive sense; that is, "including but not limited to" meaning. In the description of the present invention, unless otherwise specified, "multilayer" means two or more layers.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on the other elements or layers Layers may be on, adjacent to, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. Floor. For ease of description, spatially relative terms such as "under", "below", "under", "over", "on" and the like may be used herein to describe an element as shown in the figures The relationship between a feature or feature and another element or feature(s). It should be understood that spatially relative terms are intended to summarize different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "under" can encompass both an orientation of above and below. The device may assume other orientations (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein are interpreted accordingly.

Meanwhile, it should be understood that in the following description, "circuit" refers to a conductive loop formed by at least one element or sub-circuit through electrical connection or electromagnetic connection. When an element or circuit is referred to as being "connected" to another element or an element/circuit is "connected" between two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements Connections may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is meant that there are no intervening elements present. "Across" means that, if the dummy gate structure straddles the fin, it means that the dummy gate structure covers part of the top surface and part of the sidewall surface of the fin, and the dummy gate structure and the fin have a crossed positional relationship, and the dummy gate The height of the structure is greater than the height of the fins. "Parallel" means parallel or substantially parallel. "Vertical" means vertical or substantially vertical.

1 is a flowchart of a method for forming a semiconductor device according to an embodiment of the present disclosure. Referring to FIG. 1 , the method for forming a semiconductor device according to an embodiment of the present disclosure includes the following steps:

Step S100, providing a semiconductor substrate. Wherein, a plurality of fins are formed on the semiconductor substrate. The plurality of fins have a parallel or substantially parallel positional relationship with each other.

Step S200 , in the process of forming the fin transistor structure and the corresponding conductive connection structure on the semiconductor substrate in the first region, reuse at least part of the process in the second region to form at least one capacitor structure.

Wherein, multiplexing at least part of the process includes forming a first capacitor structure by multiplexing a process of forming a source-drain region and a gate conductive structure on the fin; The process of forming the conductive pattern forms a second capacitance structure; the process of forming the first metal layer is formed by multiplexing to form a third capacitance structure; the process of forming the second metal layer is formed by multiplexing to form a fourth capacitance structure; The process of the third metal layer forms at least one of the fifth capacitor structures.

In some optional implementations, only one step in the above process may be multiplexed to form an independent capacitor structure. In other optional implementation manners, multiple steps in the above process may also be reused to form a plurality of mutually independent capacitor structures. In still some optional implementation manners, multiple adjacent steps in the above-mentioned process can also be reused to form a plurality of interconnected capacitor structures, thereby obtaining a high-density capacitor with a multi-layer structure. When a capacitor with a larger capacitance value needs to be formed, all the steps can be reused, and the first to fifth capacitance structures are formed in parallel with each other. The following description will be given by taking as an example an implementation manner of forming the first to fifth capacitor structures in parallel with each other while forming the fin transistor structure and the conductive connection.

3 is a top view of a semiconductor substrate according to an embodiment of the present disclosure. Referring to FIG. 3 , in step S100 , a semiconductor substrate 10 is provided on which a plurality of fins 11 are parallel to each other. The semiconductor substrate 10 includes a first region 1 and a second region 2 . A fin transistor structure and a corresponding conductive connection structure will be formed on the semiconductor substrate 10 of the first region 1 . In this embodiment, at least part of the process of forming the fin transistor structure and the corresponding conductive connection structure on the semiconductor substrate 10 in the first region is reused in the second region 2 to form each capacitor structure. FIG. 4 is a partial three-dimensional perspective view of the second area 2 , and FIG. 5 is a top view of the second area 2 .

The fins 11 may be formed by patterning the semiconductor substrate 10 , or a fin material layer may be formed on the semiconductor substrate 10 , and then the fin material layer may be patterned to form the fins 11 . As an example, the semiconductor substrate 10 is patterned to form the fins 11 .

The semiconductor substrate 10 provided in step S100 may be a silicon single crystal substrate, a germanium single crystal substrate or a silicon germanium single crystal substrate. Alternatively, the semiconductor substrate 10 may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-germanium-on-insulator (S-SiGeOI), a silicon-germanium-on-insulator (SiGeOI), an insulator Germanium-on-Germanium (GeOI), epitaxial layer-on-silicon substrate or compound semiconductor substrate. The compound semiconductor substrate includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysprosium. Several structures such as epitaxial interface layers or strained layers may also be formed on the surface of the semiconductor substrate 10 to improve the electrical performance of the semiconductor device. An isolation region (not shown in the figure) is formed in the semiconductor substrate 10 . As examples, the isolation regions are shallow trench isolation (STI) regions or localized silicon oxide (LOCOS) isolation regions. The isolation regions may divide the semiconductor substrate 10 into several active regions, etc. For simplicity, the isolation regions are not shown in the figures.

In step S200, during the process of forming the fin transistor structure and the corresponding conductive connection structure on the semiconductor substrate in the first region 1, at least part of the process is multiplexed in the second region 2 to form at least one capacitor structure.

Wherein, multiplexing at least part of the process includes forming a first capacitor structure by multiplexing a process of forming a source-drain region and a gate conductive structure on the fin; The process of forming the conductive pattern forms a second capacitance structure; the process of forming the first metal layer is formed by multiplexing to form a third capacitance structure; the process of forming the second metal layer is formed by multiplexing to form a fourth capacitance structure; The process of the third metal layer forms at least one of the fifth capacitor structures.

In this embodiment, all the processes of forming fin transistors on the semiconductor substrate are multiplexed to form capacitors with small area and large capacitance on the semiconductor substrate. FIG. 2 is a flowchart of a method for forming the first to fifth capacitor structures connected in parallel with each other in this embodiment. Referring to FIG. 2 , the method for forming the first to fifth capacitor structures in parallel with each other includes the following steps:

Step S210 , forming a first capacitor structure by multiplexing the process of forming the source-drain region and the gate conductive structure on the fin.

Step S220 , forming a second capacitor structure by multiplexing the processes of forming a source-drain conductive structure and forming a conductive pattern on the gate.

Step S230 , forming a third capacitor structure by multiplexing the process of forming the first metal layer.

Step S240 , forming a fourth capacitor structure by multiplexing the process of forming the second metal layer.

Step S250 , forming a fifth capacitor structure by multiplexing the process of forming the third metal layer.

In step S210 , a first capacitor structure is formed by multiplexing the process of forming source-drain regions and gate conductive structures on the fins 11 . Forming a fin transistor on the fin portion 11 in the first region includes forming a dummy gate, forming source and drain regions by ion implantation, depositing a dielectric layer, removing the dummy gate, and forming a gate dielectric layer and a gate conductive structure at the original dummy gate.

FIG. 6 is a schematic diagram of the fins 11 in the second region 2 after ion implantation. Referring to FIG. 6 , while the source and drain regions are formed on the fins 11 in the first region 1, each fin 11 in the second region 2 is subjected to Ion Implantation. The ion implantation region may be the entire fin portion or a part of the fin portion, and it is preferable to perform ion implantation on the entire fin portion to form the fin portion 11a. FIG. 7 is a top view after forming the first conductive structure 12 , FIG. 8 is a schematic cross-sectional view taken along line X of FIG. 7 , and FIG. 9 is a schematic cross-sectional view taken along line Y of FIG. 7 . 7-9, while the gate dielectric layer is formed in the first region 1, the first dielectric layer is formed at the first position of the fin in the second region 2; while the gate conductive structure is formed in the first region, A first conductive structure 12 is formed 11 across the fin, the first conductive structure 12 covers part of the sidewall and the upper surface of the fin 11a, and is perpendicular to the fin 11a, and the height of the first conductive structure 12 is greater than the height of the fin 11a . The first dielectric layer (not marked in the figure) is located under the first conductive structure 12 and isolates the first conductive structure 12 and the fins 11a. The fin portion 11a after ion implantation is equivalent to a conductor and can be used as the first electrode of the first capacitor structure, the first conductive structure 12 is used as the second electrode of the first capacitor structure, and the gap between the fin portion 11a and the first conductive structure 12 The first dielectric layer acts as an insulator for the first capacitor structure.

In step S220, a second capacitor structure is formed by multiplexing the processes of forming the source-drain conductive structure and forming the conductive pattern on the gate. Forming the fin transistor in the first region further includes forming a source-drain conductive structure and a gate conductive structure on the gate electrode and the source-drain region, so as to reduce the contact resistance between the connection structure and the fin transistor. The specific forming method includes depositing a metal layer, forming a mask, and patterning the metal layer. As shown in FIGS. 10-12 , when the source-drain conductive structure is formed in the first region and the conductive pattern on the gate is formed, the second conductive structures 20 parallel to each other are formed in the second region.

The second conductive structures 20 are spaced apart from each other and filled with a dielectric layer to form a second capacitor structure. A part of the second conductive structure 20 is used as the first electrode 21 of the second capacitor structure, and another part of the second conductive structure 20 is used as the second capacitor structure. The second electrode 22 of the capacitive structure. Specifically, the second conductive structure 20 spans the first conductive structure 12 and covers part of the sidewall and the upper surface of the first conductive structure 12 , and the second conductive structure 20 is perpendicular to the first conductive structure 12 . A part of the second conductive structures 20 are located in the area above the fins 11a, and there is a second dielectric layer (not marked in the figure) under the second conductive structures 20 located in the area above the fins 11a, so that the area above the fins 11a has a second dielectric layer (not marked in the figure). The second conductive structure 20 is isolated from the first conductive structure 12, while the second conductive structure 20 located in the region above the fin 11a is in contact with the fin 11a to form an electrical connection. Another part of the second conductive structure 20 is in contact with the first conductive structure 12 to form an electrical connection. The second conductive structure 20 in the area above the fin 11a serves as the first electrode 21 of the second capacitor structure, and another part of the second conductive structure 20 serves as the second electrode 22 of the second capacitor structure.

The first electrode 21 of the second capacitor structure is electrically connected to the fin 11a, that is, the first electrode of the first capacitor structure, and another part of the second conductive structure 20 is electrically connected to the second electrode 22 of the second capacitor structure. The first conductive structure 12 across the fin portion 11a is the second electrode of the first capacitor structure, so that the first capacitor structure and the second capacitor structure are connected in parallel.

Preferably, when the first capacitive structure and the second capacitive structure are connected in parallel, the second conductive structure 20 and the first conductive structure 12 located in the area above the fins 11a form a capacitive structure, and this capacitive structure is connected to the fins in the first capacitive structure. The portion 11a is electrically connected to form a capacitor structure with the fin portion 11a and the first electrode 21 of the second conductive structure 20 located in the area above the fin portion 11a as the first electrode, and the first conductive structure 12 as the second electrode. On this basis, the second capacitance structure and the first capacitance structure in parallel can be regarded as the first conductive structure 12 and the second electrode 22 of the second capacitance structure together as one electrode of a capacitor, the fin 11a and the second capacitance structure An electrode 21 collectively serves as the other electrode of a capacitor.

In step S230, a third capacitor structure is formed by multiplexing the process of forming the first metal layer. A via layer and a first metal layer are also formed in the first region to form a patterned metal interconnect layer to electrically connect the fin transistors and other active devices. The specific method includes depositing a dielectric layer, using photoresist to form a patterned mask layer, etching the dielectric layer to form through holes connected to the gate, source and drain electrodes, and depositing metal in the through holes, followed by the dielectric layer. A first metal layer is formed on the surface of the layer, and the first metal layer is patterned. Wherein, the metal layer is electrically connected with the metal in the through hole. FIG. 13 is a top view after forming the first through hole 31 and the second through hole 32 , FIG. 14 is a top view after forming the third conductive structure 40 , FIG. 15 is a schematic cross-sectional view taken along line X of FIG. Schematic diagram of the cross section of the Y line. As shown in FIG. 13 to FIG. 15 , while the first metal layer is formed in the first region, a plurality of third conductive structures 40 arranged in parallel are formed in the second region, and a plurality of third conductive structures 40 are formed under the third conductive structures 40 . A through hole 31 and a plurality of second through holes 32 . The first through hole 31 and the second through hole 32 are formed in the same dielectric layer. The third conductive structures 40 are spaced from each other and filled with a dielectric layer to form a third capacitor structure. A part of the third conductive structure 40 is used as the first electrode 41 of the third capacitance structure, and another part of the third conductive structure 40 is used as the second electrode 42 of the third capacitance structure. The third conductive structure 40 is located on the upper layer of the second conductive structure 20 and is perpendicular to the second conductive structure 20 , and there is a dielectric material between the third conductive structure 40 and the second conductive structure 20 .

The first through hole 31 formed under the third conductive structure 40 connects the first electrode 41 of the third capacitor structure and the part of the second conductive structure 20 under the third conductive structure 40 to be electrically connected to each other; at the same time, the third capacitor The second electrode 42 of the structure is connected to a part of the second conductive structure 20 under the third conductive structure 40 through the second through hole 32 so as to be electrically connected to each other.

Preferably, the first through hole 31 formed under the third conductive structure 40 is connected to the first electrode 41 of the third capacitive structure and the first electrode 21 of the second capacitive structure, and the second conductive structure 40 formed under the third conductive structure 40 is connected. The through hole 32 connects the second electrode 42 of the third capacitor structure and the second electrode 22 of the second capacitor structure. Specifically, the first through hole 31 is formed at the position where the first electrode 21 of the second capacitor structure and the first electrode 41 of the third capacitor structure intersect, and the second electrode 22 of the second capacitor structure and the first electrode 41 of the third capacitor structure are formed. A second through hole 32 is formed where the two electrodes 42 intersect, and the third capacitor is connected in parallel to the second capacitor through the first through hole 31 and the second through hole 32 .

Preferably, the distance between the third conductive structure 40 and the second conductive structure 20 in the vertical direction is controlled, and while the second capacitive structure and the third capacitive structure are connected in parallel, the distance between the second conductive structure 20 and the upper third conductive structure 40 is set. A capacitive structure is formed. The first capacitor structure, the second capacitor structure, and the third capacitor structure in parallel can be regarded as the first conductive structure 12, the second electrode 22 of the second capacitor structure, and the second electrode 42 of the third capacitor structure are electrically connected to each other and collectively act as one. One electrode of the capacitor; the fin 11a, the first electrode 21 of the second capacitor structure and the first electrode 41 of the third capacitor structure are electrically connected to each other and together serve as the other electrode of a capacitor.

In step S240, a fourth capacitor structure is formed by multiplexing the process of forming the second metal layer. A via layer and a second metal layer are also formed in the first region to form a patterned metal interconnect layer to electrically connect the fin transistors and other active devices. The specific method includes depositing a dielectric layer, using photoresist to form a patterned mask layer, etching the dielectric layer to form a through hole connected to the first metal layer, depositing metal in the through hole, and then forming a first metal layer on the surface of the dielectric layer. two metal layers, and the second metal layer is patterned. Wherein, the second metal layer is electrically connected with the metal in the through hole.

FIG. 17 is a top view after forming the third through hole 61 and the fourth through hole 62 , and FIG. 18 is a schematic view after forming the fourth conductive structure 50 . The capacitor structure and the second capacitor structure, FIG. 19 is a schematic cross-sectional view taken along line X of FIG. 18 , and FIG. 20 is a schematic cross-sectional view taken along line Y of FIG. 18 . 17-20 , while the second metal layer is formed in the first region, a plurality of fourth conductive structures 50 arranged in parallel and not connected to each other are formed in the second region; and a plurality of fourth conductive structures 50 are formed under the fourth conductive structure 50 A third through hole 61 and a plurality of fourth through holes 62 . Wherein, the third through hole 61 and the fourth through hole 62 are formed in the same dielectric layer. The fourth conductive structures 50 are spaced apart from each other and separated by a dielectric material layer to form a fourth capacitor structure. A part of the fourth conductive structure 50 is used as the first electrode 51 of the fourth capacitor structure, and another part of the fourth conductive structure 50 is used as the second electrode 52 of the first capacitor structure. The fourth conductive structure 50 is located on the upper layer of the third conductive structure 40 and is perpendicular to the third conductive structure 40 , and there is a dielectric material between the fourth conductive structure 50 and the third conductive structure 40 .

The third through hole 61 formed under the fourth conductive structure 50 connects the first electrode 51 of the fourth capacitive structure and the part of the third conductive structure 40 located under the fourth conductive structure 50 to be connected to each other so as to be electrically connected to each other; The second electrode 52 of the four-capacitor structure is connected to a part of the third conductive structure 40 under the fourth conductive structure 50 through the fourth through hole 62 to be electrically connected to each other.

Preferably, the third through hole 61 formed under the fourth conductive structure 50 is connected to the first electrode 51 of the fourth capacitive structure and the first electrode 41 of the third capacitive structure, and the fourth conductive structure 50 formed under the fourth conductive structure 50 is connected. The through hole 62 connects the second electrode 52 of the fourth capacitive structure and the second electrode 42 of the third capacitive structure. Specifically, a third through hole 61 is formed at a position where the first electrode 51 in the fourth capacitance structure and the first electrode 41 in the third capacitance structure intersect, and the second electrode 52 and the third capacitance in the fourth capacitance structure A fourth through hole 62 is formed at a position where the second electrodes 42 of the structure intersect, and the fourth capacitor is connected in parallel to the third capacitor through the third through hole 61 and the fourth through hole 62 .

Preferably, the distance between the fourth conductive structure 50 and the third conductive structure 40 in the vertical direction is controlled, and while the fourth capacitive structure and the third capacitive structure are connected in parallel, the distance between the fourth conductive structure 50 and the lower third conductive structure 40 is set. A capacitive structure is formed. The first capacitor structure, the second capacitor structure, the third capacitor structure and the fourth capacitor structure connected in parallel can be regarded as the first conductive structure 12, the second electrode 22 of the second capacitor structure, the second electrode 42 of the third capacitor structure and The second electrodes 52 of the fourth capacitor structure are electrically connected to each other and together serve as one electrode of a capacitor; the fin 11a, the first electrode 21 of the second capacitor structure, the first electrode 41 of the third capacitor structure, and the first electrode of the fourth capacitor structure. An electrode 51 is electrically connected to each other and collectively serves as the other electrode of a capacitor.

In step S250, a fifth capacitor structure is formed by multiplexing the process of forming the third metal layer. A via layer and a third metal layer are also formed in the first region to form a patterned metal interconnect layer to electrically connect the fin transistors and other active devices. Specifically, a metal layer is deposited and patterned. The specific method includes depositing a dielectric layer, using photoresist to form a patterned mask layer, etching the dielectric layer to form a through hole connected to the second metal layer, depositing metal in the through hole, and then forming a first layer on the surface of the dielectric layer. Three metal layers, and patterning the third metal layer. Wherein, the third metal layer is electrically connected with the metal in the through hole.

FIG. 21 is a schematic diagram after the fifth conductive structure 70 is formed. In order to show the embodiment of the present disclosure more clearly, the first capacitor structure, the second capacitor structure and the third capacitor structure are not shown in FIG. 21 . FIG. 19 is a schematic cross-sectional view taken along line X of FIG. 18 , and FIG. 20 is a schematic cross-sectional view taken along line Y of FIG. 18 . While the third metal layer is formed in the first region, a plurality of fifth conductive structures 70 that are arranged in parallel and are not connected to each other are formed in the second region; There is a dielectric material between the six through holes 82 and the fifth conductive structure 70 . The fifth through hole 81 and the sixth through hole 82 are formed in the same dielectric layer. The fifth conductive structure 70 is located on the upper layer of the fourth conductive structure 50 and is perpendicular to the fourth conductive structure 50 , and there is a dielectric material between the fifth conductive structure 70 and the fourth conductive structure 50 . A part of the fifth conductive structure 70 is used as the first electrode 71 of the fifth capacitor structure, and another part of the fifth conductive structure 70 is used as the second electrode 72 of the fifth capacitor structure.

The fifth through hole 81 formed under the fifth conductive structure 70 connects the first electrode 71 of the fifth capacitance structure and the part of the fourth conductive structure 50 under the fifth conductive structure 70 so as to be electrically connected to each other; at the same time, the fifth The second electrode 72 of the capacitor structure is connected to a part of the fourth conductive structure 50 under the fifth conductive structure 70 through the sixth through hole 82 to be electrically connected to each other.

Preferably, the fifth through hole 81 formed under the fifth conductive structure 70 is connected to the first electrode 71 of the fifth capacitance structure and the first electrode 51 of the fourth capacitance structure, and the sixth through hole 81 formed under the fifth conductive structure 70 The through hole 82 connects the second electrode 72 of the fifth capacitive structure and the second electrode 52 of the fourth capacitive structure. Specifically, a fifth through hole 81 is formed at a position where the first electrode 71 of the fifth capacitance structure and the first electrode 51 of the fourth capacitance structure intersect, and a fifth through hole 81 is formed between the second electrode 52 of the fourth capacitance structure and the fifth capacitance structure. A sixth through hole 82 is formed at the intersection of the second electrodes 72 , and the fifth capacitor is connected in parallel to the fourth capacitor through the fifth through hole 81 and the sixth through hole 82 .

Preferably, the distance between the fifth conductive structure 70 and the third conductive structure 50 in the vertical direction is controlled, and while the fifth capacitive structure and the fourth capacitive structure are connected in parallel, the distance between the fifth conductive structure 70 and the lower fourth conductive structure 50 is set. A capacitive structure is formed. As shown in FIG. 24 , a first capacitor structure, a second capacitor structure, a third capacitor structure, a fourth capacitor structure, and a fifth capacitor structure are finally formed in parallel with each other. It can be regarded as a high-density capacitive structure composed of two electrodes intertwined in the X and Y directions, wherein the first conductive structure 12, the second electrode 22 of the second capacitive structure, and the second electrode 42 of the third capacitive structure , the second electrode 52 of the fourth capacitor structure and the second electrode 72 of the fifth capacitor structure are electrically connected to each other as an electrode of this high-density capacitor structure; the fin 11a, the first electrode 21 of the second capacitor structure, the third The first electrode 41 of the capacitive structure, the first electrode 51 of the fourth capacitive structure, and the first electrode 71 of the fifth capacitive structure are electrically connected to each other and collectively serve as another electrode of the high-density capacitive structure.

It should be understood that the first through hole, the second through hole and the third through hole in the embodiments of the present disclosure are taken as an example of a cylindrical shape, and may also have other shapes, such as a rectangular parallelepiped. Meanwhile, the fins in the embodiments of the present disclosure take a rectangular parallelepiped as an example, and the fins may also have other shapes, such as a rhombus or a trapezoidal strip with a cross-section.

It should be understood that, in other embodiments, only one step in the process of forming the fin transistor and the process of forming the fin transistor and its interconnect structure may be multiplexed to form an independent capacitor structure.

In an optional implementation manner, the capacitor structure is formed by multiplexing the process of forming the source-drain region and the gate conductive structure on the fin.

In another optional implementation manner, the capacitor structure is formed by multiplexing the processes of forming the source-drain conductive structure and forming the conductive pattern on the gate.

In yet another optional implementation manner, the capacitor structure is formed by multiplexing the process of forming the first metal layer.

In yet another optional implementation manner, the capacitor structure is formed by multiplexing the process of forming the second metal layer.

In yet another optional implementation manner, the capacitor structure is formed by multiplexing the process of forming the third metal layer.

In the process of forming the fin transistor structure and the corresponding conductive connection structure on the semiconductor substrate in the first region according to the embodiment of the present disclosure, at least part of the fin transistor structure and the corresponding conductive connection structure are multiplexed in the second region. process to form at least one capacitive structure. Therefore, a high-density capacitor structure is formed while the fin transistor structure is formed, the process process is reduced, and the production efficiency is improved. The capacitor structure formed by the method of the embodiment of the present disclosure has the advantages of small volume and large capacitance.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims (15)

1. A method of forming a semiconductor device, comprising:

providing a semiconductor substrate, wherein a plurality of fin parts are formed on the semiconductor substrate;

in the process of forming the fin-type transistor structure and the corresponding conductive connection structure on the semiconductor substrate in the first region, at least part of the process is multiplexed in the second region to form at least one capacitor structure;

wherein multiplexing at least a portion of the processes to form at least one capacitor structure comprises at least one of:

forming a first capacitor structure by multiplexing the technological process of forming a source drain region and a grid electrode conductive structure on the fin portion;

forming a source-drain electrode conductive structure and a second capacitor structure by multiplexing the technological processes of forming a conductive pattern on the grid electrode;

forming a third capacitor structure by multiplexing the technological process of forming the first metal layer;

forming a fourth capacitor structure by multiplexing the process of forming the second metal layer; and

and forming a fifth capacitor structure by multiplexing the process of forming the third metal layer.

2. The method of claim 1, wherein forming the first capacitor structure by multiplexing processes of forming source drain regions and gate conductive structures on the fin comprises:

when a source drain region is formed in the first region, ion implantation is carried out on the corresponding position of the fin part of the second region to form a first electrode of the first capacitor structure;

forming a gate dielectric layer in the first region, and forming a first dielectric layer at the first position of the fin part in the second region;

and forming a first conductive structure crossing the fin part to form a second electrode of the first capacitor structure at the same time of forming the grid conductive structure in the first region.

3. The method of claim 1, wherein forming the second capacitor structure by multiplexing processes of forming the source and drain conductive structures and forming the conductive pattern on the gate comprises:

forming a source-drain electrode conductive structure and a gate electrode conductive pattern in the first area, and forming mutually parallel second conductive structures in the second area;

and one part of the second conductive structure is used as a first electrode of the second capacitor structure, and the other part of the second conductive structure is used as a second electrode of the second capacitor structure.

4. The method of claim 1, wherein forming the third capacitive structure by multiplexing processes for forming the first metal layer comprises:

forming a plurality of third conductive structures arranged in parallel in the second area while forming the first metal layer in the first area;

and one part of the third conductive structure is used as a first electrode of the third capacitor structure, and the other part of the second conductive structure is used as a second electrode of the third capacitor structure.

5. The method of claim 1, wherein forming the fourth capacitive structure by multiplexing processes for forming the second metal layer comprises:

forming a plurality of fourth conductive structures arranged in parallel in the second area while forming the second metal layer in the first area;

and one part of the fourth conductive structure is used as the first electrode of the fourth capacitor structure, and the other part of the second conductive structure is used as the second electrode of the fourth capacitor structure.

6. The method of claim 1, wherein forming the fifth capacitive structure by multiplexing processes of forming the third metal layer comprises:

forming a plurality of fifth conductive structures arranged in parallel in the second area while forming the third metal layer in the first area;

and one part of the fifth conductive structure is used as the first electrode of the fifth capacitor structure, and the other part of the fifth conductive structure is used as the second electrode of the fifth capacitor structure.

7. The method of claim 1, wherein multiplexing at least a portion of the process comprises:

forming a first capacitor structure by multiplexing the technological process of forming a source drain region and a grid electrode conductive structure on the fin portion; and

forming a source-drain electrode conductive structure and a second capacitor structure by multiplexing the technological processes of forming a conductive pattern on the grid electrode;

wherein, the forming of the first capacitor structure by multiplexing the process of forming the source-drain region and the gate conductive structure on the fin portion comprises:

performing ion implantation on the corresponding position of the fin part of the second region to form a first electrode of the first capacitor structure while forming a source drain region in the first region;

forming a gate dielectric layer in the first region, and forming a first dielectric layer at the first position of the fin part in the second region; and

forming a first conductive structure crossing the fin part to form a second electrode of the first capacitor structure at the same time of forming the grid conductive structure in the first area;

the forming of the second capacitor structure by multiplexing the process of forming the source-drain conductive structure and the conductive pattern on the gate comprises:

forming a plurality of second conductive structures which are arranged in parallel and are not connected with each other in the second region while forming a source-drain conductive structure and a conductive pattern on the grid in the first region;

wherein a portion of the second conductive structures are electrically connected to the second location of the fin to serve as the first electrode of the second capacitor structure, and another portion of the second conductive structures are electrically connected to the first conductive structure across the fin to serve as the second electrode of the second capacitor structure.

8. The method of claim 1, wherein multiplexing at least a portion of the process comprises:

forming a source-drain electrode conductive structure and a second capacitor structure by multiplexing the technological processes of forming a conductive pattern on the grid electrode; and

forming a third capacitor structure by multiplexing the technological process of forming the first metal layer;

wherein, the process of forming the source-drain electrode conductive structure and the conductive pattern on the grid electrode by multiplexing to form the second capacitor structure comprises the following steps:

forming a plurality of second conductive structures which are arranged in parallel in the second area while forming a source-drain conductive structure and a conductive pattern on the gate in the first area;

wherein one part of the second conductive structure is used as a first electrode of the second capacitor structure, and the other part of the second conductive structure is used as a second electrode of the second capacitor structure;

wherein forming the third capacitor structure by multiplexing the processes of forming the first metal layer comprises:

forming a plurality of third conductive structures arranged in parallel in the second region, and a first via and a second via underlying the third conductive structures, while forming the first metal layer in the first region;

wherein a portion of the third conductive structure as the first electrode of the third capacitor structure is electrically connected to the second conductive structure as the first electrode of the second capacitor structure through the first via, an

And the other part of the third conductive structure serving as the second electrode of the third capacitor structure is electrically connected with the second conductive structure serving as the second electrode of the second capacitor structure through the second through hole.

9. The method of claim 1, wherein multiplexing at least a portion of the process comprises:

forming a third capacitor structure by multiplexing the technological process of forming the first metal layer; and

forming a fourth capacitor structure by multiplexing the process of forming the second metal layer;

wherein forming the third capacitor structure by multiplexing the processes of forming the first metal layer comprises:

forming a plurality of third conductive structures arranged in parallel in the second area while forming the first metal layer in the first area;

wherein one part of the third conductive structure is used as the first electrode of the third capacitor structure, and the other part of the third conductive structure is used as the second electrode of the third capacitor structure;

wherein the forming of the fourth capacitor structure by multiplexing the process of forming the second metal layer comprises:

forming a plurality of fourth conductive structures arranged in parallel in the second area, and third and fourth through holes under the fourth conductive structures while forming the second metal layer in the first area;

wherein a portion of the fourth conductive structure as the first electrode of the fourth capacitive structure is electrically connected to a third conductive structure as the first electrode of the third capacitive structure by a third via, an

And a part of the fourth conductive structure serving as the second electrode of the fourth capacitor structure is electrically connected with the third conductive structure serving as the second electrode of the third capacitor structure through the fourth through hole.

10. The method of claim 1, wherein multiplexing at least a portion of the process comprises:

forming a fourth capacitor structure by multiplexing the process of forming the second metal layer; and

forming a fifth capacitor structure by multiplexing the technological process of forming the third metal layer;

wherein the forming of the fourth capacitor structure by multiplexing the process of forming the second metal layer comprises:

forming a plurality of fourth conductive structures arranged in parallel in the second area while forming the second metal layer in the first area;

wherein a part of the fourth conductive structure is used as the first electrode of the fourth capacitor structure, and another part of the fourth conductive structure is used as the second electrode of the fourth capacitor structure;

wherein the forming of the fifth capacitor structure by multiplexing the process of forming the third metal layer comprises:

forming a plurality of fifth conductive structures arranged in parallel and fifth and sixth through holes under the fifth conductive structures in the second region while forming the third metal layer in the first region;

wherein a portion of the fifth conductive structure as the first electrode of the fifth capacitive structure is electrically connected to the fourth conductive structure as the first electrode of the fourth capacitive structure by a fifth via, an

A portion of the fifth conductive structure as the second electrode of the fifth capacitive structure is electrically connected to the fourth conductive structure as the second electrode of the fourth capacitive structure through a sixth via.

11. The method of claim 7, wherein the first conductive structure is perpendicular to the fin.

12. The method of claim 7, wherein the second conductive structure is perpendicular to the first conductive structure.

13. The method of claim 8, wherein the third conductive structure is perpendicular to the second conductive structure, and the first via is located at an intersection of the first electrode of the second capacitive structure and the first electrode of the third capacitive structure, and the second via is located at an intersection of the second electrode of the second capacitive structure and the second electrode of the third capacitive structure.

14. The method of claim 9, wherein the fourth conductive structure is perpendicular to the third conductive structure, and the third via is located at an intersection of the first electrode of the third capacitive structure and the first electrode of the fourth capacitive structure, and the fourth via is located at an intersection of the second electrode of the third capacitive structure and the second electrode of the fourth capacitive structure.

15. The method of claim 10, wherein the fifth conductive structure is perpendicular to the fourth conductive structure, and the fifth via is located at an intersection of the first electrode of the fifth capacitive structure and the first electrode of the fourth capacitive structure, and the sixth via is located at an intersection of the second electrode of the fifth capacitive structure and the second electrode of the fourth capacitive structure.

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