CN110798479B - Interoperability device and method for dynamically reconfigurable high-speed serial bus and Ethernet - Google Patents
Interoperability device and method for dynamically reconfigurable high-speed serial bus and Ethernet Download PDFInfo
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Abstract
一种动态可重构高速串行总线与以太网的互操作装置与方法，其特征在于：所述动态可重构高速串行总线与以太网的互操作装置，包括以太网控制器、接收FIFO、发送FIFO、以太网数据存储器、协议数据缓冲器、协议解释器和总线通信控制器，将以太网控制器作为动态可重构高速串行总线上的一个设备，可以通过动态可重构高速串行总线进行以太网报文收发；同时，通过协议解释器对以太网报文进行监测，以太网上的主机通过专门设置的动态可重构高速串行总线访问报文，可以对动态可重构高速串行总线上的设备进行直接访问，实现以太网与动态可重构高速串行总线互操作访问。
A dynamically reconfigurable high-speed serial bus and Ethernet interoperability device and method, characterized in that: the dynamically reconfigurable high-speed serial bus and Ethernet interoperability device includes an Ethernet controller, a receiving FIFO , send FIFO, Ethernet data memory, protocol data buffer, protocol interpreter and bus communication controller, using the Ethernet controller as a device on the dynamically reconfigurable high-speed serial bus, it can pass the dynamic reconfigurable high-speed serial At the same time, the protocol interpreter monitors the Ethernet packets, and the host on the Ethernet accesses the packets through the specially set dynamic reconfigurable high-speed serial bus, which can monitor the dynamic reconfigurable high-speed serial bus. The devices on the serial bus are directly accessed to realize the interoperable access between the Ethernet and the dynamically reconfigurable high-speed serial bus.
Description
Technical Field
The invention relates to a data transmission method and a data transmission device of a high-speed serial bus, in particular to a method and a device for mutual access between dynamically reconfigurable high-speed serial bus equipment and Ethernet equipment.
Background
A dynamically reconfigurable high-speed serial BUS (UM-BUS for short) is a high-speed serial BUS which is provided aiming at the system miniaturization and embedded integrated design, can organically unify redundancy fault tolerance and high-speed communication and has the remote expansion capability. As shown in fig. 1, it adopts a bus-type topology based on MLVDS (multi-point Low Voltage Differential Signaling) technology, supports multi-node direct interconnection, can use 64 channels at most to transmit communication concurrently, and has a communication rate of 6.4 Gbps. In the communication process, if some channels have faults, the bus controller can monitor the faults in real time, dynamically distribute data to the remaining effective channels for transmission, realize dynamic reconstruction and carry out dynamic fault tolerance on communication faults.
The UM-BUS adopts a communication mode of master-slave command response, and performs information interaction in the form of BUS data packets. The UM-BUS BUS equipment is divided into a master control node, a slave node and a monitoring node, only the master control node can actively initiate BUS communication, the slave node can only respond to a BUS communication command to send a communication response packet, and the monitoring node cannot send any information to the BUS and can only monitor communication activities on the BUS.
The UM-BUS BUS supports remote storage access to BUS nodes, and supports three address spaces including a memory, an IO and an attribute, wherein the memory space is used for buffer data access, the attribute space is used for storing configuration attributes of the nodes, and the IO space is used for accessing real-time change information. Single-word or 256-word read-write access can be performed on the memory space, and only single-word read-write can be performed on the IO space and the attribute space. The UM-BUS has a single word size of 32 bits, for a total of 4 bytes.
The access to the UM-BUS BUS is converted into a communication command packet and a response packet transmitted on the BUS for information interaction. The communication command packet and the response packet are divided into two formats, namely a long packet and a short packet, and are collectively called a communication protocol packet. The response of 256-word read operation of the memory and the command of 256-word write operation of the memory adopt a long packet format, and other commands and responses adopt a short packet format. The UM-BUS communication protocol packet adopts a fixed format as shown in fig. 2, and includes two parts of a command header and data, a short packet only has a command header, and a long packet includes two parts of a command header and data. The command header part has 16 bytes and comprises a target device number, a source device number, a command/status word, an address offset, short packet data, a response command word, an execution status word and a command header CRC; the data portion has 1025 bytes, and includes a 256-word (1024 bytes) data body and a CRC check byte.
When the UM-BUS is applied, the UM-BUS can be used as an expansion of an internal BUS of a computer system and connected with various peripheral controllers to be used as IO (input output) equipment of the computer system. For example, the ethernet controller is connected to the computer system outside the chassis via the UM-BUS as a network device of the computer system for the computer system to communicate with other devices on the network.
With the continuous deepening of information physical systems and cloud computing concepts, the requirements of multiple computer systems on mutual access of storage resources and IO resources are increasing, and remote storage access becomes an important technical hotspot. The access to the internal resources of each device on the UM-BUS BUS through the Ethernet has good promotion effect on improving the information fusion depth and breadth among a plurality of information systems, and can be greatly helpful for improving the reliability of the whole system.
Generally, the mutual operation of different networks/buses is realized by making a gateway/bus protocol converter as shown in fig. 3, managing different network/bus communication controllers by using a processor, analyzing different network/bus protocols by software running on the processor, accessing required by another network on one network, and returning data through the processing protocol of the other network as required. Software is needed for protocol conversion and access management, and the method is low in efficiency, high in cost and complex in implementation.
In order to improve the efficiency of the UM-BUS mutual access with the Ethernet and reduce the complexity and cost of implementation, the invention provides a transmission method and a transmission device based on hardware protocol conversion execution, which do not need additional processors and software, can greatly improve the efficiency of the UM-BUS mutual access with the Ethernet and realize the direct mapping from the Ethernet message to the UM-BUS BUS access.
Disclosure of Invention
The invention aims to design a device and a method suitable for carrying out interoperation access between a dynamically reconfigurable high-speed serial BUS and an Ethernet, and provides an efficient solution for deep fusion of data in an information physical computing system based on a UM-BUS BUS and the Ethernet.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
a kind of interoperable device which can dynamically reconstruct high-speed serial bus and Ethernet, its characteristic is: the interoperation device of the dynamic reconfigurable high-speed serial bus and the Ethernet comprises an Ethernet controller, a receiving FIFO, a transmitting FIFO, an Ethernet data memory, a protocol data buffer, a protocol interpreter and a bus communication controller, wherein the Ethernet controller is a standard Ethernet MAC controller and is responsible for receiving and transmitting Ethernet datagrams; the receiving FIFO is an FIFO memory capable of storing an Ethernet message and is used for buffering and storing the Ethernet message received by the Ethernet controller; the transmission FIFO is an FIFO memory for storing an Ethernet message and is used for buffering and storing the Ethernet message to be transmitted through the Ethernet controller; the protocol data buffer is used for buffering and storing the interoperation command data from the Ethernet; the protocol interpreter reads the Ethernet message from the receiving FIFO, interprets the interoperation command and generates a control command required by interoperation to the Ethernet controller and the bus communication controller; the bus communication controller is used for connecting a dynamically reconfigurable high-speed serial bus, finishing bus coding and decoding and realizing management of bus communication; when the Ethernet data memory is controlled by the dynamic reconfigurable high-speed serial bus to carry out Ethernet communication, the Ethernet data memory stores a descriptor table for receiving and sending the Ethernet communication, stores communication data and realizes configuration and state management of the Ethernet controller.
The interoperation method of the dynamic reconfigurable high-speed serial bus and the Ethernet is characterized in that the interoperation between the Ethernet and the dynamic reconfigurable high-speed serial bus equipment is realized by adopting the following method according to the interoperation device of the dynamic reconfigurable high-speed serial bus and the Ethernet:
(1) when data are sent to the Ethernet through a dynamically reconfigurable high-speed serial bus, the data to be sent are organized into frames according to the format of Ethernet messages, and then the data are written into an Ethernet data memory through a bus communication controller, a sending descriptor table is established in the Ethernet data memory, the length, the storage position and other information of the data frame to be sent are described, and then the first address of the sending descriptor table is written into the Ethernet controller; the Ethernet controller reads data to be transmitted into a transmission FIFO frame by frame according to the transmission descriptor table and transmits the data to the Ethernet; after the transmission is finished, setting a transmission finishing state indication in the Ethernet data memory for a main processor on the dynamically reconfigurable high-speed serial bus to use;
(2) when data on the Ethernet is received through a dynamic reconfigurable high-speed serial bus, a receiving descriptor table is established in an Ethernet data memory, information such as the length of a data frame to be received, the storage position and the like is described, then the first address of the receiving descriptor table is written into an Ethernet controller, and the Ethernet controller is started to receive network data; after receiving the datagram for the local machine on the network, the Ethernet controller firstly caches in a receiving FIFO, then writes the received datagram into the position appointed by a descriptor table in an Ethernet data memory through a protocol interpreter according to the receiving descriptor table, sets a data receiving state indication and updates the descriptor; the main processor on the dynamic reconfigurable high-speed serial bus reads the received Ethernet message data from the Ethernet data memory through the dynamic reconfigurable high-speed serial bus when the data is required to be received by judging the data receiving state and the descriptor in the Ethernet data memory;
(3) when accessing the equipment on the dynamic reconfigurable high-speed serial bus through the Ethernet, the operation is carried out according to the following steps:
1) constructing a dynamic reconfigurable high-speed serial bus access message in a host machine which needs to perform dynamic reconfigurable high-speed serial bus access through an Ethernet, and sending the message to a dynamic reconfigurable high-speed serial bus and Ethernet interoperation device through the Ethernet;
2) after an Ethernet controller in the dynamic reconfigurable high-speed serial bus and Ethernet interoperation device receives an Ethernet message, the Ethernet message is put into a receiving FIFO (first in first out) and a protocol interpreter is informed; the protocol interpreter interprets the Ethernet message received by the receiving FIFO, and if the received Ethernet message is not a dynamic reconfigurable high-speed serial bus access message, the Ethernet message is transferred to the Ethernet data memory; if the received Ethernet message is a dynamic reconfigurable high-speed serial bus access message, turning to step 3);
3) the protocol interpreter takes a source MAC address, a source IP address and a source port number as a target MAC address, a target IP address and a target port number according to the received dynamic reconfigurable high-speed serial bus access message, and constructs a head part responding to a UDP message in a protocol data buffer area; simultaneously, a dynamic reconfigurable high-speed serial bus command head in a dynamic reconfigurable high-speed serial bus access message is obtained from a receiving FIFO; then, turning to step 4);
4) if the received dynamic reconfigurable high-speed serial bus access message is subjected to bus long packet write operation, transmitting the dynamic reconfigurable high-speed serial bus transmission data in the dynamic reconfigurable high-speed serial bus access message in the receiving FIFO to a transmission data buffer area of the bus communication controller under the control of the protocol interpreter, and turning to the step 5); if the received dynamic reconfigurable high-speed serial bus access message is not the bus long packet write operation, directly turning to the step 5);
5) writing the obtained dynamic reconfigurable high-speed serial bus command head into a bus communication controller, starting the bus communication controller to send a communication command to the dynamic reconfigurable high-speed serial bus, and performing bus access; then turning to step 6);
6) waiting for receiving a response packet on the dynamic reconfigurable high-speed serial bus, and turning to the step 7) if the response packet on the dynamic reconfigurable high-speed serial bus is received; if the response packet on the dynamic reconfigurable high-speed serial bus is not received within the specified bus access waiting time, turning to step 8);
7) writing the head of a response UDP message of a protocol data buffer area into a transmission FIFO, reading a response packet on the dynamic reconfigurable high-speed serial bus from the bus communication controller, writing the response packet into the transmission FIFO, and turning to the step 9) if the received access message of the dynamic reconfigurable high-speed serial bus does not perform a bus long packet reading operation; if the bus long packet reading operation is carried out, the bus read data is read from a receiving buffer area of the bus communication controller and written into a transmission FIFO, and then the step 9) is carried out;
8) writing the response UDP message head of the protocol data buffer area into a transmission FIFO, then constructing the response overtime error information of the dynamically reconfigurable high-speed serial bus, writing the response overtime error information into the transmission FIFO, and turning to the step 9);
9) and starting the Ethernet controller to send the response UDP message in the transmission FIFO to the Ethernet, and finishing the response of the Ethernet to the access of the dynamic reconfigurable serial bus.
Further, the dynamically reconfigurable high-speed serial bus access message is a UDP message, a target port number in a header of the UDP message is a specific protocol conversion port, and data in the message is divided into three parts in a sequence from front to back: the first part is a pad word, the purpose is to align the second part to a 32-bit boundary; the second part is a dynamic reconfigurable high-speed serial bus command head; the third part is that the dynamic reconfigurable high-speed serial bus transmits data.
Furthermore, the length of the data transmission of the dynamic reconfigurable high-speed serial bus in the dynamic reconfigurable high-speed serial bus access message is the same as the length of the data access of the dynamic reconfigurable high-speed serial bus long packet.
The interoperation device and the interoperation method for the dynamically reconfigurable high-speed serial BUS and the Ethernet can automatically complete protocol analysis, execution and data transmission from the Ethernet to the UM-BUS BUS access by hardware, do not need a processor in the access process, improve the access efficiency, accelerate the access speed, reduce the time overhead of the whole system and improve the overall processing capacity.
Drawings
FIG. 1 is a topological block diagram of a dynamically reconfigurable high-speed serial bus;
FIG. 2 is a dynamically reconfigurable high speed serial bus communication protocol packet format;
FIG. 3 is a schematic diagram of a typical heterogeneous network/bus inter-access device structure;
FIG. 4 is a diagram of an information physical system based on a dynamic reconfigurable high-speed serial bus and Ethernet connection;
FIG. 5 is a block diagram of the interoperation device of the dynamically reconfigurable high-speed serial bus and Ethernet of the present invention.
Detailed Description
As shown in fig. 1, the UM-BUS adopts a multi-channel intelligent dynamic redundancy BUS type topology based on M-LVDS (TIA/EIA-899), and at most 30 communication nodes are directly interconnected without routing or relaying equipment. The UM-BUS uses 2-64 channels to transmit data concurrently, and the maximum communication speed can reach 6.4 Gbps. In the using process of the UM-BUS, if the channel fails, the failed channel can be automatically shielded through the channel dynamic redundancy and fault reconstruction technology, and communication is continued on the rest healthy channels. The UM-BUS adopts a master-slave response communication mode and can provide remote storage access and non-intelligent expansion capability for the system.
The nodes on the UM-BUS BUS can be divided into a main node, a slave node and a monitoring node according to different functions, a communication process can only be initiated by the main node and responded by the slave node or other main nodes, and the monitoring node is used for monitoring the communication process on the BUS. The communication command and response between nodes exchange information in the form of bus data packets. All data and protocol words in a bus data packet are distributed to all available channels of the bus in turn and evenly in byte order for encoding transmission.
The UM-BUS BUS supports remote storage access to BUS nodes, three address spaces of a memory, IO and attributes are supported, and access to the UM-BUS BUS can be converted into a communication command packet and a response packet transmitted on the BUS for information interaction. The communication command packet and the response packet are divided into a long packet and a short packet, which are collectively called as a communication protocol packet, the response packet of 256-word read operation of the memory and the command packet of 256-word write operation of the memory adopt a long packet format, and other commands and responses adopt a short packet format. The UM-BUS communication protocol packet adopts a fixed format as shown in fig. 2, and includes two parts of a command header and data, a short packet only has a command header, and a long packet includes two parts of a command header and data. The command header part has 16 bytes and comprises a target device number, a source device number, a command/status word, an address offset, short packet data, a response command word, an execution status word and a command header CRC; the data portion has 1025 bytes, and includes a 256-word (1024 bytes) data body and a CRC check byte.
In the cyber-physical system shown in fig. 4, the UM-BUS is used as an internal interconnection BUS of two systems, and the two systems perform information exchange via the ethernet. At the same time, access to sensors connected on the UM-BUS BUS in the other system is required in both system 1 and system 2.
In the conventional implementation method, when the system 1 accesses the sensor of the system 2, the software on the processor of the system 1 sends access request information to the system 2 through the ethernet, and after the processor of the system 2 receives the access request information, the software accesses the sensor information, and then sends the access result to the system 1 through the ethernet. When a large amount of sensor interoperation accesses are carried out, the method needs to occupy a large amount of running time of the processor in the two systems to carry out sensor access, Ethernet protocol stack processing and data analysis, and is low in efficiency, high in cost and high in software complexity.
Based on the UM-BUS working principle, aiming at the existing problems, a specific implementation manner of the interoperation device and method for dynamically reconfigurable high-speed serial BUS and ethernet of the invention is as follows:
the Ethernet controller and UM-BUS controller in the thick dashed frame of FIG. 4 are designed as the interoperation device of the dynamically reconfigurable high-speed serial BUS and Ethernet shown in FIG. 5, so as to realize bidirectional communication control from UM-BUS to Ethernet and from Ethernet to UM-BUS.
As shown in fig. 5, the inter-operation device of the dynamically reconfigurable high-speed serial bus and the ethernet comprises an ethernet controller, a receiving FIFO, a transmitting FIFO, an ethernet data memory, a protocol data buffer, a protocol interpreter and a bus communication controller, wherein the ethernet controller is a standard ethernet MAC controller and is responsible for receiving and transmitting ethernet datagrams; the receiving FIFO is an FIFO memory capable of storing an Ethernet message and is used for buffering and storing the Ethernet message received by the Ethernet controller; the transmission FIFO is an FIFO memory for storing an Ethernet message and is used for buffering and storing the Ethernet message to be transmitted through the Ethernet controller; the protocol data buffer is used for buffering and storing the interoperation command data from the Ethernet; the protocol interpreter reads the Ethernet message from the receiving FIFO, interprets the interoperation command and generates a control command required by interoperation to the Ethernet controller and the bus communication controller; the bus communication controller is used for connecting a dynamically reconfigurable high-speed serial bus, finishing bus coding and decoding and realizing management of bus communication; when the Ethernet data memory is controlled by the dynamic reconfigurable high-speed serial bus to carry out Ethernet communication, the Ethernet data memory stores a descriptor table for receiving and sending the Ethernet communication, stores communication data and realizes configuration and state management of the Ethernet controller.
Defining the dynamic reconfigurable high-speed serial bus access message as a UDP message, wherein a target port number in a UDP message header of the message is a specific protocol conversion port (0xc000), and data in the message is divided into three parts from front to back: the first part is a pad word, the purpose is to align the second part to a 32-bit boundary; the second part is a dynamic reconfigurable high-speed serial bus command head; the third part is that the dynamic reconfigurable high-speed serial bus transmits data, and the length is the same as the length of the dynamic reconfigurable high-speed serial bus long packet access data.
The interoperation device of the dynamic reconfigurable high-speed serial bus and the Ethernet realizes interoperation between the Ethernet and the dynamic reconfigurable high-speed serial bus equipment by adopting the following method:
(1) when data are sent to the Ethernet through a dynamically reconfigurable high-speed serial bus, the data to be sent are organized into frames according to the format of Ethernet messages, and then the data are written into an Ethernet data memory through a bus communication controller, a sending descriptor table is established in the Ethernet data memory, the length, the storage position and other information of the data frame to be sent are described, and then the first address of the sending descriptor table is written into the Ethernet controller; the Ethernet controller reads data to be transmitted into a transmission FIFO frame by frame according to the transmission descriptor table and transmits the data to the Ethernet; after the transmission is finished, setting a transmission finishing state indication in the Ethernet data memory for a main processor on the dynamically reconfigurable high-speed serial bus to use;
(2) when data on the Ethernet is received through a dynamic reconfigurable high-speed serial bus, a receiving descriptor table is established in an Ethernet data memory, information such as the length of a data frame to be received, the storage position and the like is described, then the first address of the receiving descriptor table is written into an Ethernet controller, and the Ethernet controller is started to receive network data; after receiving the datagram for the local machine on the network, the Ethernet controller firstly caches in a receiving FIFO, then writes the received datagram into the position appointed by a descriptor table in an Ethernet data memory through a protocol interpreter according to the receiving descriptor table, sets a data receiving state indication and updates the descriptor; the main processor on the dynamic reconfigurable high-speed serial bus reads the received Ethernet message data from the Ethernet data memory through the dynamic reconfigurable high-speed serial bus when the data is required to be received by judging the data receiving state and the descriptor in the Ethernet data memory;
(3) when accessing the equipment on the dynamic reconfigurable high-speed serial bus through the Ethernet, the operation is carried out according to the following steps:
1) constructing a dynamic reconfigurable high-speed serial bus access message in a host machine which needs to perform dynamic reconfigurable high-speed serial bus access through an Ethernet, and sending the message to a dynamic reconfigurable high-speed serial bus and Ethernet interoperation device through the Ethernet;
2) after an Ethernet controller in the dynamic reconfigurable high-speed serial bus and Ethernet interoperation device receives an Ethernet message, the Ethernet message is put into a receiving FIFO (first in first out) and a protocol interpreter is informed; the protocol interpreter interprets the Ethernet message received by the receiving FIFO, and if the received Ethernet message is not a dynamic reconfigurable high-speed serial bus access message, the Ethernet message is transferred to the Ethernet data memory; if the received Ethernet message is a dynamic reconfigurable high-speed serial bus access message, turning to step 3);
3) the protocol interpreter takes a source MAC address, a source IP address and a source port number as a target MAC address, a target IP address and a target port number according to the received dynamic reconfigurable high-speed serial bus access message, and constructs a head part responding to a UDP message in a protocol data buffer area; simultaneously, a dynamic reconfigurable high-speed serial bus command head in a dynamic reconfigurable high-speed serial bus access message is obtained from a receiving FIFO; then, turning to step 4);
4) if the received dynamic reconfigurable high-speed serial bus access message is subjected to bus long packet write operation, transmitting the dynamic reconfigurable high-speed serial bus transmission data in the dynamic reconfigurable high-speed serial bus access message in the receiving FIFO to a transmission data buffer area of the bus communication controller under the control of the protocol interpreter, and turning to the step 5); if the received dynamic reconfigurable high-speed serial bus access message is not the bus long packet write operation, directly turning to the step 5);
5) writing the obtained dynamic reconfigurable high-speed serial bus command head into a bus communication controller, starting the bus communication controller to send a communication command to the dynamic reconfigurable high-speed serial bus, and performing bus access; then turning to step 6);
6) waiting for receiving a response packet on the dynamic reconfigurable high-speed serial bus, and turning to the step 7) if the response packet on the dynamic reconfigurable high-speed serial bus is received; if the response packet on the dynamic reconfigurable high-speed serial bus is not received within the specified bus access waiting time, turning to step 8);
7) writing the head of a response UDP message of a protocol data buffer area into a transmission FIFO, reading a response packet on the dynamic reconfigurable high-speed serial bus from the bus communication controller, writing the response packet into the transmission FIFO, and turning to the step 9) if the received access message of the dynamic reconfigurable high-speed serial bus does not perform a bus long packet reading operation; if the bus long packet reading operation is carried out, the bus read data is read from a receiving buffer area of the bus communication controller and written into a transmission FIFO, and then the step 9) is carried out;
8) writing the response UDP message head of the protocol data buffer area into a transmission FIFO, then constructing the response overtime error information of the dynamically reconfigurable high-speed serial bus, writing the response overtime error information into the transmission FIFO, and turning to the step 9);
9) and starting the Ethernet controller to send the response UDP message in the transmission FIFO to the Ethernet, and finishing the response of the Ethernet to the access of the dynamic reconfigurable serial bus.
The interoperation device and the interoperation method for the dynamically reconfigurable high-speed serial BUS and the Ethernet, which are disclosed by the invention, can realize interoperation access between the dynamically reconfigurable high-speed serial BUS and the Ethernet, can realize conversion of different communication protocols and automatic control of BUS access without participation of a processor when accessing BUS equipment through the Ethernet, can greatly improve the access speed of the Ethernet to the UM-BUS BUS, and further improve the overall processing capacity of a system.
The present invention may have various modifications within the scope not departing from the spirit of the invention, such as: the Ethernet or the dynamic reconfigurable high-speed serial bus can be changed into other networks or buses, the dynamic reconfigurable high-speed serial bus access message target port can be changed into other ports, and the receiving and transmitting FIFO adopts other forms of buffer memories and the like, which can be changed in different implementations. Such variations are also intended to be included within the scope of the invention as claimed.
Claims (4)
1. A kind of interoperable device which can dynamically reconstruct high-speed serial bus and Ethernet, its characteristic is: the Ethernet controller is a standard Ethernet MAC controller and is responsible for receiving and sending Ethernet data reports; the receiving FIFO is an FIFO memory capable of storing an Ethernet message and is used for buffering and storing the Ethernet message received by the Ethernet controller; the transmission FIFO is an FIFO memory for storing an Ethernet message and is used for buffering and storing the Ethernet message to be transmitted through the Ethernet controller; the protocol data buffer is used for buffering and storing the interoperation command data from the Ethernet; the protocol interpreter reads the Ethernet message from the receiving FIFO, interprets the interoperation command and generates a control command required by interoperation to the Ethernet controller and the bus communication controller; the bus communication controller is used for connecting a dynamically reconfigurable high-speed serial bus, finishing bus coding and decoding and realizing management of bus communication; when the Ethernet data memory is controlled by the dynamic reconfigurable high-speed serial bus to carry out Ethernet communication, the Ethernet data memory stores a descriptor table for receiving and sending the Ethernet communication, stores communication data and realizes configuration and state management of the Ethernet controller.
2. An interoperation method of a dynamic reconfigurable high-speed serial bus and an ethernet, characterized in that the interoperation device of the dynamic reconfigurable high-speed serial bus and the ethernet according to claim 1 realizes interoperation between the ethernet and a dynamic reconfigurable high-speed serial bus device by adopting the following method:
(1) when data are sent to the Ethernet through a dynamically reconfigurable high-speed serial bus, the data to be sent are organized into frames according to the format of Ethernet messages, and then the data are written into an Ethernet data memory through a bus communication controller, a sending descriptor table is established in the Ethernet data memory, the length and the storage position of the data frame to be sent are described, and then the first address of the sending descriptor table is written into the Ethernet controller; the Ethernet controller reads data to be transmitted into a transmission FIFO frame by frame according to the transmission descriptor table and transmits the data to the Ethernet; after the transmission is finished, setting a transmission finishing state indication in the Ethernet data memory for a main processor on the dynamically reconfigurable high-speed serial bus to use;
(2) when data on the Ethernet is received through a dynamic reconfigurable high-speed serial bus, a receiving descriptor table is established in an Ethernet data memory, the length and the storage position of a data frame to be received are described, then the first address of the receiving descriptor table is written into an Ethernet controller, and the Ethernet controller is started to receive network data; after receiving the datagram for the local machine on the network, the Ethernet controller firstly caches in a receiving FIFO, then writes the received datagram into the position appointed by a descriptor table in an Ethernet data memory through a protocol interpreter according to the receiving descriptor table, sets a data receiving state indication and updates the descriptor; the main processor on the dynamic reconfigurable high-speed serial bus reads the received Ethernet message data from the Ethernet data memory through the dynamic reconfigurable high-speed serial bus when the data is required to be received by judging the data receiving state and the descriptor in the Ethernet data memory;
(3) when accessing the equipment on the dynamic reconfigurable high-speed serial bus through the Ethernet, the operation is carried out according to the following steps:
1) constructing a dynamic reconfigurable high-speed serial bus access message in a host machine which needs to perform dynamic reconfigurable high-speed serial bus access through an Ethernet, and sending the message to a dynamic reconfigurable high-speed serial bus and Ethernet interoperation device through the Ethernet;
2) after an Ethernet controller in the dynamic reconfigurable high-speed serial bus and Ethernet interoperation device receives an Ethernet message, the Ethernet message is put into a receiving FIFO (first in first out) and a protocol interpreter is informed; the protocol interpreter interprets the Ethernet message received by the receiving FIFO, and if the received Ethernet message is not a dynamic reconfigurable high-speed serial bus access message, the Ethernet message is transferred to the Ethernet data memory; if the received Ethernet message is a dynamic reconfigurable high-speed serial bus access message, turning to step 3);
3) the protocol interpreter takes a source MAC address, a source IP address and a source port number as a target MAC address, a target IP address and a target port number according to the received dynamic reconfigurable high-speed serial bus access message, and constructs a head part responding to a UDP message in a protocol data buffer area; simultaneously, a dynamic reconfigurable high-speed serial bus command head in a dynamic reconfigurable high-speed serial bus access message is obtained from a receiving FIFO; then, turning to step 4);
4) if the received dynamic reconfigurable high-speed serial bus access message is subjected to bus long packet write operation, transmitting the dynamic reconfigurable high-speed serial bus transmission data in the dynamic reconfigurable high-speed serial bus access message in the receiving FIFO to a transmission data buffer area of the bus communication controller under the control of the protocol interpreter, and turning to the step 5); if the received dynamic reconfigurable high-speed serial bus access message is not the bus long packet write operation, directly turning to the step 5);
5) writing the obtained dynamic reconfigurable high-speed serial bus command head into a bus communication controller, starting the bus communication controller to send a communication command to the dynamic reconfigurable high-speed serial bus, and performing bus access; then turning to step 6);
6) waiting for receiving a response packet on the dynamic reconfigurable high-speed serial bus, and turning to the step 7) if the response packet on the dynamic reconfigurable high-speed serial bus is received; if the response packet on the dynamic reconfigurable high-speed serial bus is not received within the specified bus access waiting time, turning to step 8);
7) writing the head of a response UDP message of a protocol data buffer area into a transmission FIFO, reading a response packet on the dynamic reconfigurable high-speed serial bus from the bus communication controller, writing the response packet into the transmission FIFO, and turning to the step 9) if the received access message of the dynamic reconfigurable high-speed serial bus does not perform a bus long packet reading operation; if the bus long packet reading operation is carried out, the bus read data is read from a receiving buffer area of the bus communication controller and written into a transmission FIFO, and then the step 9) is carried out;
8) writing the response UDP message head of the protocol data buffer area into a transmission FIFO, then constructing the response overtime error information of the dynamically reconfigurable high-speed serial bus, writing the response overtime error information into the transmission FIFO, and turning to the step 9);
9) and starting the Ethernet controller to send the response UDP message in the transmission FIFO to the Ethernet, and finishing the response of the Ethernet to the access of the dynamic reconfigurable serial bus.
3. The interoperation method of the dynamically reconfigurable high-speed serial bus with the ethernet according to claim 2, wherein: the dynamic reconfigurable high-speed serial bus access message is a UDP message, a target port number in a UDP message header of the message is a specific protocol conversion port, and data in the message is divided into three parts from front to back: the first part is a pad word, the purpose is to align the second part to a 32-bit boundary; the second part is a dynamic reconfigurable high-speed serial bus command head; the third part is that the dynamic reconfigurable high-speed serial bus transmits data.
4. The interoperation method of the dynamically reconfigurable high-speed serial bus with the ethernet according to claim 3, wherein: the length of the transmission data of the dynamic reconfigurable high-speed serial bus in the dynamic reconfigurable high-speed serial bus access message is the same as the length of the long packet access data of the dynamic reconfigurable high-speed serial bus.
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