CN106168933B - A method of realizing virtual dual-port shared memory based on high-speed serial communication - Google Patents

Abstract

The invention discloses a method for realizing virtual dual-port shared memory based on high-speed serial communication, and belongs to the technical field of embedded computing. Both sides of the communication CPU of the present invention each have an FPGA chip to provide a RAM bus interface to it, and the two FPGA chips are connected with high-speed communication lines, and the internal firmware of the FPGA realizes various communication protocols and RAM access functions. The invention enables the interaction between CPUs to be as simple and efficient as a dual-port RAM, and has great flexibility in hardware distribution.

Description

A method of realizing virtual dual-port shared memory based on high-speed serial communication

technical field

The invention belongs to the technical field of embedded computing, specifically, the invention relates to a method for realizing virtual dual-port shared memory based on high-speed serial communication.

Background technique

Embedded computing systems are widely used in the field of industrial control. Power system secondary side automatic monitoring equipment is a typical embedded computing system application, which contains one or more embedded units to achieve specific protection control or data monitoring functions. This type of automation equipment is usually logically composed of the following parts: analog quantity acquisition unit, signal input unit, control output unit, logic processing unit, data processing unit, communication interface unit, human-computer interaction unit, etc.

Most of the early embedded computing devices use a single CPU or DSP as the core to form an embedded control computing system to realize the required functions of the device. With changes in the external environment such as power grid requirements and technological development, various indicators such as the computing performance and expansion capabilities of the equipment have gradually improved, making it necessary to use multiple sets of embedded subsystems inside the equipment to meet the requirements. How to carry out real-time data interaction between multiple CPUs has become the focus and difficulty of system design.

There are roughly two ways of real-time data interaction between CPUs: parallel mode and serial mode. The parallel method refers to the use of dual-port memory chips (referred to as dual-port RAM) to provide two sets of memory compatible buses, so that the two CPUs can jointly access the same segment of memory. The serial method refers to the connection between two CPUs through high-speed buses such as Ethernet and LVDS, and executes specific communication protocols for data transmission and reception. Both methods have certain limitations. The parallel mode of dual-port RAM can only be used when the two CPUs are located on the same printed board; the serial communication mode will occupy a large amount of computing resources of the CPU for the execution of the communication protocol, reducing the application performance and real-time reliability of the CPU. In addition, there are also standardized multi-CPU high-speed interactive options, such as PCI and PCI-E, but such solutions have high requirements for system cost, development difficulty and production technology, and cannot be widely used in low-to-medium complexity and cost-sensitive Industrial Control Systems.

Contents of the invention

The purpose of the present invention is to provide a method for realizing virtual dual-port shared memory based on high-speed serial communication, aiming at the problems between multi-CPU communication in the prior art.

Specifically, the present invention is realized by adopting the following technical solutions: the CPUs of both sides of the data interaction perform data interaction through two FPGA chips connected by a high-speed serial communication link; the FPGA chip includes RAM inside, and the RAM is used for Data storage and data exchange The CPUs on both sides access the RAM of the FPGA on each side respectively. The RAM space on both sides is the same and the addresses correspond to each other; when one CPU writes data to the RAM of the FPGA on the other side, the FPGA passes the data The high-speed serial communication link is sent to the FPGA on the other side, and the CPU on the other side accesses this data by accessing the same address of the RAM of the FPGA on its side.

The further feature of above-mentioned technical scheme is, when one side CPU writes data to the RAM of the FPGA of its side, after data arrives at the other side CPU, return to the same address of the RAM of the FPGA of data original writing side automatically, If the CPU on the side where the data was originally written reads the returned data, it indicates that the data has reliably arrived at the other party.

The above technical solution is further characterized in that the RAM of the FPGA is divided into a plurality of data mapping priorities according to the order of addresses, and the data in the address area with higher priority is preferentially transmitted.

A further feature of the above technical solution is that the RAM of the FPGA is provided with a read-write registration area and a system registration area for managing data sending and receiving timing and error handling.

The invention also discloses a power grid security and stability control device based on virtual dual-port shared memory communication, including a central processing module and various functional modules, and the above-mentioned high-speed serial communication is used between the modules to realize virtual dual-port sharing In-memory method to communicate.

The beneficial effects of the present invention are as follows: the data interaction method of the present invention combines dual-port memory and high-speed communication. Both sides of the communication CPU have an FPGA chip to provide RAM bus interface to it, and the two FPGA chips are connected by a high-speed communication line, so that the interaction between the CPUs can be as simple and efficient as a dual-port RAM, and it has great flexibility in hardware distribution , especially suitable for solving complex data interaction problems of multiple subsystems.

Description of drawings

Figure 1 is the basic block diagram of COM_RAM.

Figure 2 is a common topology diagram of COM_RAM.

FIG. 3 is a schematic diagram of a COM_RAM asymmetric switching node.

Figure 4 is a flowchart of COM_RAM work.

Figure 5 is a typical application of COM_RAM: a schematic diagram of the physical components of the stability control device.

Figure 6 is a typical application of COM_RAM: the communication topology diagram of the stability control device.

Detailed ways

The present invention will be further described in detail below in conjunction with the embodiments and with reference to the accompanying drawings.

Example 1:

This embodiment shows an example of a virtual dual-port RAM (COM_RAM for short) implemented by FPGA programming. It is based on FPGA large-scale programmable logic chip and high-speed communication technology, so that the CPUs at both ends of the high-speed serial communication link can perform efficient and convenient data interaction like on-board dual-port RAM.

The basic principle of COM_RAM is to design the firmware program of the FPGA to automatically realize the multi-layer protocol of data communication, and only provide a standardized RAM access interface for the CPUs on both sides of the data exchange, simplifying its communication processing burden, so that the CPU can focus on the application software. accomplish.

The basic implementation of COM_RAM is shown in Figure 1. COM_RAM is composed of two FPGA chips connected through a high-speed serial communication link and corresponding physical interfaces. Each FPGA chip includes two logic units (LOGIC) and cache (RAM) , where two logic units are used to implement data sending logic (SEND LOGIC) and data receiving logic (RECEIVE LOGIC), and RAM is used for data storage. The CPUs on both sides of the data exchange access the RAM of the FPGA on their respective sides, and form a shared RAM-style interaction through COM_RAM. When the CPU on one side writes data into the RAM of the FPGA on one side, the FPGA sends the data to the FPGA on the other side through a high-speed serial communication link, and the CPU on the other side accesses the RAM of the FPGA on the other side through the same Address to access this data.

Since COM_RAM mainly realizes the data communication function, it can be described with reference to the layer structure of the Open System Interconnection OSI. The following table briefly lists COM_RAM corresponding to the functional comparison of OSI in each layer of communication. The function implementation and characteristics of each layer are introduced separately below.

The function of the application layer is realized by exchanging application data between CPUs of both parties. COM_RAM provides an interactive interface in the form of RAM to the CPU. This interface can have the following characteristics:

1. The CPUs on both sides of the data exchange access a shared RAM for interaction, and the interface is similar to a real dual-port RAM chip.

2. The hardware provides standard SRAM bus interface, 8/16/32 bits are optional, Intel/PowerPC mode is optional.

3. The size of the dual-port RAM is variable according to the application, the lowest can be 256 bytes, and the highest can be 64k bytes.

4. The COM_RAM module can be reused, so that a CPU can realize parallel interaction with multiple CPUs through continuous multi-segment RAM.

The basic function of the transport layer is to reliably map the data written by the A-side CPU to a certain address in the shared RAM to the same address in the B-side CPU's RAM, that is, the mapping of application data. The same address here refers to a relative address, and the absolute addresses defined by the CPUs on both sides of the segment of RAM may be different. The transport layer implements reliable mapping through data registration and bounce mechanisms. Considering that COM_RAM is a virtual dual-port RAM, the speed of successful data mapping mainly depends on the bandwidth of the serial communication link. The layer introduces a priority mechanism, that is, high-priority data is mapped first. The principle of this layer is detailed as follows:

1. The basic usage scenario of COM_RAM is peer-to-peer interaction, namely There is a RAM interface between the CPU and the FPGA. The RAM space on both sides is the same, and the addresses correspond to each other, with bytes as the basic unit.

2. Data mapping: CPU_A writes new data to an address in RAM, and CPU_B should access the new data at the same address after a period of time.

3. Rebound mechanism: After CPU_A writes new data to a certain address in RAM, after the data reaches CPU_B, it will automatically return to the same address of CPU_A (the same address of the FPGA RAM on the side where the data was originally written). Only CPU_A can read new data here. That is, after the CPU writes the data, as long as the readback is correct, it means that the data has reliably reached the other party.

4. Priority mechanism: The RAM area is divided into several data mapping (transmission) priorities according to the order of addresses. For example, addresses 0-255 are high priority, and addresses 256-64k are low priority. The transmission mechanism of different priority data is similar to the corresponding mechanism of different priority interrupts in the CPU, that is, the one with the highest current priority gets the priority transmission resource. The data mechanism with different priorities gives the CPU flexibility in application. The CPU can write interactive data with high real-time requirements to the lower address area, so that it can be read by the receiver as soon as possible.

5. Registration mechanism: Each side of the RAM is designed with a read-write registration area and a system registration area, which are used to manage the timing of sending and receiving data and error handling. The registration area is an automatic management area, which cannot be accessed by the CPU. The size of the read-write registration area corresponds to the actual size of the RAM, and each unit records the sending status and receiving status of the corresponding RAM write/read bytes; the system registration area marks and records priority information, error handling status, etc. .

In communication networks such as Ethernet, the network layer usually achieves reliable transmission of data from a source node in a complex topology network to a target node through operations such as routing and switching. The design of COM_RAM is mainly oriented to the field of industrial control computing. It is applied in relatively fixed topology connection conditions and does not have complex routing and switching functions. Although the basic module of COM_RAM is a point-to-point virtual dual-port RAM, through reasonable configuration, various topological applications such as point-to-point, point-to-multipoint, and multi-point ring can be realized. If combined with the operation of the CPU at the application layer, more complex network construction can be further realized. The topology is briefly described as follows:

1. Point-to-point: the basic topology application of COM_RAM. That is, the two CPUs communicate with each other through COM_RAM, as shown in Figure 2.

2. Point-to-multiple: on a certain CPU side, multiple COM_RAM modules are reused in the FPGA, and at the same time, the hardware link is also connected to the multi-side CPU. In this way, the local CPU can realize parallel interaction with multiple CPUs by continuously accessing multiple RAM addresses, as shown in FIG. 2 .

3. Multipoint ring: There are three CPU nodes CPU_A, CPU_B and CPU_C, each of which has a COM_RAM interface, and each COM_RAM is connected in ring on the communication link, that is, TX_A->RX_B, TX_B->RX_C, TX_C->RX_A . Through the data mapping and bounce mechanism described above, multiple CPUs can share the same segment of RAM, as shown in Figure 2.

4. Asymmetric switching: In a variety of industrial applications, the data flow of the control system has asymmetric characteristics, such as collecting data from multiple distributed nodes and converging to the central node, and broadcasting data from management nodes to execution nodes, etc. For this reason, COM_RAM has expanded a one-to-many asymmetric exchange version: many-to-one realizes convergence, and one-to-many realizes broadcast. Correspondingly, the physical link must also be configured with 1+N. In this way, under the above-mentioned multi-point network, multiple CPUs on one side can share the same section of RAM to realize data interaction with a single CPU on the other side with lower physical and design costs. As shown in Figure 3.

The basic function of the link layer is to reliably send unit data from one end of communication to the other end, generally in units of data frames. In consideration of adapting to various physical layer communication links and ensuring high reliability in industrial applications, the design of COM_RAM in the link layer has the following characteristics:

1. Efficient synchronous short frames: In order to ensure the real-time transmission of upper layer data and the consideration of connection reliability, the link layer adopts frame synchronous transmission, that is, the sending and receiving links are repeatedly transmitted in units of frames. The frame header is a special byte code, the frame body is the upper layer data with a variable frame length, and the frame tail is the CRC check code of the frame. The data frame length with higher priority is shorter. Its work flow chart is shown in Fig. 4.

2. Balanced byte encoding: the basic unit of data in the link layer including the frame header is the encoded byte. Depending on the physical layer interface, the bytes are encoded in 8b10b or 5b4b. Use special codes in byte encoding for frame sending and receiving and priority management.

3. Flexible physical layer interface: the link layer and the physical layer interface are roughly divided into two types, one is the direct interface between the link layer and the physical transceiver device or circuit, and the byte encoding is performed by the link layer; the other is the connection with the standardized physical layer. Layer chip such as Ethernet PHY interface, the link layer controls the PHY chip to send and receive bytes with a dedicated timing, and the encoding and decoding of bytes is automatically completed by the PHY chip.

The physical layer provides the physical medium for communication transmission, and is designed to ensure the reliability of transmission as much as possible. In order to adapt to a variety of industrial application environments, COM_RAM supports a variety of communication specifications and media forms on the physical layer. Depending on the usage scenario, the supported methods are listed as follows:

1. In-board interaction: high-speed SERDES (1Gbps-2.5Gbps), LVDS (10Mpbs-800Mbps.

2. Backplane interaction: LVDS (10Mpbs-500Mbps), BLVDS/MLVDS (10Mpbs-100Mbps.

3. Inter-chassis interaction: 10bpsM/100Mbps/1000bpsM Ethernet cable, dedicated optical fiber (10Mbps-2.5Gbps).

4. Remote interaction: E1 coaxial cable (multiplex link, 2Mbps/channel), SDH optical fiber (155Mbps-2.5Gbps).

In order to cope with the characteristics of changing physical layer media and complex application scenarios, the design of the physical layer has the following two characteristics:

(1) The link is changeable and the mechanism remains the same: under different application scenarios and constraints, there are many situations in the physical communication link. Distances can be as low as 10Mbps in applications using Ethernet cables. Due to the design of the layered mechanism, the communication mode and rate of the physical layer only affect the frame transmission speed of the link layer, and do not affect the upper layer implementation mechanism or reliability.

(2) Link doubling, bandwidth doubling: the original intention of the present invention is to make both communication parties under the serial link condition improve the data interaction efficiency as much as possible, so under the physical conditions permitting, the data transmission bandwidth should be improved as much as possible. Therefore, at the interface between the link layer and the physical layer, a bandwidth doubling mechanism is additionally designed, even if multiple identical communication links can provide an incremental increase in bandwidth corresponding to mathematics (due to the increase in communication overhead such as data alignment, the actual slightly lower bandwidth). For example, in the application based on backplane LVDS communication, the delay of 4-byte data mapping (CPU_A write, CPU_B read) of a single 100Mbps link is about 1us, and when 5 same links are connected at the same time, the delay will be shortened To 200ns, this speed is close to the real dual-port RAM response speed. In LVDS physical links, this function can be directly supported; in Ethernet links, direct connection is required; in E1/SDH link applications that physically support division and multiplexing protocols, remote communication can be realized bandwidth doubled.

Example 2:

This embodiment demonstrates the application of COM_RAM in a power grid security and stability control device.

The power grid security and stability control device is an important control device in a high voltage substation. Each set of equipment is usually composed of several chassis, and each chassis has multiple plug-ins, which respectively realize functions such as analog acquisition, logic calculation, digital input and output, man-machine interface, and external communication. Most of the plug-ins contain embedded systems centered on a CPU. The plug-ins inside the chassis and the chassis need to interact in real time. Interacting data pairs vary in real-time, bandwidth, and data flow. For example, switching data has high real-time requirements, low bandwidth, and two-way balance, human-machine data has high bandwidth but unbalanced input and output, and low real-time performance, and acquisition data has high bandwidth and real-time requirements and one-way upstream, etc. If COM_RAM technology is applied to this system, through the combination of various configuration methods, it can efficiently solve the problem of complex data interaction of multiple subsystems.

Fig. 5 lists a typical hardware configuration of the safety and stability control device. The device system consists of multiple chassis, including a master chassis and one or more slave chassis. The central processing unit in the master chassis needs to collect the collection, switching, communication and other data of each slave chassis and perform real-time calculation and logical judgment, and at the same time output control commands or communication data to each slave chassis. Each slave chassis is configured with internal modules according to application requirements. All slave chassis physically communicate with the master chassis through optical fibers.

Figure 6 describes the communication logic structure between the modules with COM_RAM as the main communication mode inside the above-mentioned stability control device:

1. Inside the main chassis, the central processing module communicates with the data management module and the man-machine interface module through the LVDS link on the backplane of the chassis. The data management module implements functions such as system data storage, printing, and background communication; the man-machine interface module implements functions such as liquid crystal display and keyboard input of the system man-machine interface.

2. The central processing module communicates with each slave chassis through bidirectional optical fibers. Each slave chassis is equipped with a communication exchange module to realize asymmetric data real-time exchange between multiple modules in the slave chassis and the central processing module, so that both ends share the same segment of data exchange space. According to the actual data transmission bandwidth requirements of the application, a slave chassis can be configured with multiple pairs of optical fibers to increase the communication bandwidth.

3. The communication bandwidth is small in the chassis equipped with modules such as input and output, so the connection between multi-chassis and central processing modules can be realized through the topology of multi-point ring, which can not only meet the demand, but also save communication interfaces resource.

4. Inside the slave chassis, each module has a communication channel with the communication switching module. According to different types of modules, LVDS, BLVDS, CAN, RS-485 and other physical channels in the backplane resources can be used, and communication protocols such as COM_RAM and MODBUS can be used respectively. In the FPGA chip of the communication exchange module, an IP module with DMA function is designed to realize the seamless exchange of low-speed communication interfaces such as COM_RAM and MOD_BUS, and facilitate the mutual visit of the CPUs of both communication parties.

Although the present invention has been disclosed above with preferred embodiments, the embodiments are not intended to limit the present invention. Any equivalent changes or modifications made without departing from the spirit and scope of the present invention also belong to the protection scope of the present invention. Therefore, the scope of protection of the present invention should be based on the content defined by the claims of this application.

Claims (5)

1. a kind of method for realizing virtual dual-port shared drive based on high-speed serial communication, which is characterized in that data interaction is double The CPU of side is by carrying out data interaction by the fpga chip that high-speed serial communication link connection is got up by two；The FPGA Chip interior includes RAM, and RAM is used for the storage of data, and the CPU of data interaction both sides accesses the RAM of the FPGA of respective side respectively, Two sides ram space is identical, and address is corresponding；When data are written into the RAM of the FPGA of its side in side CPU, which counts this According to the FPGA for being sent to the other side by high-speed serial communication link, other side CPU is identical by the RAM for accessing the FPGA of its side This data is accessed in address；

Wherein by communication process between high-speed serial communication both link ends be divided into application layer, transport layer, network layer, link layer, Totally 5 layers of physical layer, transport layer, network layer, link layer are realized by the FPGA；

The application layer for describe can be provided for communicating pair CPU the access interface for being equal to dual-port shared drive and Characteristic, transport layer and following layers provide the access interface of dual-port shared drive for application layer；

Transport layer is used for one section of communication memory address mappings of communicating pair, and using rebound mechanism and priority mechanism；

The network layer is divided into point-to-point, multiple spot ring, point-to-points, asymmetric exchange for realizing network topology, by communication network Four seed types, wherein two CPU of point-to-point finger are exchanged visits by the RAM of FPGA, multiple spot ring refers to that multiple cpu nodes are communicating Chain road annular concatenation shares same section of RAM, it is point-to-points refer to side CPU by the multistage address ram of connected reference FPGA with More side CPU are interacted parallel, and asymmetric exchange refers to that the multiple CPU in side share the number of the RAM and other side list CPU of same section of FPGA According to interaction；

Unit data is reliably sent to opposite end from communication one end by the link layer, is transmitted using short frame format, and frame head is spy Different byte code, frame are the upper layer data data of variable frame length, and postamble is this frame cyclic redundancy check, the higher data of priority Frame length is shorter, when link layer and physics transceiving device or circuit direct interface, carries out byte code by link layer, works as link layer When with standardized physical chip interface, byte code is carried out by physical chip；

The physical layer is for providing the physical medium of communications.

2. the method according to claim 1 for realizing virtual dual-port shared drive based on high-speed serial communication, feature It is, the mechanism of rebounding refers to, when side CPU enters data to the RAM write of the FPGA of its side, reaches other side CPU in data Afterwards, the identical address for passing back to the RAM of the FPGA of data original write-in side automatically, as the CPU of data original write-in side reads this passback Statistics indicate that data reliably reach other side.

3. the method according to claim 1 or 2 for realizing virtual dual-port shared drive based on high-speed serial communication, special Sign is that the priority mechanism refers to, the RAM of the FPGA is divided into multiple data according to the sequence of address and maps priority, The high priority data of the address area high in priority transmits.

4. the method according to claim 1 or 2 for realizing virtual dual-port shared drive based on high-speed serial communication, special Sign is that the RAM of the FPGA is equipped with read-write Acceditation Area and system registry area, at the transmitting-receiving timing and mistake for managing data Reason.

5. it is a kind of based on virtual dual-port shared drive communication safety and stability control device of electric network, including central processing module with And each function module, which is characterized in that using being realized based on high-speed serial communication as described in claim 1 ~ 4 between each module The method of virtual dual-port shared drive is communicated.