CN110767135A - Display panel - Google Patents

Abstract

The invention discloses a display panel, which is provided with a special-shaped active area and a peripheral area and comprises a plurality of pixel units, a plurality of gate lines and a substrate array row driving circuit. The plurality of pixel units are located in the specially-shaped active area. The gate lines are located in the irregular active area and are respectively coupled to the pixel units. The substrate array row driving circuit is positioned in the peripheral area and comprises a plurality of shift registers and a plurality of clock signal routing lines. The plurality of shift registers are located in the peripheral area and are respectively coupled to the plurality of gate lines. The clock signal traces are located in the peripheral region and are respectively coupled to the shift registers. At least one clock signal wire in the plurality of clock signal wires comprises a first part, a second part and a third part, wherein an included angle between the first part and the second part is an obtuse angle, and an included angle between the second part and the third part is an obtuse angle. The invention is beneficial to the manufacture of the display panel comprising the substrate array row driving circuit and the special-shaped active area, and can meet the requirements of consumers on appearance and efficiency.

Description

display panel

technical field

The present invention relates to a display panel, and more particularly, to a display panel with a special-shaped active area.

Background technique

With the evolution of display panel manufacturing technology, today's high-resolution display panels can be applied to wearable and handheld electronic products, such as smart watches, health bracelets, and the like. On the other hand, consumers' demand for aesthetics of electronic products is also increasing, and display panels with special design are applied to electronic products. Display panels on these electronic products usually have non-rectangular shapes, such as circular or other irregular shapes. On the other hand, for a display panel integrating a gate driver, the gate driver and the pixel unit are both disposed on the active array substrate and located in the peripheral area and the active area of the display panel, respectively, so the gate driver needs to be reserved in the peripheral area This will increase the width of the peripheral area, which is not conducive to the narrow frame requirement of the display panel. How to apply the technology of integrating the gate driver to the non-rectangular display panel and satisfy consumers' demands for appearance and performance has become one of the goals of the related industry.

SUMMARY OF THE INVENTION

The object of the present invention is to provide a display panel, which includes a gate on array (GOA) circuit of a substrate array having a special-shaped active area, and the row drive circuit of the substrate array has a special arrangement of components, which is helpful for the display panel. Manufactured to meet consumer demands for appearance and performance.

In accordance with the above objectives, the present invention provides a display panel, which has an odd-shaped active region and a peripheral region, and includes a plurality of pixel units, a plurality of gate lines, and a gate on array (GOA) ) circuit. A plurality of pixel units are located in the shaped active area. A plurality of gate lines are located in the shaped active region and are respectively coupled to a plurality of pixel units. The substrate array row driving circuit is located in the peripheral area, and includes a plurality of shift registers and a plurality of clock signal lines. A plurality of shift registers are located in the peripheral region and are respectively coupled to the plurality of gate lines. A plurality of clock signal traces are located in the peripheral region and are respectively coupled to the plurality of shift registers. At least one clock signal trace in the plurality of clock signal traces includes first to third parts, and the included angle between the first part and the second part of the clock signal trace is between 90 degrees and 180 degrees. The included angle between the second portion and the third portion of the clock signal trace is between 90 degrees and 180 degrees.

According to an embodiment of the present invention, a part of the edge of the above-mentioned special-shaped active region is arc-shaped.

According to another embodiment of the present invention, the above-mentioned shift registers include a first shift register and a second shift register, and the first shift register and the second shift register are respectively coupled through scan signal output leads. To the first gate line and the second gate line in the plurality of gate lines, the number of pixel units coupled to the first gate line is smaller than the number of pixel units coupled to the second gate line , and the length of the scan signal output lead coupled to the first gate line is greater than the length of the scan signal output lead coupled to the second gate line.

According to yet another embodiment of the present invention, each shift register includes at least one transistor, which is an amorphous silicon thin film transistor.

According to another embodiment of the present invention, the above-mentioned display panel further includes a reference potential signal line, the reference potential signal line is located in the peripheral region and is coupled to each shift register, and the reference potential signal line includes a first One to third parts, wherein the included angle between the first part and the second part of the reference potential signal trace is between 90 degrees and 180 degrees, and the angle between the second part and the third part of the reference potential signal trace is between 90 degrees and 180 degrees. The angle between them is between 90 degrees and 180 degrees.

According to another embodiment of the present invention, a reference potential signal lead is further included between two adjacent shift registers of the plurality of shift registers, and the reference potential signal lead is coupled to the reference potential signal wiring and the plurality of The adjacent shift registers, and the reference potential signal lead and the reference potential signal wiring belong to the same metal layer.

According to yet another embodiment of the present invention, the plurality of shift registers are located between the reference potential signal trace and the special-shaped active region.

According to yet another embodiment of the present invention, the plurality of shift registers are located between the clock signal traces and the special-shaped active region.

According to the above object, the present invention further provides a display panel, which has an odd-shaped active area and a peripheral area, and includes a plurality of pixel units, a plurality of gate lines, and a gate on array; GOA) circuit. A plurality of pixel units are located in the shaped active area. A plurality of gate lines are located in the shaped active region and are respectively coupled to a plurality of pixel units. The substrate array row driving circuit is located in the peripheral area, and includes a plurality of first shift registers, a plurality of second shift registers, a plurality of first clock signal lines and a plurality of second clock signal lines. The plurality of first shift registers are located in the peripheral region and are respectively coupled to odd-numbered gate lines of the plurality of gate lines. A plurality of second shift registers are located in the peripheral region and are respectively coupled to even-numbered gate lines of the plurality of gate lines. A plurality of clock signal traces are located in the peripheral region and are respectively coupled to the plurality of shift registers. At least one of the plurality of first clock signal traces and the plurality of second clock signal traces includes first to third portions, and the included angle between the first portion and the second portion of the clock signal traces Between 90 degrees and 180 degrees, the included angle between the second part and the third part of the clock signal trace is between 90 degrees and 180 degrees.

According to an embodiment of the present invention, the above-mentioned display panel further includes a first reference potential signal wiring and a second reference potential signal wiring, the first reference potential signal wiring is located in the peripheral area and is coupled to each of the first shifters. A bit register, and the second reference potential signal trace is located in the peripheral region and is coupled to each of the second shift registers. The reference potential signal traces in the first reference potential signal trace and the second reference potential signal trace include first to third parts, wherein the first part and the second part of the reference potential signal trace are sandwiched between the first part and the second part. The angle is between 90 degrees and 180 degrees, and the included angle between the second part and the third part of the reference potential signal trace is between 90 degrees and 180 degrees.

The advantage of the present invention is at least that, through the special arrangement of the substrate array row driving circuit elements, it is helpful for the manufacture of the display panel including the substrate array row driving circuit and the special-shaped active area, and can satisfy consumers' demands for appearance and performance. appeal.

Description of drawings

For a more complete understanding of the embodiments and their advantages, the following descriptions are now made with reference to and in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic diagram of a display panel according to an embodiment of the present invention;

2 is a schematic diagram of a display panel according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of the gate driver of FIG. 1;

FIG. 4 is an equivalent circuit diagram of the shift register of FIG. 3;

FIG. 5 illustrates the arrangement of pixel units and the arrangement of components in the upper left corner region of the display panel of FIG. 1;

FIG. 6 illustrates the shift register and element configuration in the upper left area of the display panel of FIG. 1;

7 is a schematic diagram of a display panel according to an embodiment of the present invention;

8 is a schematic diagram of a display panel according to an embodiment of the present invention;

9 is a schematic diagram of a gate driver according to an embodiment of the present invention;

FIG. 10 is a schematic diagram of a gate driver according to an embodiment of the present invention; and

11 is a schematic diagram of a display panel according to an embodiment of the present invention.

Detailed ways

Embodiments of the present invention are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The discussed and disclosed embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention.

It will be understood that, although the terms "first", "second", "third" . . . may be used herein to describe various elements, features, regions and/or sections, these terms should not limit these Elements, Parts, Areas and/or Sections. These terms are only used to distinguish one element, component, region and/or section from another element, component, region and/or section.

The terms used herein are for the purpose of describing particular embodiments only and not for the purpose of limiting the claims. Unless otherwise limited, the singular forms "a" or "the" can also be used to refer to the plural form. Furthermore, the use of spatially relative terms is intended to describe different orientations of elements in use or operation, and is not limited to the orientation depicted in the figures. Elements may also be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein may be interpreted in the same manner.

For simplicity and clarity of illustration, reference numerals and/or letters may be repeated herein among various embodiments, but this does not imply a causal relationship between the various embodiments and/or configurations discussed.

As used herein, the term "coupled" may refer to two or more elements in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, and "coupled" may also refer to two One or more elements operate or act with each other.

Please refer to FIG. 1 , which is a schematic diagram of a display panel 100 according to some embodiments of the present invention. The display panel 100 may be, for example, a twisted nematic (TN) type, an in-plane switching (IPS) type, a fringe-field switching (FFS) type, or a vertical alignment (VA) type. type of liquid crystal display panel, but not limited to this. The display panel 100 includes an active array substrate 102 and has an active area 110 and a peripheral area 120 , the active area 110 has a plurality of pixel units disposed on the active array substrate 102 , and includes a gate driver 130 in the peripheral area 120 . It is used to generate a scan signal and transmit the scan signal to the gate lines in the active area 110 , so that the pixel units in the active area 110 are driven by the scan signal to display an image at a specific time.

In the embodiment of the present invention, the display panel 100 is a system on glass (SOG) panel. That is, the gate driver 130 is fabricated on the active array substrate 102 of the display panel 100 . In this way, the same process can be used to fabricate electronic components in the gate driver 130 and electronic components in the active region 110 (eg, thin film transistors, pixel electrodes, etc., but not limited thereto).

In addition, as shown in FIG. 1 , the display panel 100 is an odd-shaped display panel, that is, the active array substrate 102 is odd-shaped. As shown in FIG. 1 , the upper left corner, the lower left corner, the upper right corner and the lower right corner of the display panel 100 are all arcs rather than right angles. In addition, the active area 110 is a special-shaped active area, and the shape of the edge 110E of the active area 110 is similar to the shape of the edge 100E of the display panel 100 . If the size of each pixel unit in the active area 110 is the same, the number of pixel units in each pixel column located at the top and bottom of the active area 110 is smaller than the number of pixel units in other pixel columns in the active area 110 .

In addition to the display panel 100 shown in FIG. 1 , the display panel of the present invention may also have other forms. For example, please refer to FIG. 2 , which is a schematic diagram of a display panel 100 ′ according to some embodiments of the present invention. As shown in FIG. 2 , the display panel 100 ′ is a special-shaped display panel, that is, the active array substrate 102 ′ is a special-shaped display panel, wherein the upper left corner, the lower left corner, the upper right corner and the lower right corner of the display panel 100 ′ are all arc-shaped rather than rectangular Right angle. In addition, the active area 110' is a special-shaped active area, and the shape of the edge 110E' of the active area 110' is similar to the shape of the edge 100E' of the display panel 100'. Compared with the display panel 100 of FIG. 1 , the display panel 100 ′ of FIG. 2 has a notch in the top region B thereof. The gate driver 130 of FIG. 2 is the same as the gate driver 130 of FIG. 1 , and details are not described here.

FIG. 3 is a schematic diagram of the gate driver 130 of FIG. 1 . As shown in FIG. 3 , the gate driver 130 is located at the left edge of the display panel 100 and disposed in the peripheral area 120 . The gate driver 130 includes clock signal traces L1-L4, start signal traces SL1, end signal traces SL2, control signal traces PL1, PL2, and shift registers 132(1)-132 from the first stage to the Nth stage (M), for outputting the scan signals OUT( 1 )˜OUT(M) to the gate lines in the active region 110 respectively and sequentially, wherein N is a positive integer greater than or equal to 5. For example, in the same frame period, the first-stage shift register 132(1) outputs the first-stage scan signal OUT(1) to the first gate line, and then after the time t , the second-stage scanning signal OUT(2) is output from the second-stage shift register 132(2) to the second gate line, and after time t, the third-stage shift register 132(3) outputs the second-stage scanning signal OUT(2) to the second gate line. The 3-stage scanning signal OUT( 3 ) goes to the third gate line, and so on, until the N-th stage shift register 132 (M) outputs the N-th stage scanning signal OUT(M) to the M-th gate line. In some embodiments, as shown in FIG. 3, M is a multiple of 4, and the clock signal trace L1 provides the clock signal C1 to the first stage shift register 132(1), the fifth stage shift register 132(5 ), ... and the (M-3) stage shift register 132 (M-3), the clock signal trace L2 provides the clock signal C2 to the second stage shift register 132 (2), the sixth stage shift register 132 ( 6), ... and the (M-2) stage shift register 132 (M-2), the clock signal line L3 provides the clock signal C3 to the third stage shift register 132 (3), the seventh stage shift register 132 (7), ... and the (M-1)th stage shift register 132 (M-1), and the clock signal line L4 provides the clock signal C4 to the fourth stage shift register 132 (4), the eighth stage shift Registers 132(8), . . . and the M-th stage shift register 132(M). The clock signals C1 to C4 are all periodic signals, and the cycle time is the same, wherein the clock signal C2 lags behind the clock signal C1 by 1/4 cycle time, the clock signal C3 lags behind the clock signal C2 by 1/4 cycle time, and the clock signal C4 lags clock signal C3 by 1/4 cycle time. In addition, the start signal line SL1 provides the start signal STV1 to the first and second stage shift registers 210(1), 210(2), and the end signal line SL2 provides the end signal STV2 to the (M−1)th ) stage and the Mth stage shift registers 210(M-1), 210(M). The control signal lines PL1 and PL2 respectively provide pull-down control signals GPW1 and GPW2 to the first to Mth stage shift registers 210( 1 )˜ 210(M). The clock signal lines L1-L4, the start signal line SL1, the end signal line SL2 and the control signal lines PL1, PL2 can be coupled to one or more chips, namely the clock signals C1-C4, the start signal STV1, the end signal The signal STV2 and the pull-down control signals GPW1 and GPW2 may be provided by one or more chips, such as, but not limited to, a driving chip and/or a timing control chip.

It should be noted that although the above description is based on the example that the gate driver 130 is arranged in the display panel 100 of FIG. For the implementation of the display panel 100 ′, please refer to the above for the relevant description, and will not be repeated here.

FIG. 4 is an equivalent circuit diagram of the i-th stage shift register 132(i) in the gate driver 130 according to FIG. 3 , where i is a positive integer from 1 to M. As shown in FIG. As shown in FIG. 4 , the i-th stage shift register 132(i) includes a precharge unit 210 , a pull-up unit 220 , a first pull-down unit 230 and a second pull-down unit 240 , wherein the precharge unit 210 and the pull-up unit 220 , one end of the first pull-down unit 230 and the second pull-down unit 240 is coupled to the node X1 (which corresponds to the precharge signal PC(i)), and the pull-up unit 220 , the first pull-down unit 230 and the second pull-down unit 240 The other end of the is coupled to the node X2 (which corresponds to the i-th scan signal OUT(i)), and the node X2 is coupled to the i-th gate line.

The precharging unit 210 receives the input signals IN1, IN2, and outputs the precharging signal PC(i) to the node X1 according to the input signals IN1, IN2. The precharging unit 210 includes transistors M1 and M2. In the present embodiment, the gate driving circuit 200 is a bidirectional scanning driving circuit, and in each of the shift registers 210(1)-210(M), the control terminal of the transistor M1 receives the input signal IN1, and the first terminal of the transistor M1 receives the input signal IN1. One end of the transistor M1 receives the forward input signal FW, and the second end of the transistor M1 outputs the precharge signal PC(i). The control terminal of the transistor M2 receives the input signal IN2, the first terminal of the transistor M2 receives the reverse input signal BW, the second terminal of the transistor M2 is coupled to the second terminal of the transistor M1, and the second terminal of the transistor M1 is connected to the second terminal of the transistor M2. The two terminals are coupled to the node X1. As used herein, the "control terminal", "first terminal" and "second terminal" of a transistor refer to the gate, source and drain of the transistor, respectively, or refer to the gate, drain and source of the transistor, respectively .

If the shift register 210(i) is the first or second stage shift register (ie i is 1 or 2), the input signal IN1 is the start signal STV1, and the input signal IN2 is the (i+2)th stage The scanning signal OUT(i+2) output by the shift register 210(i+2) (ie, the third-stage scanning signal OUT(3) or the fourth-stage scanning signal OUT(4)). If the shift register 210(i) is any shift register in the 3rd to (M-2)th stage shift registers (that is, i is any positive integer from 3 to (M-2)), then The input signals IN1 and IN2 are respectively the (i-2)-th scan signal OUT(i-2) and the (i+2)-th shift output from the (i-2)-th shift register 210 (i-2) The (i+2)th stage scan signal OUT(i+2) output by the register 210(i+2). If the shift register 210(i) is the (M-1)-th or M-th stage shift register (ie i is (M-1) or M), the input signal IN1 is the (i-2)-th stage shift The scan signal OUT(i-2) output by the register 210(i-2) (that is, the (M-3)th level scan signal OUT(M-3) or the (M-2)th level scan signal OUT(M-2) ), and the input signal IN2 is the end signal STV2.

The pull-up unit 220 is coupled to the precharge unit 210, receives the precharge signal PC(i) and the clock signal CN, and outputs the scan signal OUT(i) to the node X2 according to the precharge signal PC(i) and the clock signal CN, The clock signal CN is any one of the clock signals C1-C4. In the embodiment where M is a multiple of 4, if i is 1, 5, ..., (M-3), the clock signal CN is the clock signal C1; if i is 2, 6, ..., (M-2) , then the clock signal CN is the clock signal C2; if i is 3, 7, ..., (M-1), the clock signal CN is the clock signal C3; if i is 4, 8, ..., M, the clock signal CN is clock signal C4. The pull-up unit 220 includes a transistor M3 and a capacitor Cx. The control terminal of the transistor M3 receives the precharge signal PC(i), the first terminal of the transistor M3 receives the clock signal CN, and the second terminal of the transistor M3 outputs the scan signal OUT(i). The first terminal of the capacitor Cx is coupled to the control terminal of the transistor M3, and the second terminal of the capacitor Cx is coupled to the second terminal of the transistor M3.

The first pull-down unit 230 is coupled to the pre-charge unit 210 and the pull-up unit 220, and receives the pre-charge signal PC(i) and the pull-down control signals GPW1, GPW2, and according to the pre-charge signal PC(i) and the pull-down control signals GPW1, GPW2, GPW2 is used to control whether to pull down and maintain the scan signal OUT(i) at the reference potential. As shown in FIG. 5 , the reference potential in this embodiment is a gate low voltage (VGL), but it is not limited thereto. In the frame time, the pull-down control signals GPW1 and GPW2 are mutually inverse, that is, one of the pull-down control signals GPW1 and GPW2 is at a high level and the other is at a low level. The first pull-down unit 230 includes transistors M4-M8. The control terminal and the first terminal of the transistor M4 are input with the pull-down control signal GPW1. The control terminal of the transistor M5 is input with the pull-down control signal GPW2, the first terminal of the transistor M5 is coupled to the reference potential VGL, the second terminal of the transistor M5 is coupled to the second terminal of the transistor M4, and the second terminal of the transistor M5 is connected to the first terminal of the transistor M4. The two terminals are coupled to the node P. The control terminal of the transistor M6 is coupled to the node X1, the first terminal of the transistor M6 is coupled to the reference potential VGL, and the second terminal of the transistor M6 is coupled to the second terminal of the transistor M4. The control terminal of the transistor M7 is coupled to the second terminal of the transistor M6, the first terminal of the transistor M7 is coupled to the reference potential VGL, and the second terminal of the transistor M7 is coupled to the node X1. The control terminal of the transistor M8 is coupled to the second terminal of the transistor M6, the first terminal of the transistor M8 is coupled to the reference potential VGL, and the second terminal of the transistor M8 is coupled to the node X2. After the shift register 210(i) outputs the scan signal OUT(i) to activate the corresponding pixel row, that is, after the scan signal OUT(i) rises to a high level and maintains for a period of time and then falls to a low level, the node X1 changes from a high level to a low level. The potential drops to a low potential, and the first pull-down unit 230 starts to operate. When the pull-down control signal GPW1 is at a low level and the pull-down control signal GPW2 is at a high level, the node P is at a low level, so that the transistors M7 and M8 are turned off; and when the pull-down control signal GPW1 is at a high level and the pull-down control signal GPW2 is at a low level When the node P is in a high potential state, the transistors M7 and M8 are turned on, so that the potentials of the nodes X1 and X2 are set as the reference potential VGL. In a frame time, after the shift register 210(i) outputs the scan signal OUT(i) to activate the corresponding pixel row, that is, the scan signal OUT(i) rises to a high level and maintains for a period of time before falling to a low level After the voltage level, if the noise signal is coupled to the node X1 and/or the node X2 and causes the potential of the node X1 and/or the node X2 to ripple, the transistors M7 and M8 that are turned on will pull down the nodes X1 and X2 to a low level (for example, The reference potential VGL), that is, the scan signal OUT(i) is pulled down to and maintained at a low level, so that the scan signal OUT(i) is not disturbed by noise.

The second pull-down unit 240 is coupled to the pre-charge unit 210 and the pull-up unit 220, receives the pre-charge signal and the pull-down control signals GPW1, GPW2, and controls whether the scan signal OUT ( i) Pulled down to and maintained at the reference potential VGL. The second pull-down unit 240 includes transistors M9-M13. The control terminal and the first terminal of the transistor M9 are input with the pull-down control signal GPW2. The control terminal of the transistor M10 is input with the pull-down control signal GPW1, the first terminal of the transistor M10 is coupled to the reference potential VGL, the second terminal of the transistor M10 is coupled to the second terminal of the transistor M9, and the second terminal of the transistor M9 is connected to the first terminal of the transistor 10. The two terminals are coupled to the node Q. The control terminal of the transistor M11 is coupled to the node X1, the first terminal of the transistor M11 is coupled to the reference potential VGL, and the second terminal of the transistor M11 is coupled to the second terminal of the transistor M9. The control terminal of the transistor M12 is coupled to the second terminal of the transistor M11, the first terminal of the transistor M12 is coupled to the reference potential VGL, and the second terminal of the transistor M12 is coupled to the node X1. The control terminal of the transistor M13 is coupled to the second terminal of the transistor M11, the first terminal of the transistor M13 is coupled to the reference potential VGL, and the second terminal of the transistor M13 is coupled to the node X2. After the shift register 210(i) outputs the scan signal OUT(i) to activate the corresponding pixel row, that is, after the scan signal OUT(i) rises to a high level and maintains for a period of time and then falls to a low level, the node X1 changes from a high level to a low level. The potential drops to a low potential, and the second pull-down unit 240 starts to operate. When the pull-down control signal GPW1 is at a low level and the pull-down control signal GPW2 is at a high level, the node Q is at a high level, so that the transistors M12 and M13 are turned on to set the potentials of the nodes X1 and X2 as the reference potential VGL; and When the pull-down control signal GPW1 is at a high level and the pull-down control signal GPW2 is at a low level, the node Q is at a low level, so that the transistors M12 and M13 are turned off. In a frame time, after the shift register 210(i) outputs the scan signal OUT(i) to activate the corresponding pixel row, that is, the scan signal OUT(i) rises to a high level and maintains for a period of time before falling to a low level After the voltage level, if the noise signal is coupled to the node X1 and/or the node X2, the turned-on transistors M7 and M8 pull down the nodes X1 and X2 to a low level, that is, the scan signal OUT(i) is pulled down to and maintained at a low level , so that the scanning signal OUT(i) is not disturbed by noise.

The transistors M1-M13 in the shift register 210(i) may be amorphous silicon (amorphous silicon) thin film transistors, low temperature polysilicon (LTPS) thin film transistors, and indium gallium zinc oxide (Indium Gallium Zinc Oxide; IGZO) thin film transistors or other suitable thin film transistors.

It should be noted that the gate driver 130 can be changed to sequentially output the scan signals OUT( 1 ) to OUT(M) to the gate lines in the active region 210 in opposite directions. When the gate driver 130 is forward scanning, that is, when the forward input signal FW is high and the reverse input signal BW is low, STV1 is a start signal and STV2 is an end signal. When the gate driving circuit 200 is in reverse scanning, that is, when the forward input signal FW is at a low level and the reverse input signal BW is at a high level, STV2 is a start signal, STV1 is an end signal, and the clock signal C1 ~C4 is changed to: clock signal C2 lags behind clock signal C1 by 1/4 cycle time, clock signal C3 lags behind clock signal C2 by 1/4 cycle time, and clock signal C4 lags behind clock signal C3 by 1/4 cycle time , so that in the same frame period, the M-th level scan signal OUT(M) is firstly output from the M-th level shift register 132 (M) to the M-th gate line, and then after time t, the (M-th 1) The stage shift register 132 (M-1) outputs the (M-1) stage scanning signal OUT(M-1) to the (M-1) gate line, and then after time t passes, from the (M-1) stage scanning signal OUT(M-1) to the (M-1) gate line The M-2) stage shift register 132 (M-2) outputs the (M-2) stage scan signal OUT(M-2) to the (M-2) gate line, and so on until the first stage The shift register 132(1) outputs the first-stage scanning signal OUT(1) to the first gate line. In the embodiments herein, forward scanning is taken as an example, that is, STV1 is the start signal and STV2 is the end signal. The implementation of the reverse scanning embodiment can be directly derived according to the above description, so it is not repeated here.

FIG. 5 illustrates the arrangement of pixel units and the arrangement of elements in the upper left area A of the display panel 100 . As shown in FIG. 5 , in the upper left area A, the boundary 100E of the display panel 100 and the boundary 110E of the active area 110 are both arc-shaped. There are pixel units P in the active region 110, and each pixel unit P has a thin film transistor TFT and a pixel electrode PX. In addition, a region overlapping with the boundary 110E of the active region 110 also has pixel cells P, such as pixel cells P coupled to the gate line SL(m) and the data line DL(n+6). In this way, the boundary of the display screen is consistent with the boundary 110E of the active area 110 , that is, it is arc-shaped rather than stepped. Each thin film transistor TFT is coupled to the corresponding data line and the gate line, and controls whether to input the data signal provided by the corresponding data line to the pixel electrode PX according to the scan signal provided by the corresponding gate line. The thin film transistor TFT may be an amorphous silicon thin film transistor, a low temperature polysilicon thin film transistor, an indium gallium zinc oxide thin film transistor, or other suitable thin film transistors. The pixel electrode PX is used to generate an electric field with the common electrode (not shown), so that the liquid crystal molecules in the pixel unit P are twisted by the electric field, so that the pixel unit P displays a corresponding gray scale. In the top region of the active region 110 with the arc-shaped edge, the number of the pixel units P coupled to the gate lines gradually increases from top to bottom. As can be seen from FIG. 5 , in the bottom region of the active region 110 with the arc-shaped edge, the number of pixel units P coupled to the gate line SL(m) is smaller than that of the pixel units coupled to the gate line SL(m+1). The number of P, and the number of pixel units P coupled to the gate line SL(m+1) is smaller than the number of pixel units P coupled to the gate line SL(m+2). In contrast, in the bottom region of the active region 110 having the arc-shaped edge, the number of the pixel units P coupled to the gate lines gradually decreases from top to bottom.

Please also refer to FIG. 6 . FIG. 6 illustrates the shift register and component arrangement in the upper left corner area A of the display panel 100 . As shown in FIG. 5 and FIG. 6 , the shift registers 132(m)-132(m+2) are arranged on the clock signal lines L1-L4, the control signal lines PL1, PL2 and the reference potential signal line VL and other lines and the active region 110, and are respectively coupled to the gate lines SL(m)-SL(m+2) through the scan signal output leads WL(m)-WL(m+2) to output the scan signal OUT respectively (m)˜OUT(m+2) to gate lines SL(m)˜SL(m+2). Because the peripheral area 120 is fan-shaped in the upper left corner area A of the display panel 100, the arrangement positions of the shift registers 132(m)-132(m+2) in the horizontal direction (direction X) are different, and the clock signal lines are Lines such as L1-L4, the control signal lines PL1, PL2, and the reference potential signal line VL are not completely parallel to the vertical direction (direction Y). Taking the clock signal trace L1 as an example, the section of the clock signal trace L1 located between the shift registers 132(m) and 132(m+1) in the direction Y includes the first to third parts W1-W3, The first portion W1 and the third portion W3 are respectively parallel to the directions X and Y, and the two ends of the second portion W2 are respectively connected to the first portion W1 and the third portion W3. The included angle θ ₁₂ between the first portion W1 and the second portion W2 and the included angle θ ₂₃ between the second portion W2 and the third portion W3 are both obtuse angles, ie, between 90 degrees and 180 degrees.

It should be noted that the lengths and the included angles θ ₁₂ and θ ₂₃ of the first to third portions W1 ˜ W3 can be adjusted according to the tangent slope of the edge 100E of the display panel 100 and/or the arrangement position of the shift register. In addition, the segment of the clock signal trace L1 located between other adjacent shift registers in the direction Y may also have the first to third parts W1 to W3, and the first to third parts W1 to W3 of each segment The lengths and the included angles θ ₁₂ and θ ₂₃ may be all the same, partially the same or all different. The configurations of other traces (eg, clock signal traces L2-L4, control signal traces PL1, PL2, and/or reference potential signal traces VL, etc.) can also be similar to the configuration of the above-mentioned clock signal trace L1.

In addition, as shown in FIG. 6 , the region between the shift registers 132(m)˜132(m+2) and the active region 110 includes a forward input signal line FWL for providing the forward input signal FW , The reverse input signal wiring BWL used to provide the reverse input signal BW, and the wiring used to output the scanning signals OUT(m-2) to OUT(m+4), etc. respectively. The configuration of the forward input signal trace FWL, the reverse input signal trace BWL and the traces used to output the scan signals OUT(m-2) to OUT(m+4) can also be similar to the clock signal trace L1 ~L4, control signal wiring PL1, PL2 and reference potential signal wiring VL and other wiring configurations. Taking the forward input signal trace FWL as an example, the section of the forward input signal trace FWL located between the shift registers 132(m) and 132(m+1) in the direction Y includes the first to third parts W1 ′˜W3 ′, wherein the first part W1 and the third part W3 are parallel to the directions Y and X respectively, and the two ends of the second part W2 are respectively connected to the first part W1 and the third part W3 . The included angle θ' ₁₂ between the first portion W1 and the second portion W2 and the included angle θ' ₂₃ between the second portion W2 and the third portion W3 are both obtuse angles, ie, between 90 degrees and 180 degrees.

Similarly, the lengths and included angles θ ₁₂ , θ ₂₃ of the first to third portions W1 ˜ W3 can be adjusted according to the tangent slope of the edge 110E of the display panel 110 and/or the arrangement position of the shift register. In addition, the segment of the forward input signal trace FWL located between other adjacent shift registers in the direction Y may also have the first to third parts W1 ′ to W3 ′, and the first to third parts of each segment The lengths and the included angles θ' ₁₂ and θ' ₂₃ of the parts W1 ′ to W3 ′ may be all the same, partially the same or all different. The configurations of other traces (such as the reverse input signal trace BWL and/or traces used to output the scan signals OUT(m-2) to OUT(m+4) respectively) can also be configured with the above forward input signal traces The configuration of the FWL is similar.

In the upper left corner area A of the display panel 100, the upper shift register has a larger space than the lower shift register. Therefore, under the premise that the sizes of all the shift registers and the horizontal distance from the border 100A of the display panel 100 are approximately the same, the length of the scan signal output leads coupled to the upper shift register is greater than that of the lower shift register coupling The length of the scan signal output leads. For example, as shown in FIG. 6 , the scan signal output leads WL(m)˜WL(m+2) are respectively coupled to the traces for outputting scan signals OUT(m)˜OUT(m+2), wherein The length LW1 of the scan signal output lead WL(m) is greater than the length LW2 of the scan signal output lead WL(m+1), and the length LW2 of the scan signal output lead WL(m+1) is greater than the scan signal output lead WL(m+2 ) of length LW3.

In addition, there is also a signal output lead between adjacent shift registers, which is coupled to a plurality of adjacent shift registers and the reference potential signal line VL, so as to provide the reference potential VGL to the shift register. As shown in FIG. 6, the reference potential signal lead VWL1 is disposed between the shift registers 132(m), 132(m+1) and is coupled to the shift registers 132(m), 132(m+1) and the reference The potential signal line VL, and the reference potential signal lead VWL2 are disposed between the shift registers 132(m+1) and 132(m+2) and are coupled to the shift registers 132(m+1) and 132(m +2) and the reference potential signal trace VL. The reference potential signal trace VL, the clock signal traces L1-L4 and the control signal traces PL1, PL2 and other traces belong to different metal layers, and each reference potential signal trace and the reference potential signal trace VL belong to the same metal layer. In some embodiments, the clock signal traces L1-L4, the control signal traces PL1, PL2, the first and second terminals of the transistors M1-M13 in the shift registers 132(1)-132(M) and the pixel unit The source and drain of the thin film transistor TFT in P belong to the first metal layer, and the reference potential signal line VL, the control terminals of the transistors M1-M13 in the shift registers 132(1)-132(M) and the pixel unit P The gate of the thin film transistor TFT belongs to the second metal layer. In this way, adjacent shift registers can be directly connected through the reference potential signal lead without connecting through additional connecting lines or replacing metal layers.

It should be noted that the arrangement of components in the areas such as the lower left corner, upper right corner and lower right corner of the display panel 100 can be adjusted according to the above description of the arrangement of components in the upper left area A, for example, several components (including but not Limited to clock signal traces L1~L4, control signal traces PL1, PL2, reference potential signal traces VL, forward input signal traces FWL and reverse input signal traces BWL and other traces) configuration in the lower left corner area The configuration of the upper left corner area A can be symmetrical up and down.

In addition, the pixel cell arrangement and element configuration shown in FIG. 5 and the shift register and element configuration shown in FIG. 6 can also be applied to the display panel 100 ′ of FIG. 2 . For example, FIG. 5 may also be a shift register and element configuration in the upper left area A of the display panel 100', and FIG. 6 may also be a shift register and an element configuration in the upper left area A of the display panel 100'. Component configuration. Similarly, the arrangement of components in the lower left corner, upper right corner and lower right corner of the display panel 100 ′ can be adjusted according to the above description of the arrangement of components in the upper left corner area A.

The element arrangement in the above-mentioned embodiment can also be applied to a display device in which gate drivers are arranged on the left and right sides respectively. Please refer to FIG. 7 , which is a schematic diagram of a display panel 300 according to some embodiments of the present invention. The display panel 300 may be, for example, a liquid crystal display panel of a twisted nematic type, a horizontal switching type, a fringe field switching type, or a vertical alignment type, but is not limited thereto. The display panel 300 has an active area 310 and a peripheral area 320, and includes gate drivers 330A and 330B in the peripheral area 320, which are used to generate scan signals and respectively transmit the scan signals to the gate lines in the active area 310, so that The pixel units in the active area 310 are driven by the scan signal to display an image at a specific time. As shown in FIG. 7 , the gate drivers 330A and 330B are disposed in the peripheral region 320 and located on two sides of the display panel 300 respectively.

In the embodiment of the present invention, the display panel 300 is a system-integrated glass panel. That is to say, the gate drivers 330A and 330B are fabricated on the active array substrate 302 of the display panel 300 . In this way, the electronic components in the gate drivers 330A and 330B and the electronic components in the active region 310 (eg, thin film transistors, pixel electrodes, etc., but not limited thereto) can be fabricated using the same process.

In addition, the display panel 300 is a special-shaped display panel, that is, the active array substrate 302 is a special-shaped display panel. As shown in FIG. 7 , the shapes of the upper left corner, the lower left corner, the upper right corner and the lower right corner of the display panel 300 are all arcs rather than right angles. In addition, the active area 310 is a special-shaped active area, and the shape of the edge 310E of the active area 310 is similar to the shape of the edge 300E of the display panel 300 . If the size of each pixel unit in the active area 310 is the same, the number of pixel units in each pixel column located at the top and bottom of the active area 310 is smaller than the number of pixel units in other pixel columns in the active area 310 .

Besides the display panel 300 shown in FIG. 7 , the double-side driving display panel of the present invention can also have other forms. For example, please refer to FIG. 8 , which is a schematic diagram of a display panel 300 ′ according to some embodiments of the present invention. As shown in FIG. 8 , the display panel 300 ′ is a special-shaped display panel, that is, the active array substrate 302 ′ is a special-shaped display panel, wherein the upper left corner, the lower left corner, the upper right corner and the lower right corner of the display panel 300 ′ are all arc-shaped rather than rectangular Right angle. In addition, the active area 310' is a special-shaped active area, and the shape of the edge 310E' of the active area 310' is similar to the shape of the edge 300E' of the display panel 300'. Compared to the display panel 300 of FIG. 7 , the display panel 300 ′ of FIG. 8 has a notch in its top region. The gate drivers 330A and 330B of FIG. 8 are respectively the same as the gate drivers 330A and 330B of FIG. 7 , and details are not described here.

FIG. 9 is a schematic diagram of gate drivers 400A, 400B according to an embodiment of the present invention. The gate driver 400A corresponds to the gate driver 330A of FIG. 7 or 8, and includes shift registers 410A(1), 410A(2), . . . , 410A(M), and the gate driver 400B corresponds to FIG. 7 or 8 The gate driver 330A includes shift registers 410B(1), 410B(2), . . . , 410B(M). The shift registers 410A( 1 ), 410A( 2 ), . . . , 410A(M) are used for sequentially outputting the scan signals OUTA( 1 ) to OUTA(M) to the scan lines in the active area 310 . Likewise, the shift registers 410B( 1 ), 410B( 2 ), . . . , 410B(M) are used to sequentially output the scan signals OUTB( 1 ) to OUTB(M) to the scan lines in the active region 310 . In the gate drivers 400A and 400B, the shift registers of the same level output scan signals to the same gate line, that is, the shift registers 410A(1) and 410B(1) are both coupled to the first gate line, and shift the The bit registers 410A( 2 ), 410B( 2 ) are both coupled to the second gate lines . . . etc. to increase the driving capability of the display panel 300 . The equivalent circuits of the shift registers 410A( 1 ) to 410A(M) and 410B( 1 ) to 410B(M) are the same as the equivalent circuits of the shift register 132(i) of FIG. 4 . In addition, the gate driver 600A includes clock signal traces LA1-LA4, a start signal trace SLA1, an end signal trace SLA2, control signal traces PLA1, PLA2 and a reference potential signal trace VLA, while the gate driver 600B includes a clock trace Signal traces LB1-LB4, start signal trace SLB1, end signal trace SLB2, control signal traces PLB1, PLB2 and reference potential signal trace VLB. The signals provided by the clock signal traces LA1 to LA4, the start signal trace SLA1, the end signal trace SLA2, the control signal traces PLA1 and PLA2, and the reference potential signal trace VLA correspond to the clock signal traces L1 to L4 in Figure 3, respectively. , the signal provided by the start signal line SL1, the end signal line SL2, the control signal lines PL1, PL2 and the reference potential signal line VL. Similarly, the signals provided by the clock signal traces LB1 to LB4, the start signal trace SLB1, the end signal trace SLB2, the control signal traces PLB1, PLB2 and the reference potential signal trace VLB respectively correspond to the clock signal traces in FIG. 3 . Signals provided by L1-L4, the start signal line SL1, the end signal line SL2, the control signal lines PL1, PL2 and the reference potential signal line VL.

The configuration of the clock signal traces LA1 to LA4, the control signal traces PLA1 and PLA2 and the reference potential signal trace VLA can be the same as the clock signal traces L1 to L4 and the control signal traces PL1 and PL2 shown in FIG. 6 . The configuration is the same as that of the reference potential signal trace VL and other traces. In addition, the gate drivers 330A and 330B are respectively disposed on the left and right sides of the display panel 300, so the configuration of the clock signal lines LB1-LB4, the control signal lines PLB1, PLB2 and the reference potential signal line VLB can be The configuration of the clock signal traces LA1 to LA4, the control signal traces PLA1 and PLA2, and the reference potential signal trace VLA is mirror-symmetrical in the direction Y. In addition, although not shown in FIG. 9 , those skilled in the art should directly know from this article that the configuration of other elements of the gate driver 330A can be the same as the configuration of other elements of the gate driver 130 , and the gate driver 330B The arrangement of the other elements of the gate driver 330A can be mirror-symmetrical in the direction Y with the arrangement of the other elements of the gate driver 330A, so the elements in the upper left corner area, the lower left corner area, the upper right corner area and the lower right corner area of the display panel 300 For configuration instructions, please refer to the previous paragraphs and will not repeat them here.

FIG. 10 is a schematic diagram of gate drivers 500A, 500B according to an embodiment of the present invention. The gate driver 500A corresponds to the gate driver 330A of FIG. 7 or 8, and includes shift registers 510(1), 510(3), . . . , 510(M-1), and the gate driver 500B corresponds to FIG. 7 or Gate driver 330B of FIG. 8, and it includes shift registers 510(2), 510(4), . . . , 510(M). The combination of the gate driver 500A and the gate driver 500B may be equivalent to the gate driver 130 in FIG. 3 , that is, the shift registers 510(1), 510(3), . . . , 510(M-1) correspond to the gate driver 130 respectively The odd-numbered stage shift registers 132(1), 132(3), . . . , 132(M-1) in the shift registers 510(2), 510(4), . Even-numbered stage shift registers 132(2), 132(4), . . . , 132(M) in the driver 130 .

The shift registers 510(1), 510(2), . . . , 510(M) are used for sequentially outputting the scan signals OUT( 1 ) to OUT(M) to the scan lines in the active region 310 . The equivalent circuits of the shift registers 510( 1 ) to 510(M) are the same as the equivalent circuits of the shift register 132(i) of FIG. 4 . In addition, the gate driver 500A includes clock signal traces L1, L3, a start signal trace SLA1, an end signal trace SLA2, control signal traces PLA1, PLA2 and a reference potential signal trace VLA, while the gate driver 600B includes a clock trace Signal traces L2, L4, start signal trace SLB1, end signal trace SLB2, control signal traces PLB1, PLB2 and reference potential signal trace VLB. The signals provided by the clock signal traces L1 to L4 correspond to the signals provided by the clock signal traces L1 to L4 in FIG. 3 respectively, and the signals provided by the start signal traces SLA1 and SLB1 correspond to the signals provided by the start signal trace SL1 in FIG. 3 . , the signals provided by the end signal traces SLA2 and SLB2 correspond to the signals provided by the end signal traces SL2 in Figure 3, the control signal traces PLA1 and PLB1 correspond to the signals provided by the control signal traces PL1 in Figure 3, and the control signal traces PLA2, PLB2 corresponds to the signal provided by the control signal line PL2 in FIG. 3 , and the signals provided by the reference potential signal lines VLA and VLB correspond to the signal provided by the reference potential signal line VL in FIG. 3 .

The configuration of the clock signal traces L1, L3, the control signal traces PLA1, PLA2 and the reference potential signal trace VLA can be similar to the clock signal traces L1, L3, control signal traces PL1, The configuration of PL2 and reference potential signal traces VL and other traces. In addition, the configuration of the clock signal traces L2, L4, the control signal traces PLB1, PLB2, and the reference potential signal trace VLB can also be similar to the clock signal traces L2, L4 shown in FIG. , Control the configuration of the signal traces PL1, PL2 and the reference potential signal traces VL and other traces. In addition, although not shown in FIG. 10 , those skilled in the art should directly know from this article that the configuration of other elements of the gate driver 330A may be similar to the configuration of other elements of the gate driver 130 , and the gate driver 330B The configuration of the other elements in the display panel 300 can also be similar to the configuration of other elements of the gate driver 130 after being flipped left and right, so the configuration of the elements in the upper left area, lower left area, upper right area and lower right area of the display panel 300 Please refer to the previous paragraphs for description, and will not repeat them here. Please refer to FIG. 11 , which is a schematic diagram of a display panel 600 according to some embodiments of the present invention. Similar to the display panel 300 of FIG. 7 , the display panel 600 may be, but not limited to, a liquid crystal display panel of a twisted nematic type, a horizontal switching type, a fringe field switching type, or a vertical alignment type. The display panel 600 includes an active array substrate 602 and has an active area 610 and a peripheral area 620 , the active area 610 has a plurality of pixel units disposed on the active array substrate 602 , and the peripheral area 620 includes gate drivers 630A, 630B , which are used to generate scan signals and respectively transmit the scan signals to the gate lines in the active region 610 , so that the pixel units in the active region 610 are driven by the scan signals to display images at a specific time. The display panel 600 is a system-integrated glass panel, that is, the gate driver 630A is fabricated on the active array substrate 602 of the display panel 600 . In this way, the electronic components in the gate drivers 630A, 630B and the electronic components in the active region 610 (such as thin film transistors, pixel electrodes, etc., but not limited thereto) can be fabricated using the same process.

The display panel 600 is a special-shaped display panel. Further, as shown in FIG. 11 , the display panel 600 is a circular display panel, and the border 600A of the display panel 600 and the border 610A of the active area 610 are both circles. As shown in FIG. 1 , the upper left corner, the lower left corner, the upper right corner and the lower right corner of the display panel 100 are all arcs rather than right angles. In addition, the active area 110 is a special-shaped active area, and the shape of the edge 110E of the active area 110 is similar to the shape of the edge 100E of the display panel 100 . If the size of each pixel unit in the active area 110 is the same, the number of pixel units in each pixel column located at the top and bottom of the active area 110 is smaller than the number of pixel units in other pixel columns in the active area 110 .

To sum up, the display panel of the present invention includes the substrate array row driver circuit with irregular-shaped active regions, and the substrate array row driver circuit has a special arrangement of components, which facilitates the manufacture of the display panel and can satisfy consumers' expectations of appearance. and performance requirements.

Although the present invention has been described above with examples, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention should be determined by the claims.

Claims (10)

1. A display panel, characterized in that the display panel has a special-shaped active area and a peripheral area, and the display panel comprises: a plurality of pixel units located in the special-shaped active area; a plurality of gate lines located in the shaped active region and respectively coupled to the plurality of pixel units; A substrate array row driver circuit, located in the peripheral region, the substrate array row driver circuit comprising: a plurality of shift registers located in the peripheral region and respectively coupled to the plurality of gate lines; and a plurality of clock signal traces located in the peripheral region and respectively coupled to the plurality of shift registers; Wherein at least one of the plurality of clock signal traces includes first to third parts, and the included angle between the first part and the second part of the clock signal trace is between 90 degrees and 180 degrees, so The included angle between the second portion and the third portion of the clock signal trace is between 90 degrees and 180 degrees. 2 . The display panel of claim 1 , wherein a part of the edge of the irregular-shaped active region is arc-shaped. 3 . 3. The display panel of claim 2, wherein the plurality of shift registers comprises a first shift register and a second shift register, the first shift register and the second shift register The register is respectively coupled to a first gate line and a second gate line of the plurality of gate lines through scan signal output leads, and the number of pixel units coupled to the first gate line is smaller than the number of the pixel units coupled to the first gate line. The number of pixel units coupled to the second gate line, and the length of the scan signal output lead coupled to the first gate line is greater than the length of the scan signal output lead coupled to the second gate line. 4. The display panel of claim 1, wherein each of the shift registers comprises at least one transistor, and the at least one transistor is an amorphous silicon thin film transistor. 5. The display panel of claim 1, further comprising: A reference potential signal trace is located in the peripheral region and is coupled to each of the shift registers, the reference potential signal trace includes first to third parts, and the first part of the reference voltage signal trace is connected to The included angle between the second parts is between 90 degrees and 180 degrees, and the included angle between the second part and the third part of the reference potential signal trace is between 90 degrees and 180 degrees. 6 . The display panel of claim 5 , wherein two adjacent shift registers of the plurality of shift registers further include reference potential signal leads, the reference potential signal leads being coupled to The reference potential signal wiring and the two adjacent shift registers, and the reference potential signal wiring and the reference potential signal wiring belong to the same metal layer. 7 . The display panel of claim 5 , wherein the plurality of shift registers are located between the reference potential signal trace and the special-shaped active region. 8 . 8 . The display panel of claim 1 , wherein the shift registers are located between the at least one clock signal trace and the special-shaped active region. 9 . 9. A display panel, wherein the display panel has a special-shaped active area and a peripheral area, and the display panel comprises: a plurality of pixel units located in the special-shaped active area; a plurality of gate lines located in the shaped active region and respectively coupled to the plurality of pixel units; A substrate array row driver circuit, located in the peripheral region, the substrate array row driver circuit comprising: a plurality of first shift registers located in the peripheral region and respectively coupled to odd-numbered gate lines of the plurality of gate lines; a plurality of second shift registers located in the peripheral region and respectively coupled to even-numbered gate lines of the plurality of gate lines; a plurality of first clock signal traces located in the peripheral region and respectively coupled to the plurality of first shift registers; a plurality of second clock signal traces located in the peripheral region and respectively coupled to the plurality of second shift registers; The plurality of first shift registers and the plurality of second shift registers are respectively located on opposite sides of the shaped active area, the plurality of first clock signal traces and the plurality of second clock signals At least one of the clock signal traces in the signal traces includes first to third parts, the included angle between the first part and the second part of the clock signal traces is between 90 degrees and 180 degrees, the clock signal traces The included angle between the second portion and the third portion of the signal trace is between 90 degrees and 180 degrees. 10. The display panel of claim 9, further comprising: a first reference potential signal trace located in the peripheral region and coupled to each of the first shift registers; and a second reference potential signal trace located in the peripheral region and coupled to each of the second shift registers; Wherein, at least one of the first reference potential signal wiring and the second reference potential signal wiring includes first to third parts, and the first part of the reference potential signal wiring and the third The included angle between the two parts is between 90 degrees and 180 degrees, and the included angle between the second part and the third part of the reference potential signal trace is between 90 degrees and 180 degrees.

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