CN101847374B

CN101847374B - Driving device, shift device, buffer, shift register and driving method

Info

Publication number: CN101847374B
Application number: CN2009100483646A
Authority: CN
Inventors: 郑泰宝; 陈飞
Original assignee: Shanghai Tianma Microelectronics Co Ltd
Current assignee: Shanghai Tianma Microelectronics Co Ltd
Priority date: 2009-03-23
Filing date: 2009-03-23
Publication date: 2012-10-31
Anticipated expiration: 2029-03-23
Also published as: CN101847374A

Abstract

The invention discloses a driving device, a shifting register, a buffer, a liquid crystal display and a driving method, wherein the driving device comprises: the shift unit comprises at least two stages of shift registers connected in series, and the shift register of the nth stage outputs the shift data of the nth stage and the reverse phase data of the shift data of the nth stage according to the shift clock signal of the nth stage, the shift data of the (n-1) th stage and the reverse phase data of the shift data of the (n-1) th stage; and the buffer unit comprises at least two stages of buffers, the buffers are connected with the shift register and output driving signals, and n is a natural number. The shift data are transmitted between the shift registers of the shift unit in a unidirectional mode, so that the buffer of a certain stage has a problem and cannot influence the connected shift register, and the accuracy of the driving device is higher.

Description

Driving device, shift device, buffer, shift register and driving method

Technical Field

The present invention relates to the field of semiconductor manufacturing technologies, and in particular, to a driving device, a shift register, a buffer, a liquid crystal display, and a driving method.

Background

Liquid Crystal Displays (LCDs) have many advantages such as being light and thin, saving energy, and having no radiation, and thus have gradually replaced conventional Cathode Ray Tube (CRT) displays. At present, liquid crystal displays are widely used in electronic devices such as high definition digital televisions, desktop computers, Personal Digital Assistants (PDAs), notebook computers, mobile phones, digital cameras, and the like.

A Liquid Crystal Display (LCD) generally consists of a liquid crystal display panel and a driving circuit outside the liquid crystal display panel. Fig. 1 is an equivalent circuit schematic diagram of a liquid crystal display according to the prior art. As shown in fig. 1, the liquid crystal display includes a liquid crystal display panel 10, a data driving device 20, and a gate driving device 30. The liquid crystal display panel 10 has upper and lower glass substrates, and liquid crystal is provided between the two glass substrates. The data lines 21 and the gate lines 31 are disposed on the lower glass substrate of the liquid crystal display panel 10. The liquid crystal display panel 10 further includes i rows and xj columns of pixel units 11 arranged in a matrix, the driving device 30 is electrically connected to i gate lines 31, the data driving device 20 is electrically connected to j data lines 21, the data lines 21 and the gate lines 31 are arranged in a crossing manner, and the pixel units 11 are provided with a thin-film-transistor (TFT) 12 at each crossing point. The gates of the TFTs 12 in the same row are connected to the same gate line 31, and the TFT12 responds to a scan pulse from the gate line 31. A 1-stage shift module including a 1-stage shift portion and a 1-stage buffer portion, the driving device 30 includes a plurality of stages of shift modules, each row of gate lines 31 corresponds to an output of the 1-stage shift module of the driving device 30, the shift modules are configured to sequentially shift a start pulse of each horizontal period, generate a scan pulse, and output the scan pulse to a gate of a TFT12 in the pixel unit 11 to turn on a corresponding TFT12, and the data driving device 20 is configured to input a voltage to a capacitor connected to the TFT12 through a data line 21.

Fig. 2 is a schematic structural diagram of a conventional gate driving device 30, in which amorphous silicon is used to fabricate the gate driving device 30. The amorphous silicon gate driving device 30 is usually formed by serially connecting a plurality of stages of shift modules, each stage of shift module needs to feed back driving data output by a buffer portion of a next stage of shift module to a shift portion of a previous stage to work, and if a buffer portion of a shift module of a certain stage fails, an error occurs in the output of the entire shift module. For example, the 1 st stage shift module shown in fig. 2 receives the shift data output by the 2 nd stage shift module and outputs the driving data Gate (1) of the stage; the 2 nd stage shift module receives the shift data output by the 3 rd stage shift module and outputs the driving data Gate (2) of the stage; the 3 rd stage shift module receives the shift data output by the 4 th stage shift module and outputs the driving data Gate (3) of the stage; the shift module of the n-1 th stage receives the shift data output from the shift module of the n-th stage and outputs the driving data Gate (n-1) of the stage.

As can be seen from the above analysis, the shift data of the gate driving device of the liquid crystal display in the prior art is transmitted between the shift modules at each stage in a bidirectional manner, the correctness of the output driving data of each stage of shift module depends on the correctness of the output driving data of the next stage of shift module, and if the buffer portion of one stage of the shift module is faulty, the output of the entire shift module is faulty, so the correctness of the prior gate driving device is poor.

Disclosure of Invention

The invention aims to provide a driving device, a shifting register, a buffer, a liquid crystal display and a driving method, which improve the accuracy of the output of the driving device.

In order to solve the above problem, the present invention provides a driving apparatus including:

the shift unit comprises at least two stages of shift registers connected in series, and the shift register of the nth stage outputs the shift data of the nth stage and the reverse phase data of the shift data of the nth stage according to the shift clock signal of the nth stage, the shift data of the (n-1) th stage and the reverse phase data of the shift data of the (n-1) th stage;

and the buffer unit comprises at least two stages of buffers, the buffers are connected with the shift register and output driving signals, and n is a natural number.

Preferably, the nth stage shift register is connected to the nth stage buffer, and the nth stage buffer outputs the nth stage driving signal.

Preferably, the shift register is configured to shift the shift data and the anti-phase data of the shift data, respectively, and includes:

the switch unit is connected with the phase inversion data of the shift data and a shift clock signal and is used for controlling the on and off of the shift register;

the high level output unit is connected with the high level and the switch unit and enables the shift register to output the high level according to the signal output by the switch unit;

and the low level output unit is connected with the low level and the switch unit and enables the shift register to output the low level according to the signal output by the switch unit.

Preferably, the structure of the switch unit is a symmetrical structure, and the symmetrical structure is composed of a first switch unit and a second switch unit which are symmetrical; a first input end of the first switch unit is connected with the shift data, and a second input end of the first switch unit is connected with the clock signal; the first input end of the second switch unit is connected with the inverted phase data of the shift data, and the second input end of the second switch unit is connected with the clock signal.

Preferably, the structure of the high level output unit is a symmetrical structure, the symmetrical structure is composed of a first high level output unit and a second high level output unit which are symmetrical, the input end of the first high level output unit and the input end of the second high level output unit are both connected with a high level, the output end of the first high level output unit is connected with the first output end of the shift register, and the output end of the second high level output unit is connected with the second output end of the shift register.

Preferably, the structure of the low level output unit is a symmetrical structure, the symmetrical structure is composed of a first low level output unit and a second low level output unit which are symmetrical, the input end of the first low level output unit and the input end of the second low level output unit are both connected with a low level, the output end of the first low level output unit is connected with the first output end of the shift register, and the output end of the second low level output unit is connected with the second output end of the shift register.

Preferably, the first switch unit is a first transistor, the second switch unit is a second transistor, the first high-level output unit is a third transistor, the second high-level output unit is a fourth transistor, the first low-level output unit is a fifth transistor, and the second low-level output unit is a sixth transistor.

Preferably, the nth stage shift register in the shift unit includes a plurality of transistors, wherein the source of the first transistor inputs the nth-1 stage shift data, the gate of the first transistor inputs the nth stage shift clock signal, and the drain of the first transistor is coupled to the gate of the third transistor; the source electrode of the second transistor inputs the inverted phase data of the n-1 th level shift data, the grid electrode of the second transistor inputs the nth level shift clock signal, and the drain electrode of the second transistor is coupled with the grid electrode of the fourth transistor; the source electrodes of the third transistor and the fourth transistor are input with high level, the drain electrode of the third transistor is coupled with the first output end of the nth stage shift register, and the drain electrode of the fourth transistor is coupled with the second output end of the nth stage shift register; the grid electrode of the fifth transistor is coupled with the drain electrode of the second transistor, the drain electrode of the fifth transistor is coupled with the drain electrode of the third transistor, and the source electrode of the fifth transistor is input with low level; the grid electrode of the sixth transistor is coupled with the drain electrode of the first transistor, the drain electrode of the sixth transistor is coupled with the drain electrode of the fourth transistor, and the source electrode of the sixth transistor inputs low level.

Preferably, the buffer includes:

the pull-up unit is connected with the buffer clock signal and the output end of the buffer, and enables the buffer to output high level according to the buffer clock signal;

and the pull-down unit comprises a first pull-down unit, a second pull-down unit and a switch unit for controlling the first pull-down unit to be opened and closed, and the buffer outputs a low level according to the buffering clock signal.

Preferably, the pull-up unit is a pull-up transistor, the first pull-down unit is a first pull-down transistor, the second pull-down unit is a second pull-down transistor, and the switch unit for controlling the first pull-down unit to be turned on and off is a switch transistor.

Preferably, the nth buffer of the buffer unit includes a plurality of transistors, wherein a source of a pull-up transistor is coupled to a source of a switch transistor as an input terminal of the nth buffer, the input terminal inputs a second buffered clock signal, a gate of the pull-up transistor inputs nth shifted data, a drain of the pull-up transistor is coupled to an output terminal of the nth buffer, a gate of the switch transistor inputs inverted phase data of the nth shifted data, a drain of the switch transistor is coupled to a gate of a first pull-down transistor, a source of the first pull-down transistor inputs a first buffered clock signal, a drain of the first pull-down transistor and a drain of a second pull-down transistor are coupled to an output terminal of the nth buffer, a gate of the second pull-down transistor inputs the first buffered clock signal, and a source of the second pull-down transistor inputs the second buffered clock signal, and the output end of the nth stage buffer outputs an nth stage driving signal.

Preferably, the nth stage shift register is connected to at least two stages of buffers, and each stage of the buffers outputs a stage of driving signal.

Preferably, the nth stage shift register is connected to the 2 nth stage and the 2n-1 st stage buffer, the 2n-1 st stage buffer outputs the 2n-1 st stage driving signal, and the 2n stage buffer outputs the 2 nth stage driving signal.

Preferably, the buffer includes:

Preferably, the 2n-1 stage buffer of the buffer unit includes a plurality of transistors, wherein,

the source of the pull-up transistor is coupled with the source of the switch transistor to serve as the input end of a 2n-1 level buffer, the input end inputs a first buffer clock signal on the right side, the grid of the pull-up transistor inputs nth level shift data, the drain of the pull-up transistor is coupled with the output end of the 2n-1 level buffer, the grid of the switch transistor inputs the reverse phase data of the nth level shift data, the drain of the switch transistor is coupled with the grid of the first pull-down transistor, the source of the first pull-down transistor inputs a second buffer clock signal on the right side, the drain of the first pull-down transistor and the drain of the second pull-down transistor are coupled with the output end of the 2n-1 level buffer, the grid of the second pull-down transistor inputs the second buffer clock signal on the right side, and the source of the second pull-down transistor inputs the first buffer clock signal on the right side, the output end of the 2n-1 level buffer outputs a 2n-1 level driving signal;

the 2 nth stage buffer of the buffer unit includes a plurality of transistors, wherein a source of a pull-up transistor is coupled to a source of a switch transistor as an input terminal of the 2 nth stage buffer, the input terminal inputs a second buffer clock signal on the left, a gate of the pull-up transistor inputs nth stage shift data, a drain of the pull-up transistor is coupled to an output terminal of the buffer, a gate of the switch transistor inputs inverted phase data of the nth stage shift data, a drain of the switch transistor is coupled to a gate of a first pull-down transistor, a source of the first pull-down transistor inputs a first buffer clock signal on the left, a gate of a second pull-down transistor also inputs the first buffer clock signal on the left, a drain of the first pull-down transistor and a drain of the second pull-down transistor are coupled to an output terminal of the 2 nth stage buffer, and a source electrode of the second pull-down transistor inputs a second buffer clock signal on the left side, and an output end of the 2 nth-stage buffer outputs a 2 nth-stage driving signal.

Preferably, a gate of the second pull-down transistor, a source of the first pull-down transistor, a gate of the first transistor of the nth stage shift register, and a gate of the second transistor of the 2 nth stage buffer are coupled; the source of the pull-up transistor and the source of the second pull-down transistor of the 2 n-th stage buffer are coupled with the gate of the first transistor and the gate of the second transistor of the (n +1) -th stage shift register.

Preferably, the driving device comprises two shifting units, namely a left shifting unit and a right shifting unit; the driving device comprises two buffer units, namely a left buffer unit and a right buffer unit; the left shifting unit is connected with the left buffering unit, a left nth-stage shift register of the left shifting unit is connected with a left nth-stage buffer of the left buffering unit, and the left nth-stage buffer outputs a 2 n-1-stage driving signal according to a left nth-stage buffering clock signal, left nth-stage shifting data and anti-phase data of the left nth-stage shifting data;

the right side shifting unit is connected with the right side buffering unit, a right nth stage shifting register of the right side shifting unit is connected with a right nth stage buffer of the right side buffering unit, and the right nth stage buffer outputs a 2 nth stage driving signal according to a right nth stage buffering clock signal, right nth stage shifting data and reverse phase data of the right nth stage shifting data.

Preferably, the left nth stage buffered clock signal includes a left first buffered clock signal and a left second buffered clock signal; the right nth-stage buffer clock signal comprises a right first buffer clock signal and a right second buffer clock signal;

the left nth buffer comprises a plurality of transistors, wherein a source of a pull-up transistor is coupled with a source of a switch transistor to serve as an input end of the left nth buffer, a left second buffer clock signal is input to the input end, a left nth shift data is input to a grid of the pull-up transistor, a drain of the pull-up transistor is coupled with an output end of the left nth buffer, an inverted phase data of the left nth shift data is input to the grid of the switch transistor, a drain of the switch transistor is coupled with a grid of a first pull-down transistor, a left first buffer clock signal is input to a source of the first pull-down transistor, a drain of the first pull-down transistor and a drain of a second pull-down transistor are coupled with an output end of the left nth buffer, and the left first buffer clock signal is input to a grid of the second pull-down transistor, a source electrode of the second pull-down transistor inputs a left second buffer clock signal, and an output end of the left nth-stage buffer outputs a 2n-1 driving signal;

the nth buffer at the right side of the right buffer unit comprises a plurality of transistors, wherein the source of a pull-up transistor is coupled with the source of a switch transistor and used as the input end of the nth buffer at the right side, the input end inputs a second buffer clock signal at the right side, the grid of the pull-up transistor inputs nth shift data at the right side, the drain of the pull-up transistor is coupled with the output end of the nth buffer at the right side, the grid of the switch transistor inputs the reverse phase data of the nth shift data at the right side, the drain of the switch transistor is coupled with the grid of a first pull-down transistor, the source of the first pull-down transistor inputs a first buffer clock signal at the right side, the drain of the first pull-down transistor and the drain of the second pull-down transistor are coupled with the output end of the nth buffer at the right side, and the grid of the second pull-down transistor inputs the first buffer clock signal at the, the source electrode of the second pull-down transistor inputs a second buffer clock signal on the right side, and the output end of the nth buffer on the right side outputs a 2 nth driving signal.

Preferably, the driving device comprises two shifting units, namely a left shifting unit and a right shifting unit; the driving device comprises two buffer units, namely a left buffer unit and a right buffer unit; the left shifting unit is connected with the left buffering unit and outputs an nth-stage driving signal; and the right shifting unit is connected with the right buffer unit and outputs an nth-stage driving signal.

Preferably, the nth left-side shift register of the left-side shift unit is connected to the nth left-side buffer of the left-side buffer unit, and the nth left-side buffer outputs the nth drive signal; the right nth stage shift register of the right side shift unit is connected with the right nth stage buffer, and the right nth stage buffer outputs an nth stage driving signal.

Preferably, the nth left-side shift register of the left-side shift unit is connected to the 2 nth left-side buffer of the left-side buffer unit and the 2 nth left-side buffer of the left-side buffer unit, the 2 nth left-side buffer outputs the 2 nth driving signal, and the 2 nth left-side buffer outputs the 2 nth 2-1 driving signal;

the nth right-stage shift register of the right-side shift unit is connected with the 2 nth right-stage buffer and the 2 nth right-stage buffer of the right-side buffer unit, the 2 nth right-stage buffer outputs a 2 nth-stage driving signal, and the 2 nth right-stage buffer outputs a 2n-1 driving signal.

Correspondingly, the present invention further provides a shift register for shifting shift data and anti-phase data of the shift data, respectively, comprising: the switch unit is connected with the phase inversion data of the shift data and a shift clock signal and is used for controlling the on and off of the shift register; the high level output unit is connected with the high level and the switch unit and enables the shift register to output the high level according to the signal output by the switch unit; and the low level output unit is connected with the low level and the switch unit and enables the shift register to output the low level according to the signal output by the switch unit.

Preferably, the structure of the switching unit is a symmetrical structure.

Preferably, the symmetrical structure of the switch unit is composed of a first switch unit and a second switch unit which are symmetrical; a first input end of the first switch unit is connected with the shift data, and a second input end of the first switch unit is connected with the clock signal; the first input end of the second switch unit is connected with the inverted phase data of the shift data, and the second input end of the second switch unit is connected with the clock signal.

Preferably, the structure of the high-level output unit is a symmetrical structure.

Preferably, the symmetrical structure of the high-level output unit is composed of a first high-level output unit and a second high-level output unit which are symmetrical, the input end of the first high-level output unit and the input end of the second high-level output unit are both connected with a high level, the output end of the first high-level output unit is connected with the first output end of the shift register, and the output end of the second high-level output unit is connected with the second output end of the shift register.

Preferably, the structure of the low-level output unit is a symmetrical structure.

Preferably, the symmetrical structure of the low level output unit is composed of a first low level output unit and a second low level output unit which are symmetrical, the input end of the first low level output unit and the input end of the second low level output unit are both connected with a low level, the output end of the first low level output unit is connected with the first output end of the shift register, and the output end of the second low level output unit is connected with the second output end of the shift register.

Preferably, the source of the first transistor is used for inputting shifting data, the gate of the first transistor is used for inputting a shifting clock signal, and the drain of the first transistor is coupled with the gate of the third transistor; the source electrode of the second transistor is used for inputting the anti-phase data of the shift data, the grid electrode of the second transistor is used for inputting the shift clock signal, and the drain electrode of the second transistor is coupled with the grid electrode of the fourth transistor; the source electrodes of the third transistor and the fourth transistor are input with high level, the drain electrode of the third transistor is coupled with the first output end of the shift register, and the drain electrode of the fourth transistor is coupled with the second output end of the shift register; the grid electrode of the fifth transistor is coupled with the drain electrode of the second transistor, the drain electrode of the fifth transistor is coupled with the drain electrode of the third transistor, and the source electrode of the fifth transistor is coupled with the input low level; the grid electrode of the sixth transistor is coupled with the drain electrode of the first transistor, the drain electrode of the sixth transistor is coupled with the drain electrode of the fourth transistor, and the source electrode of the sixth transistor inputs low level.

Correspondingly, the invention also provides a shifting device which comprises at least two stages of shifting registers connected in series, wherein the shifting register of the nth stage outputs the shifting data of the nth stage and the inverted bit data of the shifting data of the nth stage according to the shifting clock signal of the nth stage, the shifting data of the (n-1) th stage and the inverted phase data of the shifting data of the (n-1) th stage.

Correspondingly, the invention also provides a buffer comprising:

Preferably, the source of the pull-up transistor is coupled to the source of the switching transistor as an input terminal of the buffer, the input terminal inputs a second buffered clock signal, the gate of the pull-up transistor inputs shift data, the drain of the pull-up transistor is coupled to the output terminal of the buffer, the gate of the switching transistor inputs inverted phase data of the shift data, the drain of the switching transistor is coupled to the gate of the first pull-down transistor, the source of the first pull-down transistor inputs the first buffered clock signal, the drain of the first pull-down transistor and the drain of the second pull-down transistor are coupled to the output terminal of the buffer, the gate of the second pull-down transistor inputs the first buffered clock signal, the source of the second pull-down transistor inputs the second buffered clock signal, and the output terminal of the buffer outputs the driving signal.

Correspondingly, the invention also provides a driving method of the driving device, which comprises the following steps:

inputting shift data of the n-1 th stage and inverted data of the shift data of the n-1 th stage to a shift register of the nth stage, and outputting shift data of the nth stage and inverted data of the shift data of the nth stage according to a shift clock signal of the nth stage and the shift data of the n-1 th stage and the inverted data of the shift data of the n-1 th stage;

and inputting the nth-stage shift data and the inverted data of the nth-stage shift data into an nth-stage buffer, wherein the nth-stage buffer outputs an nth-stage driving signal according to an nth-stage buffering clock signal and the nth-stage shift data and the inverted data of the nth-stage shift data, and n is a natural number.

Preferably, when the high level duration of the nth stage shift data is equal to the period of the nth stage shift clock signal, and the high level duration of the nth stage shift clock signal is half of the period of the nth stage shift clock signal, the output nth stage driving signal is a single pulse signal, and the high level duration of the nth stage driving signal is half of the period of the nth stage shift clock signal.

Preferably, when the high level duration of the nth stage shift data is 2 times the period of the nth stage shift clock signal and the high level duration of the nth stage shift clock signal is half of the period thereof, the output nth stage driving signal is a double pulse signal, and each high level duration is half of the period of the nth stage shift clock signal.

inputting left nth-1 stage shift data and inverted data of the left nth-1 stage shift data to a left nth stage shift register, and outputting left nth-stage shift data and inverted data of the left nth-stage shift data according to a left nth-stage shift clock signal and inverted data of the left nth-1 stage shift data and the left nth-1 stage shift data;

inputting the left nth stage shift data and the inverted data of the left nth stage shift data to a left nth stage buffer, wherein the left nth stage buffer outputs a 2n-1 stage driving signal according to a left nth stage buffer clock signal and the left nth stage shift data and the inverted data of the left nth stage shift data;

inputting right n-1 th-stage shift data and inverted data of the right n-1 th-stage shift data to a right nth-stage shift register, and outputting right nth-stage shift data and inverted data of the right nth-stage shift data according to a right nth-stage shift clock signal and inverted data of the right n-1 th-stage shift data and the right n-1 th-stage shift data;

inputting the right nth-stage shift data and the inverted data of the right nth-stage shift data to a right nth-stage buffer, wherein the right nth-stage buffer outputs a 2 nth-stage driving signal according to a right nth-stage buffer clock signal and the inverted data of the right nth-stage shift data and the right nth-stage shift data;

inputting left nth shift data and inverted data of the left nth shift data to a left nth +1 shift register, and outputting left nth +1 shift data and inverted data of the left nth +1 shift data according to a left nth +1 shift clock signal and inverted data of the left nth shift data and the left nth shift data;

inputting the left n +1 th-stage shift data and the inverted data of the left n +1 th-stage shift data to a left n +1 th-stage buffer, wherein the left n +1 th-stage buffer outputs a 2n + 1-stage driving signal according to a left n +1 th-stage buffer clock signal and the left n +1 th-stage shift data and the inverted data of the left n +1 th-stage shift data and the left n +1 th-stage shift data;

inputting right nth-stage shift data and inverted data of the right nth-stage shift data to a right n +1 th-stage shift register, and outputting right nth + 1-stage shift data and inverted data of the right nth-stage shift data according to a right n +1 th-stage shift clock signal and the inverted data of the right nth-stage shift data and the right nth-stage shift data;

and inputting the right n +1 th-level shift data and the inverted data of the right n +1 th-level shift data to a right n +1 th-level buffer, wherein the right n +1 th-level buffer outputs a 2n + 2-level driving signal according to a right n +1 th-level buffer clock signal, the right n +1 th-level shift data and the inverted data of the right n +1 th-level shift data, and n is a natural number.

Preferably, when the high level duration of the left nth stage shift data is equal to the period of the left nth stage shift clock signal, and the high level duration of the left nth stage shift clock signal is one fourth of the period of the left nth stage shift clock signal, the output 2n-1 th stage driving signal is a single pulse signal, and the high level duration of the output 2n-1 th stage driving signal is one fourth of the period of the left nth stage shift clock signal.

Preferably, when the high level duration of the right nth shift data is equal to the period of the right nth shift clock signal, and the high level duration of the right nth shift clock signal is one fourth of the period of the right nth shift clock signal, the output 2 nth drive signal is a single pulse signal, and the high level duration of the output 2 nth drive signal is one fourth of the period of the right nth shift clock signal.

Preferably, when the high level duration of the left nth stage shift data is 2 times the period of the left nth stage shift clock signal, and the high level duration of the left nth stage shift clock signal is one fourth of the period of the left nth stage shift clock signal, the output 2n-1 th stage driving signal is a double pulse signal, where each high level duration is one fourth of the period of the left nth stage shift clock signal.

Preferably, when the high level duration of the right nth stage shift data is 2 times of the period of the right nth stage shift clock signal, and the high level duration of the right nth stage shift clock signal is one fourth of the period of the right nth stage shift clock signal, the output 2 nth stage driving signal is a double pulse signal, where each high level duration is one fourth of the period of the right nth stage shift clock signal.

inputting the nth-stage shift data and the inverted data of the nth-stage shift data to a 2 n-1-stage buffer, wherein the 2 n-1-stage buffer outputs a 2 n-1-stage driving signal according to a 2 n-1-stage buffering clock signal and the nth-stage shift data and the inverted data of the nth-stage shift data;

inputting the nth-stage shift data and the inverted data of the nth-stage shift data to a 2 nth-stage buffer, wherein the 2 nth-stage buffer outputs a 2 nth-stage driving signal according to a 2 nth-stage buffer clock signal and the nth-stage shift data and the inverted data of the nth-stage shift data;

inputting nth-stage shift data and inverted data of the nth-stage shift data to an n + 1-stage shift register, and outputting the (n +1) -th-stage shift data and the inverted data of the (n +1) -th-stage shift data according to an (n +1) -th-stage shift clock signal and the inverted data of the nth-stage shift data and the nth-stage shift data;

inputting the shift data of the (n +1) th stage and the inverted data of the shift data of the (n +1) th stage to a (2n +1) th stage buffer, the (2n +1) th stage buffer outputting a (2n +1) th stage drive signal according to a (2n +1) th stage buffer clock signal and the inverted data of the shift data of the (n +1) th stage and the shift data of the (n +1) th stage;

inputting the (n +1) th-level shift data and the inverted data of the (n +1) th-level shift data to a (2n +2) th-level buffer, wherein the (2n +2) th-level buffer outputs a (2n +2) th-level drive signal according to a (2n +2) th-level buffer clock signal and the (n +1) th-level shift data and the inverted data of the (n +1) th-level shift data, and n is a natural number.

Preferably, when the high level duration of the nth stage shift data is equal to the cycle of the nth stage shift clock signal, and the high level duration of the nth stage shift clock signal is one fourth of the cycle of the nth stage shift clock signal, the output nth stage driving signal is a single pulse signal, and the high level duration of the nth stage driving signal is one fourth of the cycle of the nth stage shift clock signal.

Preferably, when the high level duration of the nth stage shift data is 2 times of the period of the nth stage shift clock signal, and the high level duration of the nth stage shift clock signal is one fourth of the period of the nth stage shift clock signal, the output nth stage driving signal is a double pulse signal, where each high level duration is one fourth of the period of the nth stage shift clock signal.

Correspondingly, the invention also provides a liquid crystal display comprising the driving device, and further comprises a liquid crystal display panel and a data driving device, wherein the liquid crystal display panel comprises a pixel array with at least 4 pixel units, each pixel unit comprises a thin film transistor, the source electrode of each column of the thin film transistors is connected to the same data line, the data line is connected with the data driving device, the grid electrode of each row of the thin film transistors is connected to the same grid line, and the grid line is connected with the driving device.

Preferably, the driving device includes two of the shift units, and two buffer units respectively connected to the shift units, and the two buffer units are respectively connected to two ends of the gate line.

Preferably, the driving device includes two of the shift units, and two buffer units respectively connected to the shift units, wherein one of the buffer units is connected to the even-numbered gate lines from one end of the gate lines, and the other buffer unit is connected to the odd-numbered gate lines from the other end of the gate lines.

In the above technical solution, the driving device includes a shift unit, the shift unit includes at least two stages of shift registers connected in series, and the shift register of the nth stage outputs the shift data of the nth stage and the inverse phase data of the shift data of the nth stage according to the shift clock signal of the nth stage, the shift data of the (n-1) th stage, and the inverse phase data of the shift data of the (n-1) th stage; and the buffer unit comprises at least two stages of buffers, the buffers are connected with the shift register and output driving signals, and n is a natural number. Compared with the prior art, the invention realizes the generation of the driving signal through the shift register connected in series and the buffer unit connected with the output end of the shift register, and the shift data is transmitted between the shift registers of the shift unit in a single direction, so that the problem of the buffer of a certain stage cannot influence the connected shift register, and the input of the buffer of each stage is provided with the signal by the connected shift register, so that only the output result of the buffer with the problem is wrong, and the results of other stages cannot be influenced, thus leading the accuracy of the driving device to be higher.

Drawings

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings. Like reference numerals refer to like parts throughout the drawings. The drawings are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention.

FIG. 1 is a schematic diagram of a prior art LCD;

fig. 2 is a schematic structural diagram of a gate driver in the prior art;

FIG. 3 is a schematic diagram of an equivalent circuit of a first embodiment of a liquid crystal display according to the present invention;

FIG. 4 is a schematic structural diagram of a gate driving device in the LCD shown in FIG. 3;

FIG. 5 is a circuit diagram of the gate driving device of FIG. 4;

FIG. 6 is a timing diagram of a single pulse operation of the gate driving device shown in FIG. 5;

FIG. 7 is a timing diagram illustrating the operation of the gate driving device shown in FIG. 5;

FIG. 8 is a schematic diagram of an equivalent circuit of a second embodiment of a liquid crystal display according to the invention;

FIG. 9 is a timing diagram of a single pulse operation of the gate driving device in the LCD shown in FIG. 8;

FIG. 10 is a timing diagram of the double-pulse operation of the gate driving device in the LCD shown in FIG. 8;

FIG. 11 is a schematic diagram of an equivalent circuit of a third embodiment of a liquid crystal display according to the invention;

FIG. 12 is a schematic diagram of a gate driving device in a fourth embodiment of an LCD according to the present invention;

FIG. 13 is a timing diagram illustrating a single pulse operation of the gate driving device shown in FIG. 12;

FIG. 14 is a timing diagram illustrating the operation of the gate driving device shown in FIG. 12 with two pulses;

FIG. 15 is a schematic diagram of an equivalent circuit of a fifth embodiment of a liquid crystal display according to the invention;

FIG. 16 is a schematic diagram of an equivalent circuit of an embodiment of a shift register of the present invention;

FIG. 17 is an equivalent circuit diagram of an embodiment of a shifting apparatus of the present invention;

FIGS. 18 and 19 are schematic diagrams of input signals at respective input terminals of the shift register unit of FIG. 17 and corresponding output signals;

FIG. 20 is an equivalent circuit diagram of an embodiment of a buffer of the present invention;

fig. 21 is a flowchart illustrating a driving method according to an embodiment of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein, but rather construed as limited to the embodiments set forth herein.

The present invention provides a driving device including: the shift unit comprises at least two stages of shift registers connected in series, and the shift register of the nth stage outputs the shift data of the nth stage and the reverse phase data of the shift data of the nth stage according to the shift clock signal of the nth stage, the shift data of the (n-1) th stage and the reverse phase data of the shift data of the (n-1) th stage; and the buffer unit comprises at least two stages of buffers, the buffers are connected with the shift register and output driving signals, and n is a natural number.

Correspondingly, the invention also provides a buffer, comprising: the pull-up unit is connected with the buffer clock signal and the output end of the buffer, and enables the buffer to output high level according to the buffer clock signal; and the pull-down unit comprises a first pull-down unit, a second pull-down unit and a switch unit for controlling the first pull-down unit to be opened and closed, and the buffer outputs a low level according to the buffering clock signal.

Correspondingly, the invention also provides a driving method of the driving device, which comprises the following steps: inputting shift data of the n-1 th stage and inverted data of the shift data of the n-1 th stage to a shift register of the nth stage, and outputting shift data of the nth stage and inverted data of the shift data of the nth stage according to a shift clock signal of the nth stage and the shift data of the n-1 th stage and the inverted data of the shift data of the n-1 th stage; and inputting the nth-stage shift data and the inverted data of the nth-stage shift data into an nth-stage buffer, wherein the nth-stage buffer outputs an nth-stage driving signal according to an nth-stage buffering clock signal and the nth-stage shift data and the inverted data of the nth-stage shift data, and n is a natural number.

Correspondingly, the invention also provides a driving method of the driving device, which comprises the following steps: inputting left nth-1 stage shift data and inverted data of the left nth-1 stage shift data to a left nth stage shift register, and outputting left nth-stage shift data and inverted data of the left nth-stage shift data according to a left nth-stage shift clock signal and inverted data of the left nth-1 stage shift data and the left nth-1 stage shift data;

For convenience of explanation, the following embodiments are described in conjunction with the application of the driving device of the present invention as a gate driving device in a liquid crystal display, wherein the driving signal is a gate driving signal.

Example one

FIG. 3 is a schematic diagram of an equivalent circuit of a liquid crystal display according to a first embodiment of the invention. FIG. 4 is a schematic structural diagram of a gate driving device in a first embodiment of a liquid crystal display according to the present invention; fig. 5 is a circuit diagram of the gate driving device in fig. 4. The first embodiment of the liquid crystal display and the embodiment of the gate driving device according to the present invention will be described in detail with reference to fig. 3 to 5.

As shown in fig. 3, the liquid crystal display includes a liquid crystal display panel 100, a gate driving device 200, and a data driving device 300 for driving the liquid crystal display panel 100. Specifically, the liquid crystal display panel 100 includes two substrates disposed opposite to each other and a liquid crystal layer between the two substrates (for simplicity, the physical structure of the liquid crystal display panel not relevant to the present invention is not described in detail), wherein the liquid crystal display panel 100 is divided into i rows and xj columns of pixel units 101 distributed in an array. Each pixel cell 101 has a TFT102 therein. The gates of each row of TFTs 102 are connected to the same gate line 103, and the sources of each column of TFTs 102 are connected to the same data line 104. The drain of each TFT102 is connected to a pixel electrode of the present pixel, which forms a liquid crystal capacitance with the common electrode of the upper substrate. Where i and j are natural numbers.

The gate driving device 200 is connected to the gate line 103 of the liquid crystal display panel 100. The data driving device 300 is connected to the data lines 104 of the liquid crystal display panel 100. When the gate driving device 200 applies a gate driving signal to the gate line 103, the data driver 300 outputs a data signal to the data line 104. In one implementation, the liquid crystal display adopts a working mode of inputting a grid driving signal on one side. Therefore, the gate driving device 200 is disposed on a single side of the liquid crystal display panel 100, and all the gate lines 103 are connected to the gate driving device 200 from the same side of the liquid crystal display panel 100.

As shown in fig. 4, the gate driving device 200 of the liquid crystal display of the present invention includes: a shift unit 310 and a buffer unit 320. Specifically, the shift unit 310 includes at least two shift registers 315 connected in series, where the shift register 315 of the nth stage shifts the shift data Q (n-1) of the (n-1) th stage and the inverse phase data QB (n-1) of the shift data of the (n-1) th stage according to the shift clock signal CLK _ Q (n) of the nth stage, and outputs the shift data Q (n) of the nth stage and the inverse phase data QB (n) of the shift data of the nth stage, for example, the shift data input to the shift register of the first stage is Q (0). The buffer unit 320 includes at least two stages of buffers 325, and the buffers 325 obtain gate driving signals gate (n) according to the nth stage buffer clock signal CLK _ g (n), the nth stage shift data q (n), and its inverted bit data qb (n), where n is a natural number.

Compared with the prior art, the invention realizes the generation of the gate driving signal through the shift register 315 and the buffer 325 connected with the output end of the shift register 315 which are connected in series, and the shift data is transmitted between the shift registers 315 of the shift unit 310 in a single direction, that is, the shift register of the stage does not depend on the data output by the buffer 325 of the next stage, that is, even if the buffer 325 of the stage goes wrong, the result of the shift register 315 connected with the buffer 325 of the other stage is not influenced, so that the accuracy of the output structure of the gate driving device is higher.

In one implementation, the same number of stages of shift registers and buffers are used as the number of gate lines of the liquid crystal display. The nth stage shift register 315 is connected to the nth stage buffer 325. Each stage of shift register 315 shifts the shift data Q (n-1), Q (n +1) and the inverted data QB (n-1), QB (n +1) of the corresponding shift data, outputs Q (n), Q (n +1), Q (n +2) and the corresponding inverted data QB (n), QB (n +1), QB (n +2), and outputs n stages of Gate driving signals Gate (n), Gate (n +1), and Gate (n +2) through the buffer 325. The n-stage shift register 315 is sequentially connected to the n gate lines through n buffers, respectively, and outputs a gate driving signal to the n gate lines.

Specifically, the shift register of the first stage is connected to a first stage buffer, and the first stage buffer is coupled to the gate line connected to the gate of the first row of TFTs. The shift register of the first stage outputs the shifted first stage shift data Q (1) and its inverted bit data QB (1) to the first stage buffer in accordance with the 0 th stage shift data Q (0) and its inverted bit data QB (0), and the 1 st stage shift clock signal CLK _ Q (1). The first stage buffer derives a first stage Gate drive signal Gate (1) from the first stage shift data Q (1) and its inverted bit data QB (1), and the 1 st stage buffered clock signal CLK _ G (1). The first stage buffer outputs a Gate driving signal Gate (1) to the first Gate line.

And so on, the nth stage buffer is coupled with the gate line connected with the gate of the nth row TFT. The shift register of the nth stage outputs shifted nth stage shift data Q (n) and its inverse phase data QB (n-1) to the nth stage buffer according to the (n-1) th stage shift data Q (n-1) and its inverse phase data QB (n-1), and the nth stage shift clock signal CLK _ Q (n). The nth stage buffer obtains the nth stage gate driving signal gate (n) according to the nth stage shift data q (n) and the inverted data qb (n) thereof, and the nth stage buffer clock signal CLK _ g (n). The nth stage buffer outputs a gate driving signal gate (n) to the nth gate line.

And so on, the n +1 th stage buffer is coupled to the gate line connected to the gate of the n +1 th row of TFTs. The shift register of the (n +1) th stage outputs the shifted data Q (n +1) of the (n +1) th stage and the inverted data QB (n +1) thereof to the buffer of the (n +1) th stage in accordance with the shift data Q (n) of the (n) th stage and the inverted data QB (n) thereof, and the (n +1) th stage shift clock signal CLK _ Q (n + 1). The (n +1) th stage buffer obtains the (n +1) th stage Gate driving signal Gate (n +1) from the (n +1) th stage shift data Q (n +1) and its inverted bit data QB (n +1), and the (n +1) th stage buffered clock signal CLK _ G (n + 1). The (n +1) th stage buffer outputs a Gate driving signal Gate (n +1) to the (n +1) th Gate line.

The nth stage of the shift clock signal CLK _ Q (n) is the first clock signal CK or the second clock signal CKB (inverted to CK). In this embodiment, the shift clock signal input to the odd-numbered shift registers is the first clock signal CK, and the shift clock signal input to the even-numbered shift registers is the second clock signal CKB.

Specifically, the shift register is configured to shift the shift data and the anti-phase data of the shift data, respectively, and includes: the switch unit is connected with the phase inversion data of the shift data and a shift clock signal and is used for controlling the on and off of the shift register; the high level output unit is connected with the high level and the switch unit and enables the shift register to output the high level according to the signal output by the switch unit; and the low level output unit is connected with the low level and the switch unit and enables the shift register to output the low level according to the signal output by the switch unit.

The structure of the switch unit is a symmetrical structure, and the symmetrical structure is composed of a first switch unit and a second switch unit which are symmetrical; a first input end of the first switch unit is connected with the shift data, and a second input end of the first switch unit is connected with the clock signal; the first input end of the second switch unit is connected with the inverted phase data of the shift data, and the second input end of the second switch unit is connected with the clock signal.

The structure of the high-level output unit is a symmetrical structure, the symmetrical structure is composed of a first high-level output unit and a second high-level output unit which are symmetrical, the input end of the first high-level output unit and the input end of the second high-level output unit are both connected with a high level, the output end of the first high-level output unit is connected with the first output end of the shift register, and the output end of the second high-level output unit is connected with the second output end of the shift register.

The structure of the low level output unit is a symmetrical structure, the symmetrical structure is composed of a first low level output unit and a second low level output unit which are symmetrical, the input end of the first low level output unit and the input end of the second low level output unit are both connected with a low level, the output end of the first low level output unit is connected with the first output end of the shift register, and the output end of the second low level output unit is connected with the second output end of the shift register.

The first switch unit is a first transistor, the second switch unit is a second transistor, the first high-level output unit is a third transistor, the second high-level output unit is a fourth transistor, the first low-level output unit is a fifth transistor, and the second low-level output unit is a sixth transistor.

Specifically, as shown in fig. 5, any one stage of the shift register 315 in the shift unit 310 includes a plurality of transistors, for example, 6 transistors, wherein a source of the first transistor T1 is a first input terminal, and the n-1 th stage of shift data Q (n-1) is input; the gate of the first transistor T1 is a second input terminal, and the nth stage shift clock signal CLK _ Q is input; the drain of the first transistor T1 is coupled to the gate of the third transistor T3. The source of the second transistor T2 is a third input terminal to which the inverted phase data QB (n-1) of the shift data of the (n-1) th stage is input; the gate of the second transistor T2 is a fourth input terminal to which the nth stage shift clock signal CLK _ Q is input; the drain of the second transistor T2 and the gate of the fourth transistor T4 are coupled. Sources of the third transistor T3 and the fourth transistor T4 are coupled to the high level VGH, a drain of the third transistor T3 is coupled to the first output terminal, and a drain of the fourth transistor T4 is coupled to the second output terminal; a gate of the fifth transistor T5 is coupled to the drain of the second transistor T2, a drain of the fifth transistor T5 is coupled to the drain of the third transistor T3, and a source of the fifth transistor T5 is coupled to the low level VGL; the gate of the sixth transistor T6 is coupled to the drain of the first transistor T1, the drain of the sixth transistor T6 is coupled to the drain of the fourth transistor T4, and the source of the sixth transistor T6 is coupled to the low level VGL.

Compared with the shift register circuit in the prior art, the shift register circuit is simple in structure, the area of the circuit is reduced, and therefore cost is reduced.

Also, the LCD is mainly applied to portable products at present because the products are more emphasized on lightness and thinness of the display, integration capability of the device, better reliability, and low cost, and therefore, a higher demand is also placed on the size of the LCD, and it is necessary to reduce the number of transistors in the LCD driving circuit in order to make the LCD have a smaller size. The shift register has simple circuit and less transistors, thereby saving the area of the substrate and realizing the requirement of reducing the size of the LCD.

Specifically, the buffer includes: the pull-up unit is connected with the buffer clock signal and the output end of the buffer, and enables the buffer to output high level according to the buffer clock signal; and the pull-down unit comprises a first pull-down unit, a second pull-down unit and a switch unit for controlling the first pull-down unit to be opened and closed, and the buffer outputs a low level according to the buffering clock signal.

The pull-up unit is a pull-up transistor, the first pull-down unit is a first pull-down transistor, the second pull-down unit is a second pull-down transistor, and the switch unit for controlling the first pull-down unit to be turned on and off is a switch transistor.

With continued reference to fig. 5, in particular, the nth stage buffer 325 in the buffer unit 320 includes a plurality of transistors, for example, 4 transistors: a pull-up transistor Td1, a switching transistor Td2, a first pull-down transistor Td3 and a second pull-down transistor Td 4. The specific connection mode is as follows: a source of the pull-up transistor Td1 and a source of the switching transistor Td2 are coupled to input a second buffered clock signal as an input of the buffer, specifically, the second buffered clock signal is equal to the second clock signal CKB, a gate of the pull-up transistor Td1 inputs the nth-stage shift data q (n), and a drain of the pull-up transistor Td1 is coupled to the gate driving signal output terminal gate (n); the gate of the switching transistor Td2 inputs the inverted phase data qb (n) of the nth stage shift data, and the drain of the switching transistor is coupled to the gate of the first pull-down transistor Td 3; drains of the first pull-down transistor Td3 and the second pull-down transistor Td4 are also coupled to the gate driving signal output terminal gate (n), and a source of the first pull-down transistor Td3 inputs the first buffered clock signal.

Specifically, the first buffered clock signal is equal to the first clock signal CK, the gate of the second pull-down transistor Td4 also inputs the first buffered clock signal, i.e., the first clock signal CK, and the source of the second pull-down transistor Td4 inputs the second buffered clock signal, i.e., the second clock signal CKB.

Of course, in other embodiments, the specific selection may be performed by ensuring that the input signal at the input end of the buffer and the input signal at the gate end of the second pull-down transistor Td4 are opposite in phase, the source input signal of the second pull-down transistor Td4 and the source input signal of the first pull-down transistor Td3 are opposite in phase, and the gate input end of the first transistor T1 and the gate input end of the second transistor T2 of the shift register and the input signal at the input end of the corresponding buffer are opposite in phase.

The circuit of the buffer 325 has a simpler structure than a conventional buffer circuit, and a pull-down module is composed of a switching transistor Td2, a first pull-down transistor Td3 and a second pull-down transistor Td4, so that the threshold shift of the transistors is reduced, and the service life of the circuit is prolonged.

Fig. 6 is a timing diagram of a single pulse operation of the gate driving device shown in fig. 5. As shown in fig. 6, in the shift register of the nth stage, the shift data Q (n-1) of the (n-1) th stage is inputted to the first input terminal, the first clock signal CK is inputted to the second input terminal, the inverted signal QB (n-1) of the shift data of the (n-1) th stage is inputted to the third input terminal, and the first clock signal CK is also inputted to the fourth input terminal. The first output terminal outputs the nth stage shift bit data Q (n), and the second output terminal outputs the inverted bit data QB (n).

For the nth stage buffer, the input end of the nth stage buffer inputs a second clock signal CKB, the gate of the pull-up transistor inputs nth stage shift data q (n), the gate of the switch transistor Td2 inputs the inverted phase data qb (n) of the nth stage shift data, the source of the first pull-down transistor Td3 inputs the first clock signal CK, the gate of the second pull-down transistor Td4 also inputs the first clock signal CK, and the source of the second pull-down transistor inputs the second clock signal CKB; the nth stage buffer outputs the nth stage gate driving signal gate (n).

In this way, for the (n +1) th stage shift register, the nth stage shift data q (n) is input to the first input terminal, the second clock signal CKB is input to the second input terminal, the inverted signal qb (n) of the nth stage shift data is input to the third input terminal, and the second clock signal CKB is also input to the fourth input terminal. The first output terminal outputs the nth stage shift bit data Q (n +1), and the second output terminal outputs the inverted bit data QB (n + 1).

For the (n +1) th stage buffer, the input end of the buffer inputs a first clock signal CK, the gate of the pull-up transistor inputs the (n +1) th stage shift data Q (n +1), the gate of the switching transistor Td2 inputs the inverted bit data QB (n +1) of the (n +1) th stage shift data, the source of the first pull-down transistor Td3 inputs a second clock signal CKB, the gate of the second pull-down transistor Td4 also inputs the second clock signal CKB, and the source of the second pull-down transistor inputs the first clock signal CK; the n +1 th stage buffer outputs the n +1 th stage Gate driving signal Gate (n + 1).

Fig. 7 is a timing diagram of the double-pulse operation of the gate driving device shown in fig. 5.

As shown in fig. 7, for the nth stage shift register, the first input terminal inputs the shift data Q (n-1) of the (n-1) th stage, the second input terminal inputs the first clock signal CK, the third input terminal inputs the inverted signal QB (n-1) of the shift data of the (n-1) th stage, and the fourth input terminal also inputs the first clock signal CK; for the nth stage buffer, the input terminal thereof inputs the second clock signal CKB, the gate of the pull-up transistor inputs the nth stage shift data q (n), the gate of the switching transistor Td2 inputs the inverted phase data qb (n) of the nth stage shift data, the source of the first pull-down transistor Td3 inputs the first clock signal CK, the gate of the second pull-down transistor Td4 also inputs the first clock signal CK, and the source of the second pull-down transistor inputs the second clock signal CKB.

As can be seen from the above description, the input signal types at the respective input terminals of the shift register and the buffer are the same in the single pulse operation timing and the double pulse operation timing, except that: in the double pulse operation timing shown in fig. 7, the high level duration of the (n-1) th stage shift data Q (n-1) inputted from the first input terminal is 2 times the cycle of the first clock signal CK, and the low level duration of the inverted data QB (n-1) of the (n-1) th stage shift data inputted from the third input terminal is also 2 times the cycle of the first clock signal CK, so that the high level duration of the (n) th stage shift data Q (n) outputted from the nth stage shift register and the low level duration of the inverted data QB (n) thereof are also 2 times the cycle of the first clock signal CK, and accordingly, the (n) th stage gate driving signal gate (n) outputted from the nth stage buffer is a double pulse signal, and at the first pulse, the liquid crystal layer capacitor coupled to the drain of the TFT102 is precharged through the TFT 102; in the second pulse, the liquid crystal layer capacitance coupled to the drain of the TFT102 is further charged through the TFT 102.

By analogy, in the double-pulse working timing, the working principle and timing of the shift register of the (n +1) th stage and the buffer of the (n +1) th stage are not described in detail herein.

Example two

FIG. 8 is a schematic structural diagram of a second embodiment of a liquid crystal display according to the invention.

In this embodiment, the composition and the positional relationship of the elements of the shift unit and the buffer unit in the liquid crystal display panel 100, the data driving device 200, and the gate driving device 300 are the same as those in the first embodiment and are not repeated. The difference from the first embodiment is that: in this embodiment, the liquid crystal display adopts a working mode of inputting gate driving signals from two sides. Specifically, the gate driving device includes two shift units and two buffer units, i.e., a left shift unit, a right shift unit, a left buffer unit, and a right buffer unit. The gate driving device inputs signals to the gate lines from different directions, and in this embodiment, the gate driving device is divided into two parts and disposed at opposite sides of the liquid crystal display panel 100, wherein the left shifting unit is connected to the left buffer unit, disposed at the left side of the liquid crystal display panel 100, and connected to the gates of the TFTs of the odd-numbered row of pixel units, and the left buffer unit outputs the 2n-1 th-level gate driving signal. The right shifting unit is connected with the right buffer unit, is arranged on the right side of the liquid crystal display panel 100, is connected with the grid electrodes of the TFTs of the pixel units in the even rows, and outputs 2 nth-level grid driving signals.

In the gate driver shown in fig. 8, the components and connection of the shift register and the buffer of each stage on the left and right sides are the same as those in fig. 5 of the first embodiment, except that the input signals of the components are different, and the following detailed description is made with reference to fig. 9 and 10.

FIG. 9 is a timing diagram of a single pulse operation of the gate driving device in the LCD shown in FIG. 8.

As shown in fig. 9, for the nth left stage shift register, the first input terminal inputs the (n-1) th left stage shift data Q-L (n-1), the second input terminal inputs the first left clock signal CK-L, the third input terminal inputs the inverted signal QB-L (n-1) of the (n-1) th left stage shift data, and the fourth input terminal also inputs the first left clock signal CK-L; for the left nth stage buffer, the input terminal thereof inputs the left second clock signal CKB-L, the gate of the pull-up transistor Td1 inputs the left nth stage shift data Q-L (n), the gate of the switching transistor Td2 inputs the inverted phase data QB-L (n) of the left nth stage shift data, the source of the first pull-down transistor Td3 inputs the left first clock signal CK-L, the gate of the second pull-down transistor Td4 also inputs the left first clock signal CK-L, and the source of the second pull-down transistor Td4 inputs the left second clock signal CKB-L; the left nth stage buffer outputs a 2n-1 th stage Gate driving signal Gate (2 n-1).

For the nth stage shift register on the right, the first input end inputs shift data Q-R (n-1) of the nth 1 stage on the right, the second input end inputs a first clock signal CK-R on the right, the third input end inputs an inverted signal QB-R (n-1) of the shift data of the nth 1 stage on the right, and the fourth input end also inputs the first clock signal CK-R on the right; for the right nth stage buffer, the input end of the right nth stage buffer inputs a right second clock signal CKB-R, the gate of the pull-up transistor inputs right nth stage shift data Q-R (n), the gate of the switch transistor Td2 inputs inverted phase data QB-R (n) of the right nth stage shift data, the source of the first pull-down transistor Td3 inputs a right first clock signal CK-R, the gate of the second pull-down transistor Td4 also inputs the right first clock signal CK-R, and the source of the second pull-down transistor inputs a right second clock signal CKB-R; the right nth stage buffer outputs a 2 nth stage Gate driving signal Gate (2 n).

In analogy, for the (n +1) th-stage shift register on the left side, the first input end inputs the shift data Q-L (n) of the nth stage on the left side, the second input end inputs the second clock signal CKB-L on the left side, the third input end inputs the inverted signal QB-L (n) of the shift data of the nth stage on the left side, and the fourth input end also inputs the second clock signal CKB-L on the left side; for the left n +1 stage buffer, the input terminal thereof inputs the left first clock signal CK-L, the gate of the pull-up transistor inputs the left n +1 stage shift data Q-L (n +1), the gate of the switching transistor Td2 inputs the inverted phase data QB-L (n +1) of the left n +1 stage shift data, the source of the first pull-down transistor Td3 inputs the left second clock signal CKB-L, the gate of the second pull-down transistor Td4 also inputs the left second clock signal CKB-L, and the source of the second pull-down transistor inputs the left first clock signal CK-L; the left n +1 th stage buffer outputs a 2n +1 th stage Gate driving signal Gate (2n + 1).

For the (n +1) th shift register on the right side, the first input end inputs the shift data Q-R (n) of the nth shift register on the right side, the second input end inputs the second clock signal CKB-R on the right side, the third input end inputs the inverted signal QB-R (n) of the shift data of the nth shift register on the right side, and the fourth input end also inputs the second clock signal CKB-R on the right side; for the right n +1 stage buffer, the input terminal thereof inputs the right first clock signal CK-R, the gate of the pull-up transistor inputs the right n +1 stage shift data Q-R (n +1), the gate of the switching transistor Td2 inputs the inverted phase data QB-R (n +1) of the right n +1 stage shift data, the source of the first pull-down transistor Td3 inputs the right second clock signal CKB-R, the gate of the second pull-down transistor Td4 also inputs the right second clock signal CKB-R, and the source of the second pull-down transistor inputs the right first clock signal CK-R; the right n +1 th stage buffer outputs the 2n +2 th stage Gate driving signal Gate (2n + 2).

For each stage of shift register and its corresponding stage of buffer, when selecting the input signal specifically, it is only necessary to ensure that the phase of the input signal at the input end of the buffer is opposite to that of the input signal at the gate of the second pull-down transistor, and the phase of the clock signal input by the shift register is opposite to that of the input signal at the input end of the corresponding buffer. It should be noted that the signals referred to in the present invention have opposite phases, and some cases are not completely opposite, but only have opposite phases, and the specific case is determined according to the needs and the actual waveform.

FIG. 10 is a timing diagram of the double-pulse operation of the gate driving device in the LCD shown in FIG. 8.

The difference between the single pulse timing and the double pulse timing is similar to that of the first embodiment, and it is easy to understand by those skilled in the art, so that the detailed description is omitted here.

EXAMPLE III

Fig. 11 is a schematic structural diagram of a liquid crystal display according to a third embodiment of the invention.

In this embodiment, the composition and the positional relationship of the elements of the shift unit and the buffer unit in the liquid crystal display panel 100, the data driving device 200, and the gate driving device 300 are the same as those in the first embodiment and are not repeated. The difference from the first embodiment is that: in this embodiment, the gate driving device 200 includes two shift units and two buffer units, i.e., a left shift unit, a right shift unit, a left buffer unit, and a right buffer unit. The left shifting unit is connected with the left buffering unit, and the left buffering unit outputs an nth-level gate driving signal; the right shifting unit is connected with the right buffer unit, and the right buffer unit outputs an nth-level gate driving signal. The component composition and the signal input of the left side shifting unit and the right side shifting unit are completely the same, and the component composition and the signal input of the original components of the left side buffering unit and the right side buffering unit are completely the same.

In this embodiment, the same signal is inputted to each gate line from a different side of the gate line, so that the thin film transistors connected to both sides of the same gate line can be simultaneously turned on. Especially for a large-sized panel, since the panel is relatively large and the gate line is relatively long, if the gate driving device inputs a signal on one side of the gate line, a signal received by the thin film transistor connected to the other side of the gate line of the gate driving device is delayed, so that the present embodiment can solve the delay problem well.

In a specific implementation of the present embodiment, as shown in fig. 11, the right shifting unit and the right buffering unit are connected and disposed on the right side of the liquid crystal display panel 100; the left shift unit is connected to the left buffer unit and disposed on the left side of the liquid crystal display panel 100. The same gate driving signal is input to the pixel array from both the left and right sides, thereby reducing delay and improving accuracy.

Example four

Fig. 12 is a schematic structural diagram of a gate driving device in a fourth embodiment of a liquid crystal display according to the invention.

In this embodiment, the components and the positional relationship of the shift register and the buffer in the liquid crystal display panel, the data driving device, and the gate driving device are the same as those in the first embodiment, and therefore, the description thereof is omitted. The difference from the first embodiment is that: each stage of shift register is connected with at least two stages of buffers, and the at least two stages of buffers output two stages of gate driving signals.

Specifically, the nth (in this embodiment, n is a natural number) stage shift register is connected to the 2n-1 th stage and the 2 n-th stage buffer, the 2n-1 th stage buffer outputs the 2n-1 th stage gate driving signal, and the 2 n-th stage buffer outputs the 2 n-th stage gate driving signal; the (n +1) th stage shift register is connected with the (2(n +1) -1 th stage and the (2(n +1) th stage buffer, the (2(n +1) -1) th stage buffer outputs a (2(n +1) -1) th stage gate driving signal, and the 2(n +1) th stage buffer outputs a 2(n +1) th stage gate driving signal. For example, the 1 st stage shift register is connected with a 1 st stage and a 2 nd stage buffer, the 1 st stage buffer outputs a 1 st stage gate driving signal, and the 2 nd stage buffer outputs a 2 nd stage gate driving signal; the 2 nd stage shift register is connected with the 3 rd stage buffer and the 4 th stage buffer, the 3 rd stage buffer outputs a 3 rd stage gate driving signal, and the 4 th stage buffer outputs a 4 th stage gate driving signal.

In a specific implementation manner of this embodiment, as shown in fig. 12, for the nth stage shift register, the first input terminal inputs the nth-1 stage shift data Q (n-1), the second input terminal inputs the nth stage shift clock signal, the third input terminal inputs the inverted signal QB (n-1) of the nth-1 stage shift data, and the fourth input terminal also inputs the nth stage shift clock signal. The nth stage shift clock signal is the first clock signal CK-L on the left side.

The 2n-1 stage buffer is connected to the nth stage shift register, a source of a pull-up transistor Td1 of the 2n-1 stage buffer and a source of a switching transistor Td2 are coupled as an input of the 2n-1 stage buffer, the input inputs a right first buffer clock signal, a gate of the pull-up transistor Td1 inputs nth stage shift data q (n), a drain of the pull-up transistor Td1 is coupled to an output of the 2n-1 stage buffer, a gate of the switching transistor Td2 inputs inverted phase data qb (n) of nth stage shift data, a drain of the switching transistor Td2 is coupled to a gate of a first pull-down transistor Td3, a source of the first pull-down transistor Td3 is input a right second buffer clock signal, a drain of the first pull-down transistor Td3 and a drain of a second pull-down transistor Td4 are coupled to an output of the 2n-1 stage buffer, the Gate of the second pull-down transistor Td4 also inputs the right second buffered clock signal, the drain of the first pull-down transistor Td3 and the drain of the second pull-down transistor Td4 are coupled to the output of the 2n-1 th buffer, the source of the second pull-down transistor inputs the right first buffered clock signal, and the output of the 2n-1 th buffer outputs the 2n-1 th Gate driving signal Gate (2 n-1). Wherein, the right first buffer clock signal is a right first clock signal CK-R; the right second buffered clock signal is the right second clock signal CKB-R.

A 2 n-th stage buffer is connected to the nth stage shift register, a source of a pull-up transistor Td1 of the 2 n-th stage buffer and a source of a switching transistor Td2 are coupled as an input of the 2 n-th stage buffer, the input inputs a left second buffered clock signal, a gate of the pull-up transistor Td1 inputs an nth stage shift data q (n), a drain of the pull-up transistor Td1 is coupled to an output of the 2 n-th stage buffer, a gate of the switching transistor Td2 inputs an inverted phase data qb (qbn) of the nth stage shift data, a drain of the switching transistor Td2 is coupled to a gate of a first pull-down transistor Td3, a source of the first pull-down transistor Td3 is input a left first buffered clock signal, a gate of the second pull-down transistor Td4 is also input the left first buffered clock signal, a drain of the first pull-down transistor 3 and a drain of the second pull-down transistor Td4 are coupled to an output of the 2 n-th stage buffer, the source of the second pull-down transistor inputs a left second buffered clock signal, and the output end of the 2 nth stage buffer outputs a 2 nth stage Gate driving signal Gate (2 n). Wherein, the first buffer clock signal at the left side is a first clock signal CK-L at the left side; the left second buffered clock signal is the left second clock signal CKB-L.

For the (n +1) th stage shift register, the nth stage shift data q (n) is input to the first input terminal, the (n +1) th stage shift clock signal is input to the second input terminal, the inverted signal qb (n) of the nth stage shift data is input to the third input terminal, and the (n +1) th stage shift clock signal is also input to the fourth input terminal. The (n +1) th stage shift clock signal is the second clock signal CKB-L on the left side.

The 2(n +1) -1 stage buffer is connected to the n +1 th stage shift register, a source of a pull-up transistor Td1 of the 2(n +1) -1 stage buffer and a source of a switching transistor Td2 are coupled as an input terminal of the 2(n +1) -1 stage buffer, the input terminal inputs a second buffered clock signal on the right, a gate of the pull-up transistor Td1 inputs a shift data Q (n +1) of the n +1 th stage, a drain of the pull-up transistor Td1 is coupled to an output terminal of the 2(n +1) -1 stage buffer, a gate of the switching transistor Td2 inputs an inverted bit data QB (n +1) of the shift data of the n +1 th stage, a drain of the switching transistor Td2 is coupled to a gate of a first pull-down transistor Td3, a source of the first pull-down transistor Td3 inputs a first buffered clock signal on the right, the Gate of the second pull-down transistor Td4 also inputs the right second buffered clock signal, the drain of the first pull-down transistor Td3 and the drain of the second pull-down transistor Td4 are coupled to the output of the 2(n +1) -1 th stage buffer, the source of the second pull-down transistor inputs the right second buffered clock signal, and the output of the 2(n +1) -1 th stage buffer outputs the 2(n +1) -1 th stage Gate driving signal Gate (2(n +1) -1). Wherein, the right first buffer clock signal is a right first clock signal CK-R; the right second buffered clock signal is the right second clock signal CKB-R.

A 2(n +1) -th stage buffer is connected to the n + 1-th stage shift register, a source of a pull-up transistor Td1 of the 2(n +1) -th stage buffer and a source of a switching transistor Td2 are coupled as an input of the 2(n +1) -th stage buffer, the input inputs a left first buffer clock signal, a gate of the pull-up transistor Td1 inputs a n + 1-th stage shift data Q (n +1), a drain of the pull-up transistor Td1 is coupled to an output of the 2(n +1) -th stage buffer, a gate of the switching transistor Td2 inputs an inverted bit data QB (n +1) -th stage shift data, a drain of the switching transistor Td2 is coupled to a gate of a first pull-down transistor Td3, a source of the first pull-down transistor Td3 is input a left second buffer clock signal, a drain of the first pull-down transistor 3 is coupled to a drain of a second pull-down transistor 4, and the output of the 2(n +1) -th stage buffer, the Gate of the second pull-down transistor Td4 also inputs the left second buffered clock signal, the drain of the first pull-down transistor Td3 and the drain of the second pull-down transistor Td4 are coupled to the output of the 2(n +1) th stage buffer, the source of the second pull-down transistor inputs the left first buffered clock signal, and the output of the 2(n +1) th stage buffer outputs the 2(n +1) th stage Gate driving signal Gate (2(n + 1)). Wherein, the first buffer clock signal at the left side is a first clock signal CK-L at the left side; the left second buffered clock signal is the left second clock signal CKB-L.

In a specific implementation, as long as the signal inputted to the source of the first pull-down transistor Td3 of each stage buffer is guaranteed to be different from the signal inputted to the input terminal of the stage buffer, one of the other three clock signals except the clock signal inputted to the input terminal of the stage buffer is selected. Moreover, as will be understood by those skilled in the art, each stage of the shift register can select the right first clock signal CK-R or the right second clock signal CKB-R, only by changing the signals of the first input terminal and the third input terminal of the shift register accordingly.

Fig. 13 is a timing diagram of a single pulse operation of the gate driving device shown in fig. 12.

The gate driving signals of the respective stages shown in fig. 13 can be obtained by inputting the corresponding waveform signals shown in fig. 13 to the respective input terminals of the gate driving device shown in fig. 12. Since similar descriptions are provided in the first embodiment, they will not be described in detail. Fig. 14 is a timing diagram of the double pulse operation of the gate driving device shown in fig. 12.

The gate driving signals of the respective stages shown in fig. 14 can be obtained by inputting the corresponding waveform signals shown in fig. 14 to the respective input terminals of the gate driving device shown in fig. 12. Since similar descriptions are provided in the first embodiment, they will not be described in detail.

Of course, in other embodiments, the driving device may be used in other apparatuses as well as other driving devices than a gate driving device, for example, in a display of a CRT as a driving device.

EXAMPLE five

Fig. 15 is a schematic structural diagram of a fifth embodiment of a liquid crystal display according to the invention.

In this embodiment, the composition and the positional relationship of the elements of the shift unit and the buffer unit in the liquid crystal display panel 100, the data driving device 200, and the gate driving device 300 are the same as those in the first embodiment and are not repeated. The difference from the first embodiment is that: in this embodiment, the gate driving device 200 includes two shift units and two buffer units; the first shifting unit is connected with the first buffer unit, the second shifting unit is connected with the second buffer unit, the component composition and the signal input of the first shifting unit and the second shifting unit are completely the same, and the component composition and the signal input of the first buffer unit and the second buffer unit are completely the same.

In the specific implementation of this embodiment, as shown in fig. 11, the same gate driving signal is input to the pixel array from both the left and right sides, so that the delay is reduced and the accuracy is improved.

In addition, in other embodiments, the shift register in the gate driving device of the liquid crystal display may have other structures, but the buffer may have the structure in the above embodiments.

EXAMPLE six

In addition, the present invention also provides a shift register for shifting shift data and anti-phase data of the shift data, respectively, comprising: the switch unit is connected with the phase inversion data of the shift data and a shift clock signal and is used for controlling the on and off of the shift register; the high level output unit is connected with the high level and the switch unit and enables the shift register to output the high level according to the signal output by the switch unit; and the low level output unit is connected with the low level and the switch unit and enables the shift register to output the low level according to the signal output by the switch unit.

Specifically, the shift register includes a plurality of transistors, for example, 6, as shown in fig. 16, wherein a source of the first transistor T1 is a first input terminal, and the shift data Q (n-1) is input; the gate of the first transistor T1 is a second input terminal, and the shift clock signal is input; the drain of the first transistor T1 is coupled to the gate of the third transistor T3. The source of the second transistor T2 is a third input terminal to which the inverted phase data QB (n-1) of the shift data is input; the gate of the second transistor T2 is a fourth input terminal to which the shift clock signal CK is input; the drain of the second transistor T2 and the gate of the fourth transistor T4 are coupled. Sources of the third transistor T3 and the fourth transistor T4 are coupled to a high level VGH, a drain of the third transistor T3 is connected to the first output terminal, and a drain of the fourth transistor T4 is connected to the second output terminal; a gate of the fifth transistor T5 is coupled to the drain of the second transistor T2, a drain of the fifth transistor T5 is coupled to the drain of the third transistor T3, and a source of the fifth transistor T5 is coupled to the low level VGL; the gate of the sixth transistor T6 is coupled to the drain of the first transistor T1, the drain of the sixth transistor T6 is coupled to the drain of the fourth transistor T4, and the source of the sixth transistor T6 is coupled to the low level VGL. The shift clock signal is the first clock signal CK.

The invention also provides a shift device, which comprises at least two stages of shift registers connected in series, wherein the nth stage and the (n +1) th stage of shift registers are shown in fig. 17, and CKB is an inverted clock signal of the clock signal CK.

Fig. 18 and 19 are schematic diagrams of input signals at respective input terminals of the shift register unit shown in fig. 17 and corresponding output signals thereof.

The present invention also provides a buffer comprising: the pull-up unit is connected with the buffer clock signal and the output end of the buffer, and enables the buffer to output high level according to the buffer clock signal; and the pull-down unit comprises a first pull-down unit, a second pull-down unit and a switch unit for controlling the first pull-down unit to be opened and closed, and the buffer outputs a low level according to the buffering clock signal.

Specifically, as shown in fig. 20, the buffer includes a plurality of transistors, for example, 4: a pull-up transistor Td1, a switching transistor Td2, a first pull-down transistor Td3 and a second pull-down transistor Td 4. The specific chain connection mode is as follows: the source of the pull-up transistor Td1 and the source of the switch transistor Td2 are coupled as the input end of the buffer, the input signal is the second buffered clock signal, the gate of the pull-up transistor inputs the shift data q (n), the drain of the pull-up transistor Td1 is coupled to the gate driving signal output end gate (n); the gate of the switching transistor Td2 inputs the inverted phase data qb (n) of the nth stage shift data, and the drain of the switching transistor is coupled to the gate of the first pull-down transistor Td 3; drains of the first pull-down transistor Td3 and the second pull-down transistor Td4 are also coupled to the gate driving signal output terminal gate (n), a source of the first pull-down transistor Td3 inputs the first buffered clock signal, a gate of the second pull-down transistor Td4 also inputs the first buffered clock signal, and a source of the second pull-down transistor inputs the second buffered clock signal. The first buffered clock signal is a first clock signal CK, and the second buffered clock signal is a second clock signal CKB.

The shift signal and the inverted signal of the shift signal in other embodiments of the present invention, and the corresponding clock signal are input to the buffer, so that the gate driving signal corresponding to the situation can be obtained.

In the above embodiments, the first output terminal of the shift register is a shift data output terminal, and the second output terminal is an anti-phase data output terminal of the shift data.

In addition, the invention also discloses a gate driving method, and fig. 21 is a flowchart of an embodiment of the driving method of the invention. This driving method will be described below with reference to fig. 21.

The driving method of the present embodiment includes the steps of:

a: inputting shift data of the n-1 th stage and inverted data of the shift data of the n-1 th stage to a shift register of the nth stage, and outputting shift data of the nth stage and inverted data of the shift data of the nth stage according to a shift clock signal of the nth stage and the shift data of the n-1 th stage and the inverted data of the shift data of the n-1 th stage;

b: and inputting the nth-stage shift data and the inverted data of the nth-stage shift data into an nth-stage buffer, wherein the nth-stage buffer outputs an nth-stage gate driving signal according to an nth-stage buffer clock signal and the nth-stage shift data and the inverted data of the nth-stage shift data.

When the high level duration of the nth level shift data is equal to the period of the nth level shift clock signal, and the high level duration of the nth level shift clock signal is half of the period of the nth level shift clock signal, the output nth level gate driving signal is a single pulse signal, and the high level duration of the nth level gate driving signal is half of the period of the nth level shift clock signal.

Wherein, when the high level duration of the nth stage shift data is 2 times of the period of the nth stage shift clock signal and the high level duration of the nth stage shift clock signal is half of the period thereof, the output nth stage gate driving signal is a double pulse signal, and each high level duration is half of the period of the nth stage shift clock signal.

The invention also discloses another driving method, which comprises the following steps:

a: inputting left nth-1 stage shift data and inverted data of the left nth-1 stage shift data to a left nth stage shift register, and outputting left nth-stage shift data and inverted data of the left nth-stage shift data according to a left nth-stage shift clock signal and inverted data of the left nth-1 stage shift data and the left nth-1 stage shift data;

b: inputting the left nth stage shift data and the inverted data of the left nth stage shift data to a left nth stage buffer, wherein the left nth stage buffer outputs a 2n-1 stage gate driving signal according to a left nth stage buffer clock signal and the inverted data of the left nth stage shift data and the left nth stage shift data;

c: inputting right n-1 th-stage shift data and inverted data of the right n-1 th-stage shift data to a right nth-stage shift register, and outputting right nth-stage shift data and inverted data of the right nth-stage shift data according to a right nth-stage shift clock signal and inverted data of the right n-1 th-stage shift data and the right n-1 th-stage shift data;

d: inputting the right nth stage shift data and the inverted data of the right nth stage shift data to a right nth stage buffer, wherein the right nth stage buffer outputs a 2 nth stage gate driving signal according to a right nth stage buffer clock signal and the inverted data of the right nth stage shift data and the right nth stage shift data;

e: inputting left nth shift data and inverted data of the left nth shift data to a left nth +1 shift register, and outputting left nth +1 shift data and inverted data of the left nth +1 shift data according to a left nth +1 shift clock signal and inverted data of the left nth shift data and the left nth shift data;

f: inputting the left n +1 th-stage shift data and the inverted data of the left n +1 th-stage shift data to a left n +1 th-stage buffer, the left n +1 th-stage buffer outputting a 2n + 1-stage gate driving signal according to a left n +1 th-stage buffer clock signal and the left n +1 th-stage shift data and the inverted data of the left n +1 th-stage shift data and the left n +1 th-stage shift data;

g: inputting right nth-stage shift data and inverted data of the right nth-stage shift data to a right n +1 th-stage shift register, and outputting right nth + 1-stage shift data and inverted data of the right nth-stage shift data according to a right n +1 th-stage shift clock signal and the inverted data of the right nth-stage shift data and the right nth-stage shift data;

h: inputting the right n +1 th-stage shift data and the inverted data of the right n +1 th-stage shift data to a right n +1 th-stage buffer, wherein the right n +1 th-stage buffer outputs a 2n + 2-stage gate driving signal according to a right n +1 th-stage buffer clock signal, the right n +1 th-stage shift data and the inverted data of the right n +1 th-stage shift data;

when the high level duration of the left nth shift data is equal to the period of the left nth shift clock signal, and the high level duration of the left nth shift clock signal is one quarter of the period of the left nth shift clock signal, the output 2n-1 gate driving signal is a single pulse signal, and the high level duration of the output 2n-1 gate driving signal is one quarter of the period of the left nth shift clock signal.

When the high level duration of the right nth shift data is equal to the period of the right nth shift clock signal, and the high level duration of the right nth shift clock signal is one quarter of the period of the right nth shift clock signal, the output 2 nth gate driving signal is a single pulse signal, and the high level duration of the output 2 nth gate driving signal is one quarter of the period of the right nth shift clock signal.

When the high level duration of the left nth stage shift data is 2 times of the period of the left nth stage shift clock signal, and the high level duration of the left nth stage shift clock signal is one fourth of the period of the left nth stage shift clock signal, the output 2n-1 th stage gate driving signal is a double pulse signal, wherein each high level duration is one fourth of the period of the left nth stage shift clock signal.

When the high level duration of the right nth stage shift data is 2 times of the period of the right nth stage shift clock signal, and the high level duration of the right nth stage shift clock signal is one fourth of the period of the right nth stage shift clock signal, the output 2 nth stage gate driving signal is a double pulse signal, where each high level duration is one fourth of the period of the right nth stage shift clock signal.

b: inputting the nth-stage shift data and the inverted data of the nth-stage shift data to a 2 n-1-stage buffer, wherein the 2 n-1-stage buffer outputs a 2 n-1-stage gate driving signal according to a 2 n-1-stage buffer clock signal and the nth-stage shift data and the inverted data of the nth-stage shift data;

c: inputting the nth-stage shift data and the inverted data of the nth-stage shift data to a 2 nth-stage buffer, wherein the 2 nth-stage buffer outputs a 2 nth-stage gate driving signal according to a 2 nth-stage buffer clock signal and the nth-stage shift data and the inverted data of the nth-stage shift data;

d: inputting nth-stage shift data and inverted data of the nth-stage shift data to an n + 1-stage shift register, and outputting the (n +1) -th-stage shift data and the inverted data of the (n +1) -th-stage shift data according to an (n +1) -th-stage shift clock signal and the inverted data of the nth-stage shift data and the nth-stage shift data;

e: inputting the shift data of the (n +1) th stage and the inverted data of the shift data of the (n +1) th stage to a (2n +1) th stage buffer, the (2n +1) th stage buffer outputting a (2n +1) th stage gate driving signal according to a (2n +1) th stage buffer clock signal and the inverted data of the shift data of the (n +1) th stage and the shift data of the (n +1) th stage;

f: inputting the shift data of the (n +1) th stage and the inverted data of the shift data of the (n +1) th stage to a (2n +2) th stage buffer, the (2n +2) th stage buffer outputting a (2n +2) th stage gate driving signal according to a (2n +2) th stage buffer clock signal and the shift data of the (n +1) th stage and the inverted data of the shift data of the (n +1) th stage;

when the high level duration of the nth stage shift data is equal to the cycle of the nth stage shift clock signal, and the high level duration of the nth stage shift clock signal is one quarter of the cycle of the nth stage shift clock signal, the output 2n-1 and 2 nth stage gate driving signals are single pulse signals, and the high level duration of the output 2n-1 and 2 nth stage gate driving signals is one quarter of the cycle of the nth stage shift clock signal.

When the high level duration of the nth stage shift data is 2 times of the period of the nth stage shift clock signal, and the high level duration of the nth stage shift clock signal is one fourth of the period of the nth stage shift clock signal, the output 2n-1 and 2 nth stage gate driving signals are double pulse signals, wherein each high level duration is one fourth of the period of the nth stage shift clock signal.

In the above embodiments, n is a natural number.

The foregoing is merely a preferred embodiment of the invention and is not intended to limit the invention in any manner.

Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Those skilled in the art can make numerous possible variations and modifications to the present invention, or modify equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the present invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the scope of the protection of the technical solution of the present invention, unless the contents of the technical solution of the present invention are departed.

Claims

1. A drive device, comprising:

the buffer unit comprises at least two stages of buffers, the buffers are connected with the shift register and output driving signals, the nth stage of shift register is connected with the nth stage of buffers, the nth stage of buffers output nth stage driving signals, and n is a natural number.

2. The driving apparatus as claimed in claim 1, wherein the shift register for shifting the inverted data of the shift data and the shift data, respectively, comprises:

3. The driving device according to claim 2, wherein the structure of the switching unit is a symmetrical structure composed of a first switching unit and a second switching unit that are symmetrical; a first input end of the first switch unit is connected with the shift data, and a second input end of the first switch unit is connected with the clock signal; the first input end of the second switch unit is connected with the inverted phase data of the shift data, and the second input end of the second switch unit is connected with the clock signal.

4. The driving apparatus as claimed in claim 3, wherein the structure of the high level output unit is a symmetrical structure, the symmetrical structure is composed of a first high level output unit and a second high level output unit which are symmetrical, an input terminal of the first high level output unit and an input terminal of the second high level output unit are both connected to a high level, an output terminal of the first high level output unit is connected to a first output terminal of the shift register, and an output terminal of the second high level output unit is connected to a second output terminal of the shift register.

5. The driving apparatus as claimed in claim 4, wherein the low level output unit has a symmetrical structure, the symmetrical structure is composed of a first low level output unit and a second low level output unit, an input terminal of the first low level output unit and an input terminal of the second low level output unit are connected to a low level, an output terminal of the first low level output unit is connected to the first output terminal of the shift register, and an output terminal of the second low level output unit is connected to the second output terminal of the shift register.

6. The driving apparatus according to claim 5, wherein the first switching unit is a first transistor, the second switching unit is a second transistor, the first high-level output unit is a third transistor, the second high-level output unit is a fourth transistor, the first low-level output unit is a fifth transistor, and the second low-level output unit is a sixth transistor.

7. The drive device according to claim 6,

the nth stage shift register in the shift unit comprises a plurality of transistors, wherein the source electrode of the first transistor inputs nth-1 stage shift data, the grid electrode of the first transistor inputs nth stage shift clock signals, and the drain electrode of the first transistor is coupled with the grid electrode of the third transistor; the source electrode of the second transistor inputs the inverted phase data of the n-1 th level shift data, the grid electrode of the second transistor inputs the nth level shift clock signal, and the drain electrode of the second transistor is coupled with the grid electrode of the fourth transistor; the source electrodes of the third transistor and the fourth transistor are input with high level, the drain electrode of the third transistor is coupled with the first output end of the nth stage shift register, and the drain electrode of the fourth transistor is coupled with the second output end of the nth stage shift register; the grid electrode of the fifth transistor is coupled with the drain electrode of the second transistor, the drain electrode of the fifth transistor is coupled with the drain electrode of the third transistor, and the source electrode of the fifth transistor is input with low level; the grid electrode of the sixth transistor is coupled with the drain electrode of the first transistor, the drain electrode of the sixth transistor is coupled with the drain electrode of the fourth transistor, and the source electrode of the sixth transistor inputs low level.

8. The drive of claim 7, wherein said damper comprises:

9. The driving apparatus as claimed in claim 8, wherein the pull-up unit is a pull-up transistor, the first pull-down unit is a first pull-down transistor, the second pull-down unit is a second pull-down transistor, and the switch unit for controlling the first pull-down unit to turn on and off is a switch transistor.

10. The drive device according to claim 8,

the nth buffer of the buffer unit comprises a plurality of transistors, wherein a source of a pull-up transistor is coupled with a source of a switch transistor to serve as an input end of the nth buffer, a second buffer clock signal is input to the input end, nth shift data is input to a grid of the pull-up transistor, a drain of the pull-up transistor is coupled with an output end of the nth buffer, inverted phase data of the nth shift data is input to the grid of the switch transistor, a drain of the switch transistor is coupled with a grid of a first pull-down transistor, a first buffer clock signal is input to a source of the first pull-down transistor, a drain of the first pull-down transistor and a drain of a second pull-down transistor are coupled with an output end of the nth buffer, the first buffer clock signal is input to a grid of the second pull-down transistor, and a second buffer clock signal is input to a source of the second pull-down transistor, and the output end of the nth stage buffer outputs an nth stage driving signal.

11. The driving device according to claim 1, wherein the nth stage shift register is connected to at least two stages of buffers, and each stage of the buffers outputs one stage of driving signal.

12. The driving apparatus as claimed in claim 11, wherein the nth stage shift register is connected to the 2 nth stage and the 2n-1 st stage buffer, the 2n-1 st stage buffer outputs the 2n-1 st stage driving signal, and the 2n nd stage buffer outputs the 2n nd stage driving signal.

13. The driving apparatus as claimed in claim 12, wherein the shift register for shifting the inverted data of the shift data and the shift data, respectively, comprises:

14. The driving device according to claim 13, wherein the structure of the switching unit is a symmetrical structure composed of a first switching unit and a second switching unit that are symmetrical; a first input end of the first switch unit is connected with the shift data, and a second input end of the first switch unit is connected with the clock signal; the first input end of the second switch unit is connected with the inverted phase data of the shift data, and the second input end of the second switch unit is connected with the clock signal.

15. The driving apparatus as claimed in claim 14, wherein the structure of the high level output unit is a symmetrical structure, the symmetrical structure is composed of a first high level output unit and a second high level output unit which are symmetrical, an input terminal of the first high level output unit and an input terminal of the second high level output unit are both connected to a high level, an output terminal of the first high level output unit is connected to the first output terminal of the shift register, and an output terminal of the second high level output unit is connected to the second output terminal of the shift register.

16. The driving apparatus as claimed in claim 15, wherein the structure of the low level output unit is a symmetrical structure, the symmetrical structure is composed of a first low level output unit and a second low level output unit which are symmetrical, an input terminal of the first low level output unit and an input terminal of the second low level output unit are both connected to a low level, an output terminal of the first low level output unit is connected to the first output terminal of the shift register, and an output terminal of the second low level output unit is connected to the second output terminal of the shift register.

17. The driving apparatus as claimed in claim 16, wherein the first switching unit is a first transistor, the second switching unit is a second transistor, the first high-level output unit is a third transistor, the second high-level output unit is a fourth transistor, the first low-level output unit is a fifth transistor, and the second low-level output unit is a sixth transistor.

18. The drive device according to claim 17,

the nth stage shift register in the shift unit includes a plurality of transistors, wherein,

the source electrode of the first transistor inputs the shift data of the (n-1) th level, the grid electrode of the first transistor inputs the shift clock signal of the nth level, and the drain electrode of the first transistor is coupled with the grid electrode of the third transistor; the source electrode of the second transistor inputs the inverted phase data of the n-1 th level shift data, the grid electrode of the second transistor inputs the nth level shift clock signal, and the drain electrode of the second transistor is coupled with the grid electrode of the fourth transistor; the source electrodes of the third transistor and the fourth transistor are input with high level, the drain electrode of the third transistor is coupled with the first output end of the nth stage shift register, and the drain electrode of the fourth transistor is coupled with the second output end of the nth stage shift register; the grid electrode of the fifth transistor is coupled with the drain electrode of the second transistor, the drain electrode of the fifth transistor is coupled with the drain electrode of the third transistor, and the source electrode of the fifth transistor is input with low level; the grid electrode of the sixth transistor is coupled with the drain electrode of the first transistor, the drain electrode of the sixth transistor is coupled with the drain electrode of the fourth transistor, and the source electrode of the sixth transistor inputs low level.

19. The drive of claim 18, wherein said damper comprises:

20. The driving device as claimed in claim 19, wherein the pull-up unit is a pull-up transistor, the first pull-down unit is a first pull-down transistor, the second pull-down unit is a second pull-down transistor, and the switch unit for controlling the first pull-down unit to turn on and off is a switch transistor.

21. The drive of claim 20,

the 2n-1 stage buffer of the buffer unit includes a plurality of transistors, wherein,

the 2 n-th stage buffer of the buffer unit includes a plurality of transistors, wherein,

the source of the pull-up transistor is coupled with the source of the switch transistor to serve as the input end of a 2 nth-stage buffer, the input end inputs a second buffer clock signal on the left side, the gate of the pull-up transistor inputs nth-stage shift data, the drain of the pull-up transistor is coupled with the output end of the buffer, the gate of the switch transistor inputs the anti-phase data of the nth-stage shift data, the drain of the switch transistor is coupled with the gate of the first pull-down transistor, the source of the first pull-down transistor inputs a first buffer clock signal on the left side, the gate of the second pull-down transistor also inputs the first buffer clock signal on the left side, the drain of the first pull-down transistor and the drain of the second pull-down transistor are coupled with the output end of the 2 nth-stage buffer, and the source of the second pull-down transistor inputs a second buffer clock signal on the left, and the output end of the 2 nth stage buffer outputs a 2 nth stage driving signal.

22. The driving apparatus as claimed in claim 21, wherein the gate of the second pull-down transistor, the source of the first pull-down transistor, the gate of the first transistor of the nth stage shift register, and the gate of the second transistor of the 2 nth stage buffer are coupled; the source of the pull-up transistor and the source of the second pull-down transistor of the 2 n-th stage buffer are coupled with the gate of the first transistor and the gate of the second transistor of the (n +1) -th stage shift register.

23. The drive device according to claim 1,

24. The drive device according to claim 1, characterized in that it comprises two said displacement units, respectively a left displacement unit and a right displacement unit; the driving device comprises two buffer units, namely a left buffer unit and a right buffer unit; wherein,

the left shifting unit is connected with the left buffering unit, a left nth-stage shift register of the left shifting unit is connected with a left nth-stage buffer of the left buffering unit, and the left nth-stage buffer outputs a 2 n-1-stage driving signal according to a left nth-stage buffering clock signal, left nth-stage shifting data and anti-phase data of the left nth-stage shifting data;

25. The driving apparatus as claimed in claim 24, wherein the left nth stage buffered clock signals comprise a left first buffered clock signal and a left second buffered clock signal; the right nth-stage buffer clock signal comprises a right first buffer clock signal and a right second buffer clock signal;

26. The drive device according to claim 1, characterized in that it comprises two said displacement units, respectively a left displacement unit and a right displacement unit; the driving device comprises two buffer units, namely a left buffer unit and a right buffer unit; wherein,

the left shifting unit is connected with the left buffering unit and outputs an nth-stage driving signal;

and the right shifting unit is connected with the right buffer unit and outputs an nth-stage driving signal.

27. The driving apparatus as claimed in claim 26, wherein the left nth stage shift register of the left shifting unit is connected to the left nth stage buffer of the left buffering unit, and the left nth stage buffer outputs the nth stage driving signal;

the right nth stage shift register of the right side shift unit is connected with the right nth stage buffer, and the right nth stage buffer outputs an nth stage driving signal.

28. The drive of claim 26,

the nth left-side shift register of the left-side shift unit is connected with the 2 nth left-side buffer of the left-side buffer unit and the 2 nth left-side buffer of the left-side buffer unit, the 2 nth left-side buffer outputs a 2 nth driving signal, and the 2 nth left-side buffer outputs a 2 nth-1 driving signal;

29. A shift register for shifting shift data and inverted data of the shift data, respectively, comprising:

30. The shift register according to claim 29, wherein the structure of the switching unit is a symmetrical structure.

31. The shift register according to claim 30, wherein the symmetrical structure of the switch units is composed of a first switch unit and a second switch unit that are symmetrical; a first input end of the first switch unit is connected with the shift data, and a second input end of the first switch unit is connected with the clock signal; the first input end of the second switch unit is connected with the inverted phase data of the shift data, and the second input end of the second switch unit is connected with the clock signal.

32. The shift register of claim 31, wherein the structure of the high-level output unit is a symmetric structure.

33. The shift register of claim 32, wherein the symmetrical structure of the high level output units is composed of a first high level output unit and a second high level output unit which are symmetrical, an input terminal of the first high level output unit and an input terminal of the second high level output unit are both connected to a high level, an output terminal of the first high level output unit is connected to a first output terminal of the shift register, and an output terminal of the second high level output unit is connected to a second output terminal of the shift register.

34. The shift register of claim 33, wherein the structure of the low-level output unit is a symmetric structure.

35. The shift register of claim 34, wherein the symmetrical structure of the low level output units is composed of a first low level output unit and a second low level output unit which are symmetrical, an input terminal of the first low level output unit and an input terminal of the second low level output unit are both connected to a low level, an output terminal of the first low level output unit is connected to a first output terminal of the shift register, and an output terminal of the second low level output unit is connected to a second output terminal of the shift register.

36. The shift register according to claim 35, wherein the first switching unit is a first transistor, the second switching unit is a second transistor, the first high-level output unit is a third transistor, the second high-level output unit is a fourth transistor, the first low-level output unit is a fifth transistor, and the second low-level output unit is a sixth transistor.

37. The shift register of any one of claims 29 to 36, wherein a source of the first transistor inputs shift data, a gate of the first transistor inputs a shift clock signal, and a drain of the first transistor is coupled to a gate of the third transistor; the source electrode of the second transistor is used for inputting the anti-phase data of the shift data, the grid electrode of the second transistor is used for inputting the shift clock signal, and the drain electrode of the second transistor is coupled with the grid electrode of the fourth transistor; the source electrodes of the third transistor and the fourth transistor are input with high level, the drain electrode of the third transistor is coupled with the first output end of the shift register, and the drain electrode of the fourth transistor is coupled with the second output end of the shift register; the grid electrode of the fifth transistor is coupled with the drain electrode of the second transistor, the drain electrode of the fifth transistor is coupled with the drain electrode of the third transistor, and the source electrode of the fifth transistor is coupled with the input low level; the grid electrode of the sixth transistor is coupled with the drain electrode of the first transistor, the drain electrode of the sixth transistor is coupled with the drain electrode of the fourth transistor, and the source electrode of the sixth transistor inputs low level.

38. A shift device comprising the shift register according to any one of claims 29 to 36, characterized by comprising at least two stages of shift registers connected in series, said shift register of the nth stage outputting shift data of the nth stage and shift data of an inverted phase of shift data of the nth stage in accordance with a shift clock signal of the nth stage, shift data of the (n-1) th stage, and shift data of the (n-1) th stage.

39. A buffer is characterized in that the buffer is connected with a shift register and outputs a driving signal, an nth-stage shift register is connected with an nth-stage buffer, and the nth-stage buffer outputs an nth-stage driving signal, wherein n is a natural number; the shift register of the nth stage outputs the shift data of the nth stage and the reverse phase data of the shift data of the nth stage according to the shift clock signal of the nth stage, the shift data of the (n-1) th stage and the reverse phase data of the shift data of the (n-1) th stage;

the buffer includes:

40. The buffer of claim 39, wherein the pull-up unit is a pull-up transistor, the first pull-down unit is a first pull-down transistor, the second pull-down unit is a second pull-down transistor, and the switch unit for controlling the first pull-down unit to turn on and off is a switch transistor.

41. The buffer of claim 39 or 40, wherein a source of a pull-up transistor and a source of a switch transistor are coupled as an input of the buffer, the input inputs a second buffered clock signal, a gate of the pull-up transistor inputs shift data, a drain of the pull-up transistor is coupled to an output of the buffer, a gate of the switch transistor inputs anti-phase data of the shift data, a drain of the switch transistor is coupled to a gate of a first pull-down transistor, a source of the first pull-down transistor inputs a first buffered clock signal, a drain of the first pull-down transistor and a drain of a second pull-down transistor are coupled to an output of the buffer, a gate of the second pull-down transistor inputs the first buffered clock signal, a source of the second pull-down transistor inputs a second buffered clock signal, the output end of the buffer outputs a driving signal.

42. A driving method comprising the driving apparatus as claimed in any one of claims 1 to 10, characterized by comprising the steps of:

43. The driving method as claimed in claim 42, wherein when the high level duration of the nth stage shift data is equal to the period of the nth stage shift clock signal, and the high level duration of the nth stage shift clock signal is half of the period thereof, the output nth stage driving signal is a single pulse signal, and the high level duration thereof is half of the period of the nth stage shift clock signal.

44. The driving method as claimed in claim 42, wherein when the high level duration of the nth stage shift data is 2 times the period of the nth stage shift clock signal and the high level duration of the nth stage shift clock signal is half of its period, the output nth stage driving signal is a double pulse signal, and wherein each high level duration is half of the period of the nth stage shift clock signal.

45. A driving method comprising a driving device according to any one of claims 24 to 28, characterized by comprising the steps of:

46. The driving method as claimed in claim 45, wherein when the high level duration of the left nth stage shift data is equal to the period of the left nth stage shift clock signal, and the high level duration of the left nth stage shift clock signal is one fourth of the period of the left nth stage shift clock signal, the output 2n-1 th stage driving signal is a single pulse signal, and the high level duration of the single pulse signal is one fourth of the period of the left nth stage shift clock signal.

47. The driving method as claimed in claim 45, wherein when the high level duration of the shifted data of the nth right stage is equal to the period of the shifted clock signal of the nth right stage, and the high level duration of the shifted clock signal of the nth right stage is one quarter of the period of the shifted clock signal of the nth right stage, the output driving signal of the 2 nth stage is a single pulse signal, and the high level duration of the driving signal of the nth right stage is one quarter of the period of the shifted clock signal of the nth right stage.

48. The driving method as claimed in claim 45, wherein when the high level duration of the left nth stage shift data is 2 times the period of the left nth stage shift clock signal, and the high level duration of the left nth stage shift clock signal is one quarter of the period thereof, the output 2n-1 th stage driving signal is a double pulse signal, wherein each high level duration is one quarter of the period of the left nth stage shift clock signal.

49. The driving method as claimed in claim 45, wherein when the high level duration of the shifted data of the nth right stage is 2 times the period of the shifted clock signal of the nth right stage, and the high level duration of the shifted clock signal of the nth right stage is one quarter of the period of the shifted clock signal of the nth right stage, the output driving signal of the 2 nth 2 stage is a double pulse signal, wherein each high level duration is one quarter of the period of the shifted clock signal of the nth right stage.

50. A driving method comprising the driving apparatus as claimed in any one of claims 11 to 22, characterized by comprising the steps of:

51. The driving method according to claim 50, wherein when the high level duration of the nth stage shift data is equal to the period of the nth stage shift clock signal, and the high level duration of the nth stage shift clock signal is one quarter of the period of the nth stage shift clock signal, the output nth stage driving signal is a single pulse signal, and the high level duration of the nth stage driving signal is one quarter of the period of the nth stage shift clock signal.

52. The driving method as claimed in claim 50, wherein when the high level duration of the nth stage shift data is 2 times the period of the nth stage shift clock signal, and the high level duration of the nth stage shift clock signal is a quarter of the period thereof, the output nth stage driving signal is a double pulse signal, wherein each high level duration is a quarter of the period of the nth stage shift clock signal.

53. A liquid crystal display comprising the driving device of claim 1, further comprising a liquid crystal display panel and a data driving device, the liquid crystal display panel comprising a pixel array having at least 4 pixel cells, each pixel cell comprising a thin film transistor, the sources of the thin film transistors in each column being connected to the same data line, the data line being connected to the data driving device, the gates of the thin film transistors in each row being connected to the same gate line, the gate line being connected to the driving device.

54. The liquid crystal display of claim 53, wherein the nth stage shift register is connected to the nth stage buffer, and the nth stage buffer outputs the nth stage driving signal.

55. The liquid crystal display of claim 53, wherein the nth stage shift register is connected to the 2 nth stage and the 2n-1 st stage buffers, the 2n-1 st stage buffer outputting the 2n-1 st stage driving signal, and the 2n stage buffer outputting the 2n stage driving signal.

56. The liquid crystal display device of claim 54 or 55, wherein the driving device comprises two of the shift units, and two buffer units respectively connected to the shift units, the two buffer units being respectively connected to two ends of the gate lines.

57. The liquid crystal display device of claim 54 or 55, wherein the driving device comprises two of the shift units, and two buffer units respectively connected to the shift units, wherein one of the buffer units is connected to the even-numbered gate lines from one end of the gate lines, and the other buffer unit is connected to the odd-numbered gate lines from the other end of the gate lines.