CN110718559B - Array substrate, preparation method and display panel - Google Patents
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/431—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having different compositions, shapes, layouts or thicknesses of gate insulators in different TFTs
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- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/481—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs integrated with passive devices, e.g. auxiliary capacitors
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- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
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Abstract
本发明实施例公开了一种阵列基板、制备方法及显示面板，阵列基板包括基板，基板包括显示区和非显示区，基板上依次设有薄膜晶体管层和第一像素电极层，薄膜晶体管层包括位于显示区内的薄膜晶体管和位于非显示区内的层间介电层，第一像素电极层与薄膜晶体管层连接，层间介电层在基板的非显示区开设有第一过孔；基板的非显示区设有检测器件，包括：栅极金属层，与第一过孔位置对应；源漏极层，位于第一过孔内；第二像素电极层，沉积在源漏极层上，第二像素电极层通过引线与第一像素电极层连接。本发明提供的阵列基板，降低源漏极层与阵列基板层间介电层之间的高度差，使得引线层在源漏极层与层间介电层的交界处不易发生断线，提高检测器件的可靠性。
Embodiments of the present invention disclose an array substrate, a preparation method and a display panel. The array substrate includes a substrate, the substrate includes a display area and a non-display area, and a thin film transistor layer and a first pixel electrode layer are arranged on the substrate in sequence, and the thin film transistor layer includes The thin film transistor located in the display area and the interlayer dielectric layer located in the non-display area, the first pixel electrode layer is connected with the thin film transistor layer, and the interlayer dielectric layer is provided with a first via hole in the non-display area of the substrate; the substrate The non-display area is provided with a detection device, including: a gate metal layer, corresponding to the position of the first via hole; a source and drain layer, located in the first via hole; a second pixel electrode layer, deposited on the source and drain layer, The second pixel electrode layer is connected to the first pixel electrode layer through wires. The array substrate provided by the present invention reduces the height difference between the source-drain layer and the interlayer dielectric layer of the array substrate, so that the lead layer is less likely to be disconnected at the junction of the source-drain layer and the interlayer dielectric layer, thereby improving detection device reliability.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a preparation method and a display panel.
Background
The contact impedance between the drain electrode and the pixel electrode in the display panel determines the power consumption of the driving circuit and the charge-discharge response speed of the pixel, so that after the pixel design of the display panel is completed, the contact impedance between the drain electrode and the pixel electrode needs to be measured. Since the number of the display area films of the panel is large, the direct measurement of the contact impedance between the drain terminal electrode and the pixel electrode damages other films of the display area, and therefore, a detection device is generally disposed in the non-display area of the panel, and the detection device includes a thin film transistor and a pixel electrode, and the pixel electrode is connected to the pixel electrode of the display area through a lead wire to detect the contact impedance between the drain terminal electrode and the pixel electrode.
However, since the number of film layers in the test area of the detection device is larger than that in the wire resistor area, a height difference exists between the leads on the test area and the display area, and the leads are very easy to be broken at the position with the height difference, so that the device fails.
Disclosure of Invention
The embodiment of the invention provides an array substrate, a preparation method and a display panel, and aims to improve the structure of the array substrate, reduce the height difference between a detection device and an interlayer dielectric layer on the array substrate, enable a lead to be difficult to break at the junction of the detection device and the interlayer dielectric layer and improve the reliability of the detection device.
In a first aspect, the application provides an array substrate, the array substrate includes a substrate, the substrate includes a display area and a non-display area, a thin film transistor layer and a first pixel electrode layer are sequentially arranged on the substrate, the thin film transistor layer includes a thin film transistor located in the display area and an interlayer dielectric layer located in the non-display area, the first pixel electrode layer is connected with the thin film transistor layer, and the interlayer dielectric layer is provided with a first via hole in the non-display area of the substrate; the non-display area of the substrate is provided with a detection device, the detection device including:
the first grid metal layer is deposited on the substrate and corresponds to the first through hole in position;
the first source drain layer is deposited on the first grid metal layer and is positioned in the first through hole;
and the second pixel electrode layer is deposited on the source drain electrode layer and is connected with the first pixel electrode layer through a lead.
Optionally, the array substrate further includes a planarization layer, the planarization layer is located between the thin-film transistor layer and the first pixel electrode layer, the planarization layer is provided with a second via hole in the non-display area of the substrate to form a test area, and the first via hole is located in the test area.
Optionally, the leads are deposited on the planarization layer and the interlayer dielectric layer.
Optionally, the area of the first via hole is greater than or equal to the area of the first gate metal layer.
Optionally, the height of the upper surface of the first gate metal layer is less than the height of the interlayer dielectric layer.
Optionally, the height of the upper surface of the first source drain layer is equal to the height of the upper surface of the interlayer dielectric layer.
In a second aspect, the present application provides a method for manufacturing an array substrate, the array substrate including a display region and a non-display region, the method including:
providing a substrate, wherein the substrate comprises a display area and a non-display area;
forming a thin film transistor layer, a first gate layer and a first source drain layer on the substrate, wherein the thin film transistor comprises a thin film transistor positioned in the display area and an interlayer dielectric layer positioned in the non-display area, and the interlayer dielectric layer is provided with a first through hole in the non-display area of the substrate; the first gate metal layer and the first source drain layer are positioned in the non-display area, the first gate layer corresponds to the first via hole in position, and the first source drain layer is positioned in the first via hole and is in contact with the gate layer;
and forming a first pixel electrode layer, a second pixel electrode layer and a lead on the thin film transistor layer, wherein the first pixel electrode layer is connected with the thin film transistor, and the second pixel electrode layer is positioned on the first source drain electrode layer and is connected with the first pixel electrode layer through the lead.
Optionally, before forming the first pixel electrode layer, the second pixel electrode layer, and the lead on the thin film transistor layer, the method further includes:
forming a planarization layer on the thin-film transistor layer;
a second through hole is formed in the position, corresponding to the non-display area, of the planarization layer to form a test area; the first via hole is located in the test area, the first pixel electrode layer is formed on the planarization layer, the second pixel electrode layer is formed on the source drain layer, and the lead is formed on the planarization layer and the interlayer dielectric layer.
Optionally, the forming a thin film transistor, a first gate layer, and a first source drain layer on the substrate includes:
forming a first gate layer and a second gate layer on the substrate;
forming a first source drain layer above the first gate layer;
forming the thin film transistor over the second gate layer.
In a third aspect, the present application further provides a display panel, which includes the array substrate as described in any one of the above.
Has the advantages that: according to the array substrate provided by the embodiment of the invention, the via hole is formed in the interlayer dielectric layer of the array substrate, and the source drain layer is completely deposited in the first via hole, so that the height difference between the source drain layer and the interlayer dielectric layer of the array substrate is reduced, the lead layer is not easy to break at the junction of the source drain layer and the interlayer dielectric layer, and the reliability of a detection device is improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
FIG. 1 is a cross-sectional view of an array substrate according to an embodiment of the present invention;
fig. 2 is a top view of an array substrate according to an embodiment of the present invention;
fig. 3 is a schematic flow chart illustrating a method for manufacturing an array substrate according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, it is to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be considered as limiting the present invention. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise.
In this application, the word "exemplary" is used to mean "serving as an example, instance, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is presented to enable any person skilled in the art to make and use the invention. In the following description, details are set forth for the purpose of explanation. It will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and processes are not shown in detail to avoid obscuring the description of the invention with unnecessary detail. Thus, the present invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
The embodiment of the invention provides an array substrate, a preparation method and a display panel. The following are detailed below.
As shown in fig. 1, a cross-sectional view of an embodiment of an array substrate provided by the present invention includes a substrate 10, the substrate includes a display area and a non-display area, a thin film transistor layer 20 and a first pixel electrode layer 30 are sequentially disposed on the substrate, the thin film transistor layer 20 includes a thin film transistor 201 located in the display area and an interlayer dielectric layer 202 located in the non-display area, the thin film transistor 201 further includes a second gate layer 2011 and a second source drain layer 2012 located in the display area, and the second gate layer and the second source drain layer are connected by a via hole; the thin film transistor 201 further includes other structures, such as an interlayer dielectric layer, a polysilicon layer, an insulating layer, etc., which are not shown; the interlayer dielectric layer 202 has a first via 2021 formed in the non-display region of the substrate. And a detection device is provided in the non-display region of the substrate, wherein the detection device includes:
and a first gate metal layer 40 deposited on the substrate 10 and corresponding to the first via 2021.
And a first source drain layer 50 deposited on the first gate metal layer 40, wherein the first source drain layer 50 is located in the first via 2021.
And a second pixel electrode layer 60 deposited on the first source drain layer 50, the second pixel electrode layer 60 being connected to the first pixel electrode layer 30 through a lead.
According to the array substrate provided by the embodiment of the invention, the first via hole 2021 is formed in the interlayer dielectric layer 202 of the array substrate, and the first source drain layer 50 is completely deposited in the first via hole 2021, so that the height difference between the first source drain layer 50 and the interlayer dielectric layer 202 of the array substrate is reduced, the lead is not easily broken at the junction of the first source drain layer 50 and the interlayer dielectric layer 50, and the reliability of a detection device is improved.
In other embodiments of the present invention, the array substrate may further include a planarization layer 70, the planarization layer 70 is an organic planarization layer, the organic planarization layer 70 is prepared on the interlayer dielectric layer 202, the organic planarization layer 70 is disposed between the thin-film transistor layer 20 and the first pixel electrode layer 30, and the organic planarization layer 70 is used to help the upper surface of the display panel to be at the same height, so as to avoid the display being affected by the unevenness. Meanwhile, the organic planarization layer 70 is provided with a second via hole 701 in the non-display region of the substrate 10 to form a test region, so as to facilitate a subsequent test on the display panel, and the first via hole 2021 is also located in the test region. Other structures of the array substrate are prepared in the second via hole, and reference may be made to the prior art herein, which is not limited herein.
On the basis of the above embodiment, the second pixel electrode layer is deposited on the organic planarization layer 70, and the lead is deposited on the test region formed by the second via hole 701; the second pixel electrode layer 60 is also deposited on the first source drain layer 50, and the leads are used to connect the second pixel electrode layer in the display region and the first pixel electrode layer in the non-display region, and further connect the display panel and the test region for subsequent detection.
In one embodiment of the present invention, the area of the first via 2021 is larger than the area of the first gate metal layer 40. Or in other embodiments of the present invention, the area of the first via 2021 is equal to the area of the first gate metal layer 40.
Specifically, when the area of the first via 2021 is larger than the area of the first gate metal layer 40, the first source drain layer 50 is completely deposited inside the first via 2021, and the area of the first source drain layer 50 is larger than the area of the first gate metal layer 40. Meanwhile, the height of the upper surface of the first source drain layer 50 is equal to the height of the upper surface of the interlayer dielectric layer 202. That is, the height of the upper surface of the first source drain layer 50 is at the same level as the height of the upper surface of the interlayer dielectric layer 202.
As shown in fig. 2, which is a top view of an embodiment of the array substrate provided by the present invention, the planarization layer 70 is located at the outermost periphery of the array substrate, the interlayer dielectric layer 202 is located above the planarization layer 70, and the size of the interlayer dielectric layer 202 is smaller than that of the planarization layer 70. While the first gate metal layer 40 is located inside the interlayer dielectric layer 202, and the first source drain layer 50 is deposited on the first gate metal layer 40, the first gate metal layer 40 and the first source drain layer 50 may be rectangular. A second pixel electrode layer 60 is deposited on the first source drain layer 50, a first pixel electrode layer 30 is deposited on the interlayer dielectric layer 202, and the first pixel electrode layer 30 and the second pixel electrode layer 60 are connected by a lead, that is, the display region and the non-display region of the display panel are connected by a lead.
In some embodiments of the present invention, the gate layer may be made of a metal material such as molybdenum, and the source and drain may be made of an aluminum alloy, specifically, a Ti-Al-Ti alloy.
It should be noted that, in the embodiment of the array substrate, only the above structure is described, and it is understood that, in addition to the above structure, the display panel according to the embodiment of the present invention may further include any other necessary structure as needed, and the specific structure is not limited herein.
The present invention further provides a method for manufacturing an array substrate, where the array substrate includes a display area and a non-display area, as shown in fig. 3, which is a schematic flow chart of an embodiment of the method for manufacturing an array substrate provided by the present invention, and the method includes steps 201 to 203, which are described in detail as follows:
201. a substrate is provided, the substrate including a display region and a non-display region.
202. Forming a thin film transistor layer, a first gate layer and a first source drain layer on a substrate, wherein the thin film transistor comprises a thin film transistor positioned in a display area and an interlayer dielectric layer positioned in a non-display area, and the interlayer dielectric layer is provided with a first through hole in the non-display area of the substrate; the first grid metal layer and the first source drain layer are positioned in the non-display area, the first grid layer corresponds to the first through hole in position, and the first source drain layer is positioned in the first through hole and is in contact with the grid layer.
303. And forming a first pixel electrode layer, a second pixel electrode layer and a lead on the thin film transistor layer, wherein the first pixel electrode layer is connected with the thin film transistor, and the second pixel electrode layer is positioned on the first source drain electrode layer and is connected with the first pixel electrode layer through the lead.
According to the manufacturing method of the array substrate, the via hole is formed in the interlayer dielectric layer of the array substrate, the source drain layer is completely deposited in the first via hole, the height difference between the source drain layer and the interlayer dielectric layer of the array substrate is reduced, the lead layer is not prone to being broken at the junction of the source drain layer and the interlayer dielectric layer, and the reliability of a detection device is improved.
Specifically, after the substrate is provided, a thin film transistor layer and a first pixel electrode layer are sequentially prepared above the substrate, and the thin film transistor layer includes a thin film transistor located in a display area of the display panel and an interlayer dielectric layer located in a non-display area of the display panel. Meanwhile, when the interlayer dielectric layer is prepared, a first through hole is formed in the position, located in the non-display area of the display panel, of the interlayer dielectric layer.
In an embodiment of the present invention, the step 21 of forming a thin film transistor layer, a first gate layer, and a first source drain layer on a substrate may include:
(1) forming a first gate layer and a second gate layer on a substrate;
(2) forming a first source drain layer above the first gate layer;
(3) and forming the thin film transistor above the second gate layer.
Specifically, a gate material layer is coated on a region, corresponding to the first via hole, of the substrate in the non-display region, and a gate material layer is coated on the display region of the display panel; forming a patterned mask layer on the gate material layer; and carrying out a wet etching process to reduce the size of the patterned mask layer, taking the patterned mask layer as a mask, removing part of the gate material layer, and respectively forming a first gate metal layer and a second gate metal layer. After the first grid metal layer located in the non-display area and the second grid metal layer located in the display area are prepared, the first source drain layer is prepared on the first grid metal layer, and the thin film transistor layer is prepared above the second grid metal layer.
In the above embodiments, reference may be made to the prior art for a specific method for fabricating a structure in a display panel such as a thin film transistor, which is not limited herein.
The height of the upper surface of the first gate metal layer after the preparation is finished is smaller than that of the interlayer dielectric layer. Meanwhile, a first source drain layer is deposited on the first gate metal layer, the height of the upper surface of the first source drain layer is equal to that of the upper surface of the interlayer dielectric layer, namely the height of the upper surface of the first source drain layer is at the same horizontal height as that of the upper surface of the interlayer dielectric layer, and the first source drain layer is completely deposited inside the first via hole and is arranged corresponding to the first gate metal layer. Because the height of the upper surface of the first source drain layer is equal to that of the upper surface of the interlayer dielectric layer, the height difference between the upper surface of the first source drain layer and the upper surface of the interlayer dielectric layer is avoided. Meanwhile, the area of the first source drain layer may be greater than or equal to the area of the first gate metal layer.
In an embodiment of the present invention, before forming the first pixel electrode layer, the second pixel electrode layer, and the wire on the thin-film transistor layer in step 22, the method may further include:
forming an organic planarization layer on the thin film transistor layer, wherein the organic planarization layer is provided with a second through hole in a non-display area of the substrate to form a test area, and the first through hole is positioned in the test area; the first pixel electrode layer is formed on the organic planarization layer, the second pixel electrode layer is formed on the source drain layer, and the lead is formed on the organic planarization layer and the interlayer dielectric layer.
Specifically, an organic planarization layer is formed above the thin film transistor, and meanwhile, a second through hole is formed in the non-display area of the substrate of the organic planarization layer to form a test area, so that subsequent tests are facilitated. The first pass is located within the test area. After the preparation of the organic planarization layer is finished, a first pixel electrode layer is prepared and formed above the organic planarization layer, and a second pixel electrode layer is prepared and formed above the first source drain electrode. The lead wire can be prepared with the pixel electrode at the same time, or can be prepared separately after the pixel electrode is finished, and is connected with the first pixel electrode layer and the second pixel electrode layer. The leads may be indium gallium zinc (ITO) material. The prepared lead does not have height difference at the joint of the display area and the non-display area of the display panel, so that the lead is not broken, and the defect of a detection device caused by the broken lead is avoided.
It should be noted that, in the array substrate provided in the embodiments of the present invention, there may be a plurality of detection devices, and the detection devices are connected to the array substrate for detecting defects in the array substrate.
The invention also provides a display panel which comprises the array substrate. The array substrate comprises a substrate 10, wherein the substrate comprises a display area and a non-display area, a thin film transistor layer 20 and a first pixel electrode layer 30 are sequentially arranged on the substrate, and the thin film transistor layer 20 comprises a thin film transistor 201 located in the display area and an interlayer dielectric layer 202 located in the non-display area. The first pixel electrode layer 30 is connected to the thin film transistor layer 20, and the interlayer dielectric layer 202 has a first through hole 2021 in the non-display region of the substrate. And a detection device is provided in the non-display region of the substrate, wherein the detection device includes:
and a first gate metal layer 40 deposited on the substrate 10 and corresponding to the first via 2021.
And a first source drain layer 50 deposited on the first gate metal layer 40, wherein the first source drain layer 50 is located in the first via 2021.
And a second pixel electrode layer 60 deposited on the first source drain layer 50, the second pixel electrode layer 60 being connected to the first pixel electrode layer 30 through a lead.
According to the display panel provided by the invention, the via hole is formed in the interlayer dielectric layer of the array substrate, and the source drain layer is completely deposited in the first via hole, so that the height difference between the source drain layer and the interlayer dielectric layer of the array substrate is reduced, the lead layer is not easy to break at the junction of the source drain layer and the interlayer dielectric layer, and the reliability of a detection device is improved.
In the above embodiments, the descriptions of the respective embodiments have respective emphasis, and parts that are not described in detail in a certain embodiment may refer to the above detailed descriptions of other embodiments, and are not described herein again.
In a specific implementation, each unit or structure may be implemented as an independent entity, or may be combined arbitrarily to be implemented as one or several entities, and the specific implementation of each unit or structure may refer to the foregoing method embodiment, which is not described herein again.
The above operations can be implemented in the foregoing embodiments, and are not described in detail herein.
The above embodiment of the invention provides an array substrate collective preparation method and a display panel, and a specific example is applied to explain the principle and the implementation of the invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the invention; meanwhile, for those skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (8)
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| CN201910885526.5A CN110718559B (en) | 2019-09-19 | 2019-09-19 | Array substrate, preparation method and display panel |
| PCT/CN2019/115879 WO2021051495A1 (en) | 2019-09-19 | 2019-11-06 | Array substrate, manufacturing method, and display panel |
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