CN105870136A - Array substrate, making method thereof and display device - Google Patents

Abstract

Embodiments of the present invention provide an array substrate, a manufacturing method thereof, and a display device, which relate to the field of display technology and can reduce the number of patterning processes used in manufacturing the array substrate. The array substrate includes: a first electrode layer, the first electrode layer includes: a reserved pattern and a first electrode; a gate metal layer located on the first electrode layer, the gate metal layer includes: located on the reserved pattern A gate metal pattern on the top and in direct contact with the reserved pattern; a second electrode layer, the second electrode layer includes: a second electrode opposite to the first electrode, wherein the first electrode is a common An electrode, the second electrode is a pixel electrode; or, the first electrode is a pixel electrode, and the second electrode is a common electrode. The array substrate can be applied in the manufacturing process of the array substrate.

Description

Array substrate, manufacturing method thereof, and display device

technical field

The present invention relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device.

Background technique

As shown in Figure 1, it is a schematic structural diagram of the array substrate in the current display panel. When making the array substrate, at least 5-6 patterning processes are required. The gate insulating layer 05 is formed on the electrode 13, the active layer 02 is formed through a patterning process, the source electrode 11 and the drain electrode 12 are respectively formed through a patterning process, and the pixel electrode 01 is formed through a patterning process, and then the source electrode 11 The passivation layer 04 is formed on the drain electrode 12 and the pixel electrode 01. Finally, the common electrode 03 is formed on the passivation layer 04 through one patterning process. In this way, the above-mentioned array substrate can be obtained through five patterning processes.

It can be seen that the number of patterning processes used in the fabrication of the above-mentioned array substrate is relatively high, thereby increasing the complexity and fabrication cost of the fabrication of the array substrate.

Contents of the invention

The invention provides a method for manufacturing an array substrate, which can reduce the number of patterning processes used in manufacturing the array substrate, and also provides an array substrate and a display device that can support the reduction of the number of patterning processes.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

In one aspect, the present invention provides an array substrate, comprising:

a first electrode layer, the first electrode layer comprising: a reserved pattern and a first electrode;

a gate metal layer on the first electrode layer, the gate metal layer comprising: a gate metal pattern on the reserved pattern and in direct contact with the reserved pattern;

The second electrode layer, the second electrode layer includes: a second electrode disposed opposite to the first electrode, wherein the first electrode is a common electrode, and the second electrode is a pixel electrode; or, the second electrode is a pixel electrode; The first electrode is a pixel electrode, and the second electrode is a common electrode.

Further, the second electrode layer is located above the gate metal layer, and the array substrate further includes:

a gate insulating layer on the gate metal layer;

A source-drain metal layer located on the gate insulating layer, the source-drain metal layer comprising: a source electrode and a drain electrode, and a data line;

a passivation layer on the source-drain metal layer;

Wherein, the second electrode layer is located on the passivation layer.

Further, a first via hole is provided in the passivation layer, and the drain electrode is electrically connected to the second electrode through the first via hole, so that the second electrode is a pixel electrode.

Further, a second via hole is provided in the gate insulating layer, and the drain electrode is electrically connected to the first electrode through the second via hole, so that the first electrode is a pixel electrode.

Further, the second electrode layer further includes: a connection pattern;

A third via hole is provided in the passivation layer, and the connection pattern is connected to the drain through the third via hole;

The array substrate also has a fourth via hole penetrating through the passivation layer and the gate insulating layer, and the connection pattern is connected to the first electrode through the fourth via hole, so that the first electrode is pixel electrodes.

Further, the second electrode layer further includes: a shielding electrode disposed opposite to the data line.

Further, the second electrode layer further includes: a signal access pattern, and the source-drain metal layer further includes: a conductive pattern, and the gate metal pattern includes a common electrode line;

Wherein, the signal access pattern is electrically connected to the conductive pattern through a via hole penetrating the passivation layer, and the conductive pattern is electrically connected to the common electrode line through a via hole penetrating the gate insulating layer.

Further, the signal access pattern includes: a first access sub-pattern and a second access sub-pattern;

The first access sub-pattern is electrically connected to the conductive pattern through the fifth via hole penetrating the passivation layer, and the second access sub-pattern is connected to the conductive pattern through the sixth via hole penetrating the passivation layer. The conductive pattern is electrically connected.

In another aspect, the present invention provides a method for manufacturing the aforementioned array substrate, comprising:

Fabricate a transparent conductive film and a metal film in sequence on the base substrate, and use a mask to pattern the transparent conductive film and the metal film to form a first electrode layer and a gate metal layer; wherein the first electrode layer includes: A reserved pattern and a first electrode, the gate metal layer includes: a gate metal pattern located on the reserved pattern and in direct contact with the reserved pattern;

The method further includes: forming a second electrode layer, the second electrode layer including: a second electrode disposed opposite to the first electrode;

Wherein, the first electrode is a common electrode, and the second electrode is a pixel electrode; or, the first electrode is a pixel electrode, and the second electrode is a common electrode.

In another aspect, the present invention provides a display device, comprising the array substrate described in any one of the above.

So far, the present invention provides an array substrate, a manufacturing method thereof, and a display device, wherein the array substrate includes: a first electrode layer, and the first electrode layer includes: a reserved pattern and a first electrode; A gate metal layer, the gate metal layer includes: a gate metal pattern located on the reserved pattern and in direct contact with the reserved pattern; and a second electrode layer, the second electrode layer includes: a second electrode disposed opposite to the first electrode Electrodes, wherein, the first electrode is a common electrode, and the second electrode is a pixel electrode; or, the first electrode is a pixel electrode, and the second electrode is a common electrode. Then, when fabricating the above-mentioned array substrate, a transparent conductive film and a metal film can be fabricated sequentially on the base substrate, and a primary mask is used to pattern the transparent conductive film and the metal film to form the first electrode layer and the gate electrode layer of the above structure. The metal layer, that is, the first electrode and the gate can be fabricated at the same time through one patterning process. Compared with the prior art, which requires three patterning processes to separately fabricate the gate, pixel electrode and common electrode, the array substrate provided by the present invention and its The manufacturing method can reduce the number of patterning processes used when manufacturing the array substrate.

Description of drawings

FIG. 1 is a structural schematic diagram 1 of an array substrate in the prior art;

FIG. 2 is a first structural schematic diagram of an array substrate provided by an embodiment of the present invention;

FIG. 3 is a schematic structural diagram II of an array substrate provided by an embodiment of the present invention;

FIG. 4 is a schematic structural diagram III of an array substrate provided by an embodiment of the present invention;

FIG. 5 is a structural schematic diagram 4 of an array substrate provided by an embodiment of the present invention;

FIG. 6 is a schematic structural diagram V of an array substrate provided by an embodiment of the present invention;

FIG. 7 is a sixth structural schematic diagram of an array substrate provided by an embodiment of the present invention;

FIG. 8 is a second structural schematic diagram of an array substrate in the prior art;

FIG. 9 is a first schematic diagram of the manufacturing process of an array substrate provided by an embodiment of the present invention;

FIG. 10 is a second schematic diagram of the manufacturing process of an array substrate provided by an embodiment of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, a feature defined as "first" and "second" may explicitly or implicitly include one or more of these features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

An embodiment of the present invention provides an array substrate 100, as shown in FIG. 2 , including:

A first electrode layer, the first electrode layer comprising: a reserved pattern 101 and a first electrode 102;

a gate metal layer located on the first electrode layer, the gate metal layer comprising: a gate metal pattern 103 located on the reserved pattern 101 and in direct contact with the reserved pattern 101;

The second electrode layer, the second electrode layer includes: a second electrode 104 opposite to the first electrode 102, wherein the first electrode 102 is a common electrode, and the second electrode is a 104 pixel electrode; or, the first electrode 102 is a common electrode; One electrode 102 is a pixel electrode, and the second electrode 104 is a common electrode.

Exemplarily, for an array substrate 100 with a bottom gate structure, as shown in FIG. 2 , the array substrate 100 further includes: a gate insulating layer 14 located on the gate metal layer; layer, the source-drain metal layer includes: a source electrode 105, a drain electrode 106, and a data line 107; and a passivation layer 16 located on the source-drain metal layer; wherein, the above-mentioned second electrode layer is located on the passivation layer 16 .

It can be seen that when fabricating the above-mentioned array substrate 100, a transparent conductive film and a metal film can be sequentially fabricated on the base substrate, and a primary mask is used to pattern the transparent conductive film and the metal film, thereby forming the first structure of the above structure. The electrode layer and the gate metal layer, that is, the first electrode 102 and the gate can be fabricated simultaneously through one patterning process. Compared with the prior art, the gate electrode, the pixel electrode and the common electrode need to be fabricated separately through three patterning processes. The present invention provides The array substrate and the manufacturing method thereof can reduce the number of patterning processes used when manufacturing the array substrate.

At the same time, in the array substrate 100 provided by the embodiment of the present invention, since there are two layers of passivation layer 16 and gate insulating layer 14 between the first electrode 102 and the second electrode 104, there is no need for The storage capacitance between the first electrode and the second electrode is reduced by increasing the thickness of the passivation layer, thereby reducing the thickness of the array substrate.

Exemplarily, in a possible design, as shown in FIG. 3 , a first via hole 201 is disposed in the passivation layer 16, and the drain electrode 106 is electrically connected to the second electrode 104 through the first via hole 201, so that the first via hole 201 is electrically connected to the second electrode 104. The second electrode 104 is a pixel electrode.

Exemplarily, in another possible design, as shown in FIG. 4, the second electrode layer further includes: a connection pattern 108; wherein, a third via hole 202 is provided in the passivation layer 16, and the connection pattern 108 passes through the first Three via holes 202 are connected to the drain electrode 106; at this time, the array substrate 100 also has a fourth via hole 203 penetrating through the passivation layer 16 and the gate insulating layer 14, and the connection pattern 108 is connected to the first electrode 102 through the fourth via hole 203 , so that the first electrode 102 is a pixel electrode.

However, in the array substrate 100 shown in FIG. 4 , since the connection pattern 108 connecting the third via hole 202 and the fourth via hole 203 is included, the area of the via hole area is increased, so that the aperture ratio of the array substrate 100 reduce.

In this regard, the embodiment of the present invention proposes an optimization scheme on the basis of FIG. 4. As shown in FIG. An electrode 102 is electrically connected, so that the first electrode 102 is a pixel electrode.

In this way, compared with the array substrate 100 shown in FIG. 4, in the array substrate 100 shown in FIG. , the area of the via hole region can be reduced, thereby reducing the influence on the aperture ratio of the array substrate 100 .

In addition, in the array substrate 100 shown in any one of FIGS. 2-5 , as shown in FIG. 6 , the second electrode layer further includes: a shielding electrode 109 arranged opposite to the data line 107. At this time, the shielding electrode 109 is used for The electric field formed around the shielding data line 107 prevents light leakage caused by the electric field.

Further, based on any array substrate 100 shown in FIGS. 2-5 , as shown in FIG. 7 , the second electrode layer further includes: a signal access pattern 110; the source-drain metal layer further includes: a conductive pattern 111; The metal pattern 103 includes a gate 112 and a common electrode line 113; wherein, the signal access pattern 110 is electrically connected to the conductive pattern 111 through the via hole penetrating the passivation layer 16, and the conductive pattern 111 is connected to the common electrode line through the via hole penetrating the gate insulating layer 14. The electrode lines 113 are electrically connected.

Exemplarily, as still shown in FIG. 7 , the signal access pattern 110 specifically includes: a first access sub-pattern 211 and a second access sub-pattern 212; wherein, the first access sub-pattern 211 passes through the passivation layer The fifth via hole 205 is electrically connected to the conductive pattern 111 , and the second access sub-pattern 212 is electrically connected to the conductive pattern 111 through the sixth via hole 206 penetrating through the passivation layer.

In the prior art, based on the array substrate shown in FIG. 1 , the signal access patterns 110, conductive patterns 111 and common electrode lines 113 are arranged as shown in FIG. The via hole C of the passivation layer 16, and the via hole D and the via hole E penetrating the passivation layer 16, the conductive pattern 111 communicates with the signal access pattern 110 through the via hole D and the via hole E, and the common electrode line 113 passes through the via hole C It communicates with the signal access pattern 110. At this time, since three via holes are provided, namely, via hole C, via hole D and via hole E, the area of the signal access pattern 110 in the via hole area increases, reducing the array The aperture ratio of the substrate 100.

However, in the array substrate 100 provided in FIG. 7 according to the embodiment of the present invention, when forming the gate insulating layer 14, a via hole can be made through an etching process, so that the conductive pattern 111 is electrically connected to the common electrode line 113 through the via hole. The fifth via hole 205 and the sixth via hole 206 need to be provided in the passivation layer 16, so that the signal access pattern 110 can be electrically connected to the common electrode line 113 through the conductive pattern 111, thereby reducing the number of via signal access patterns 110. area, thereby reducing the influence on the aperture ratio of the array substrate 100 .

Further, an embodiment of the present invention also provides a method for manufacturing the above-mentioned array substrate 100, including:

First, as shown in FIG. 9 , a transparent conductive thin film 31 and a metal thin film 32 are sequentially formed on the base substrate 200 . The transparent conductive film 31 may be a transparent conductive material such as ITO (Indium Tin Oxides, indium tin oxide).

Furthermore, as shown in Figure 10, after using a mask to expose, develop and etch the transparent conductive film 31 and the metal film 32, the pattern retained by the transparent conductive film 31 is the first electrode layer, and the metal film 32 remains The resulting pattern is the gate metal layer.

Wherein, the first electrode layer includes: a reserved pattern 101 and a first electrode 102 ; the gate metal layer includes: a gate metal pattern 103 located on the reserved pattern 101 and in direct contact with the reserved pattern 101 .

For example, the gate metal pattern 103 may be composed of a gate 112 and a common electrode line 113 .

It should be noted that, the first electrode 102 may be a common electrode, and at this time, the second electrode disposed opposite to the first electrode 102 is a pixel electrode; or, the first electrode 102 may be a pixel electrode, and at this time, the The second electrode opposite to 102 is a common electrode.

It can be seen that the first electrode 102 and the gate 112 can be produced simultaneously by only one patterning process in the above-mentioned production method. The provided array substrate and its manufacturing method can reduce the number of patterning processes used in manufacturing the array substrate, thereby reducing the complexity and manufacturing cost of manufacturing the array substrate.

Subsequently, the gate insulating layer 14 , the source-drain metal layer, the passivation layer 16 , and the second electrode layer may be fabricated separately.

Hereinafter, the manufacturing method of the array substrate 100 will be described in detail with respect to the specific structure of the array substrate 100 provided in FIGS. 3-5 .

For the array substrate 100 shown in FIG. 3 , after forming the above-mentioned first electrode layer and gate metal layer, a gate insulating layer 14 can be formed on the gate metal layer, and then, a source electrode can be fabricated on the gate insulating layer 14 through a patterning process. Drain metal layer, the source and drain metal layer includes: source electrode 105 and drain electrode 106, data line 107; furthermore, a passivation layer 16 is formed on the source and drain metal layer, and is formed in the passivation layer 16 by an etching process The first via hole 201, one end of the first via hole 201 is connected to the drain electrode 106, and finally, a second electrode layer is formed on the passivation layer 16 through a patterning process, and the second electrode layer includes: Opposed to the second electrode 104, at this time, the second electrode 104 is connected to the first via hole 201, so that the second electrode 104 is electrically connected to the drain electrode 106, the second electrode 104 is a pixel electrode, and the first electrode 102 is common electrode.

For the array substrate 100 shown in FIG. 4 , after forming the above-mentioned first electrode layer and gate metal layer, a gate insulating layer 14 can be formed on the gate metal layer, and then, a source electrode can be fabricated on the gate insulating layer 14 through a patterning process. Drain metal layer, the source-drain metal layer includes: source electrode 105 and drain electrode 106, data line 107; and then, make passivation layer 16 on the source-drain metal layer, after forming passivation layer 16, can pass through twice The third via hole 202 penetrating through the passivation layer 16 and the fourth via hole 203 penetrating the passivation layer 16 and the gate insulating layer 14 are produced respectively by etching process, wherein, one end of the third via hole 202 is connected with the drain electrode 106, and the third via hole 202 is connected to the drain electrode 106. One end of the four via holes 203 is connected to the first electrode 102. Since the depth of the fourth via hole 203 is relatively large, the concentration of the etching solution used in making the fourth via hole 203 is relatively large, and/or the etching time longer. Finally, a second electrode layer is formed on the passivation layer 16 through a patterning process, and the second electrode layer includes: a second electrode 104 disposed opposite to the first electrode 102, and a connection pattern 108, and the connection pattern 108 is simultaneously connected with the first electrode 102. The third via hole 202 is connected to the fourth via hole 203, so that the drain electrode 106 is electrically connected to the first electrode 102 through the third via hole 202, the fourth via hole 203 and the connection pattern 108. At this time, the second electrode 104 is a common electrode, and the first electrode 102 is a pixel electrode.

For the array substrate 100 shown in FIG. 5 , after forming the first electrode layer and the gate metal layer, a gate insulating layer 14 can be formed on the gate metal layer, and after forming the gate insulating layer 14, an etching process can be performed on the Form the second via hole 204 in the gate insulating layer 14, and one end of the second via hole 204 is connected to the first electrode 102, and further, a source-drain metal layer is fabricated on the gate insulating layer 14 through a patterning process, and the source-drain metal layer includes : source 105 and drain 106, data line 107; wherein, the drain 106 is connected to the other end of the second via hole 204, so that the drain 106 is electrically connected to the first electrode 102, and subsequently, the source-drain metal A passivation layer 16 is made on the passivation layer 16, and then, a second electrode layer is made on the passivation layer 16 through a patterning process, and the second electrode layer includes: a second electrode 104 opposite to the first electrode 102. At this time, The second electrode 104 is a common electrode, and the first electrode 102 is a pixel electrode.

Further, based on any one of the above-mentioned fabrication methods, when fabricating the above-mentioned second electrode layer, the second electrode 104 and the shielding electrode 109 can be formed at the same time, and the shielding electrode 109 is arranged opposite to the data line 107 to obtain an array as shown in FIG. 6 In the substrate 100 , at this time, the shielding electrode 109 is used to shield the electric field formed around the data line 107 to prevent light leakage caused by the electric field.

In addition, based on any of the above fabrication methods, when fabricating the array substrate 100 as shown in FIG. 106, the data line 107 and the conductive pattern 111 form a source-drain metal layer; when the second electrode 104 is produced, the signal access pattern 110 can be produced at the same time, for example, the first access sub-pattern 211 and the second access sub-pattern 212, And, after the gate insulating layer 14 is formed, a via hole connecting the common electrode line 113 and the conductive pattern 111 is made in the gate insulating layer 14 by an etching process, and after the passivation layer 16 is formed, the passivation layer is formed by an etching process. In the layer 16, make a via hole connecting the conductive pattern 111 and the signal access pattern 110, so that the external voltage signal can be transmitted to the common electrode line 113 through the signal access pattern 110, so as to drive the common electrode and the pixel electrode in the role of the external voltage signal An electric field is formed under it to deflect the liquid crystal molecules between the array substrate and the color filter substrate.

Further, an embodiment of the present invention also provides a display device, including the above-mentioned array substrate 100 . Wherein, the display device can be any display panel, or any product or component with a display function integrated with a display panel, such as: liquid crystal panel, electronic paper, OLED panel, mobile phone, tablet computer, TV, monitor, Laptops, digital photo frames, navigators, etc.

So far, the present invention provides an array substrate, a manufacturing method thereof, and a display device, wherein the array substrate includes: a first electrode layer, and the first electrode layer includes: a reserved pattern and a first electrode; A gate metal layer, the gate metal layer includes: a gate metal pattern located on the reserved pattern and in direct contact with the reserved pattern; and a second electrode layer, the second electrode layer includes: a second electrode disposed opposite to the first electrode Electrodes, wherein, the first electrode is a common electrode, and the second electrode is a pixel electrode; or, the first electrode is a pixel electrode, and the second electrode is a common electrode. Then, when fabricating the above-mentioned array substrate, a transparent conductive film and a metal film can be fabricated sequentially on the base substrate, and a primary mask is used to pattern the transparent conductive film and the metal film to form the first electrode layer and the gate electrode layer of the above structure. The metal layer, that is, the first electrode and the gate can be fabricated at the same time through one patterning process. Compared with the prior art, which requires three patterning processes to separately fabricate the gate, pixel electrode and common electrode, the array substrate provided by the present invention and its The manufacturing method can reduce the number of patterning processes used when manufacturing the array substrate.

In the description of this specification, specific features, structures, materials or characteristics may be combined in any one or more embodiments or examples in an appropriate manner.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. Should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims (10)

1. an array base palte, it is characterised in that including:

First electrode layer, described first electrode layer includes: retain pattern and the first electrode；

Being positioned at the grid metal level on described first electrode layer, described grid metal level includes: be positioned at institute State and retain the grid metal pattern directly contacted on pattern and with described reservation pattern；

The second electrode lay, described the second electrode lay includes: be oppositely arranged with described first electrode Second electrode, wherein, described first electrode is public electrode, and described second electrode is pixel electrode； Or, described first electrode is pixel electrode, and described second electrode is public electrode.

Array base palte the most according to claim 1, it is characterised in that described second electrode Layer is positioned at described grid metal layer, and described array base palte also includes:

It is positioned at the gate insulation layer on described grid metal level；

The source and drain metal level being positioned on described gate insulation layer, described source and drain metal level includes: source electrode And drain electrode, data wire；

It is positioned at the passivation layer on described source and drain metal level；

Wherein, described the second electrode lay is positioned on described passivation layer.

Array base palte the most according to claim 2, it is characterised in that in described passivation layer Being provided with the first via, described drain electrode is electrically connected with described second electrode by described first via, Making described second electrode is pixel electrode.

Array base palte the most according to claim 2, it is characterised in that described gate insulation layer Inside being provided with the second via, described drain electrode is electrically connected with described first electrode by described second via Connect so that described first electrode is pixel electrode.

Array base palte the most according to claim 2, it is characterised in that

Described the second electrode lay also includes: connecting pattern；

Being provided with the 3rd via in described passivation layer, described connecting pattern passes through described 3rd via It is connected with described drain electrode；

Described array base palte also has the 4th mistake running through described passivation layer and described gate insulation layer Hole, described connecting pattern is connected with described first electrode by described 4th via so that described the One electrode is pixel electrode.

6. according to the array base palte according to any one of claim 2-5, it is characterised in that institute State the second electrode lay also to include: the bucking electrode being oppositely arranged with described data wire.

7. according to the array base palte according to any one of claim 1-5, it is characterised in that institute State the second electrode lay also to include: signal accesses pattern, and described source and drain metal level also includes: conduction figure Case, described grid metal pattern includes public electrode wire；

Wherein, described signal accesses pattern by running through the via of described passivation layer and described conduction Pattern electrically connects, and described conductive pattern is by running through the via of described gate insulation layer and described common electrical Polar curve electrically connects.

Array base palte the most according to claim 7, it is characterised in that described signal accesses Pattern includes: first accesses sub pattern and second accesses sub pattern；

Described first accesses sub pattern by running through the 5th via of described passivation layer and described conduction Pattern electrically connects, and described second accesses sub pattern by running through the 6th via and the institute of described passivation layer State conductive pattern electrical connection.

9. a manufacture method for the array base palte as according to any one of claim 1-8, its It is characterised by, including:

Underlay substrate makes transparent conductive film and metallic film successively, and use is once covered Lamina membranacea forms the first electrode layer and grid metal level to described transparent conductive film and metallic film composition； Wherein, described first electrode layer includes: retaining pattern and the first electrode, described grid metal level includes: The grid metal pattern being positioned on described reservation pattern and directly contact with described reservation pattern；

Described method also includes: forming the second electrode lay, described the second electrode lay includes: with institute State the second electrode that the first electrode is oppositely arranged；

Wherein, described first electrode is public electrode, and described second electrode is pixel electrode；Or Person, described first electrode is pixel electrode, and described second electrode is public electrode.

10. a display device, it is characterised in that include as any one of claim 1-8 Described array base palte.