CN110718545A - Low residual voltage ESD surge protection device with low-capacitance structure - Google Patents
Low residual voltage ESD surge protection device with low-capacitance structure Download PDFInfo
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- 238000000034 method Methods 0.000 claims abstract description 12
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- 238000000137 annealing Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 9
- 238000002513 implantation Methods 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 230000001960 triggered effect Effects 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
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- 238000002347 injection Methods 0.000 claims 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/711—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements
- H10D89/713—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base region coupled to the collector region of the other transistor, e.g. silicon controlled rectifier [SCR] devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
- H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
- H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
- H02H9/045—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere
- H02H9/046—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage adapted to a particular application and not provided for elsewhere responsive to excess voltage appearing at terminals of integrated circuits
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
- H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
- H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
- H10D89/931—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs characterised by the dispositions of the protective arrangements
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Abstract
Description
技术领域technical field
本发明属于半导体元器件装置,更具体地说,涉及一种低容结构的低残压ESD浪涌防护器件。The invention belongs to a semiconductor component device, and more particularly, relates to a low-residual-voltage ESD surge protection device with a low-capacitance structure.
背景技术Background technique
由于工艺限制,纵向低残压器件受Zener+R2R结构限制,残压一直难以降低。随着信号口保护受续流问题的影响变弱,SCR结构成为降低器件残压的最有效方式,然而为了实现单向SCR结构的器件,多种工艺被用于制作SCR结构的保护器件,各有优点,由于使用了多层结构,在器件正向实现上工艺变得非常复杂。平面结构相对而言要简单很多,但是为了取得需要动作的击穿电压,不得不采用比较低掺杂浓度降低击穿电压,这样导致电容难以做到很低。Due to process limitations, vertical low residual voltage devices are limited by the Zener+R2R structure, and the residual voltage has been difficult to reduce. As the protection of the signal port is weakened by the freewheeling problem, the SCR structure has become the most effective way to reduce the residual voltage of the device. However, in order to realize the device of the unidirectional SCR structure, various processes are used to make the protection device of the SCR structure. There is an advantage that the process becomes very complex in the forward implementation of the device due to the use of a multi-layer structure. The planar structure is relatively simpler, but in order to obtain the breakdown voltage that needs to be operated, a relatively low doping concentration has to be used to reduce the breakdown voltage, which makes it difficult to achieve very low capacitance.
发明内容SUMMARY OF THE INVENTION
针对现有技术存在的不足,本发明的目的在于提供了一种低容结构的低残压ESD浪涌防护器件,设计合理,实现的单向大骤回SCR结构的保护器件,通过双沟槽工艺,实现了极低电容的SCR结构保护器件,能够满足当前低残压保护需求,且该器件具有低电容、低钳位和大浪涌通流能力等特点。In view of the deficiencies in the prior art, the purpose of the present invention is to provide a low-capacitance structure and low residual voltage ESD surge protection device, the design is reasonable, and the unidirectional large snapback SCR structure protection device can be realized through double trenches. The technology realizes a very low capacitance SCR structure protection device, which can meet the current low residual voltage protection requirements, and the device has the characteristics of low capacitance, low clamping and large surge current capacity.
为实现上述目的,本发明提供了如下技术方案:For achieving the above object, the present invention provides the following technical solutions:
一种低容结构的低残压ESD浪涌防护器件,其特征在于:包括通过电连接关系连接的降容管D1、TVS管D4、肖特基管D2、NPN管T1和正向降容管D3;其中降容管D3提供正向电流通路;D1与T1构成PNPN结构,为主放电通道;TVS管D4提供开启电压。A low-capacitance low-residual-voltage ESD surge protection device, characterized in that it includes a derating tube D1, a TVS tube D4, a Schottky tube D2, an NPN tube T1, and a forward de-rating tube D3 connected through an electrical connection relationship ; Among them, the derating tube D3 provides a forward current path; D1 and T1 form a PNPN structure, which is the main discharge channel; TVS tube D4 provides a turn-on voltage.
作为一种优化的技术方案,所述TVS管自下而上依次由N型衬底、N+扩区和P+扩区构成,其中TVS管的阴极为N+扩区,N+扩区位于中央位置;P+扩区用于制作TVS管的阳极。As an optimized technical solution, the TVS tube is composed of an N-type substrate, an N+ extension area and a P+ extension area in sequence from bottom to top, wherein the cathode of the TVS tube is the N+ extension area, and the N+ extension area is located in the central position; P+ The expansion area is used to make the anode of the TVS tube.
作为一种优化的技术方案,所述主放电通道自下而上依次由两个衬底N+Deep区、N-Epi区、P+基区和N+发射区构成;两个衬底N+Deep区设置在N-Epi区的两侧;P+基区的位置在N+发射区的上方,并在围绕TVS管的阳极中心位置等距离的地方留出能让门极触发时阴极短路孔上具有相同电位的阴极短路孔。As an optimized technical solution, the main discharge channel is composed of two substrate N+Deep regions, N-Epi regions, P+ base regions and N+ emitter regions in sequence from bottom to top; two substrate N+Deep regions It is arranged on both sides of the N-Epi region; the position of the P+ base region is above the N+ emitter region, and there is an equal distance around the center of the anode of the TVS tube, so that the cathode short-circuit hole has the same potential when the gate is triggered. cathode shorting hole.
本发明还提供了一种低残压ESD浪涌防护器件的制作工艺是:The present invention also provides a manufacturing process of the low residual voltage ESD surge protection device:
步骤如下:Proceed as follows:
高参杂的P+衬底材料上通过注入退火方式,形成N+埋层区;生长外延层N-Epi,通过注入退火形成N+Deep区,再通过注入退火方式,分别形成N+扩区和P+扩区;深槽刻蚀形成沟槽,沟槽内填充二氧化硅,再通过湿法腐蚀工艺,形成台面沟槽,淀积金属层形成金属互连,使得金属与衬底N+Deep区、P+区以及N-Epi区连接。On the highly doped P+ substrate material, the N+ buried layer region is formed by implantation annealing; the epitaxial layer N-Epi is grown, the N+ Deep region is formed by implantation annealing, and the N+ extension region and P+ extension region are formed respectively by implantation annealing. deep groove etching to form a trench, fill the trench with silicon dioxide, and then through a wet etching process to form a mesa trench, deposit a metal layer to form a metal interconnection, so that the metal and the substrate N+Deep region, P+ zone and N-Epi zone connection.
由于采用了上述技术方案,与现有技术相比,本发明设计合理,实现的单向大骤回SCR结构的保护器件,通过双沟槽工艺,实现了极低电容的SCR结构保护器件,能够满足当前低残压保护需求,且该器件具有低电容、低钳位和大浪涌通流能力等特点。Due to the adoption of the above technical solution, compared with the prior art, the present invention has a reasonable design, realizes a protection device with a unidirectional large snapback SCR structure, and realizes a protection device with an extremely low capacitance SCR structure through a double trench process. Meet the current low residual voltage protection requirements, and the device has the characteristics of low capacitance, low clamping and large surge current capacity.
参照附图和实施例对本发明做进一步说明。The present invention will be further described with reference to the accompanying drawings and embodiments.
附图说明Description of drawings
图1是本发明一种实施例的电路原理图;1 is a schematic circuit diagram of an embodiment of the present invention;
图2为本发明一种实施例制备完成后的整体结构示意图。FIG. 2 is a schematic diagram of the overall structure of an embodiment of the present invention after the preparation is completed.
具体实施方式Detailed ways
实施例Example
如图1所示,一种低容结构的低残压ESD浪涌防护器件,包括通过电连接关系连接的降容管D1、TVS管D4、肖特基管D2、NPN管T1和正向降容管D3;其中降容管D3提供正向电流通路;D1与T1构成PNPN结构,为主放电通道;TVS管D4提供开启电压。As shown in Figure 1, a low-capacitance low-residual-voltage ESD surge protection device includes a derating tube D1, a TVS tube D4, a Schottky tube D2, an NPN tube T1 and a forward derating tube connected through an electrical connection relationship Tube D3; among them, the derating tube D3 provides a forward current path; D1 and T1 form a PNPN structure, which is the main discharge channel; TVS tube D4 provides a turn-on voltage.
所述TVS管自下而上依次由N型衬底、N+扩区和P+扩区构成,其中TVS管的阴极为N+扩区,N+扩区位于中央位置;P+扩区用于制作TVS管的阳极。The TVS tube is composed of an N-type substrate, an N+ extension area and a P+ extension area from bottom to top, wherein the cathode of the TVS tube is an N+ extension area, and the N+ extension area is located at the central position; the P+ extension area is used to make the TVS tube. anode.
所述主放电通道自下而上依次由两个衬底N+Deep区、N-Epi区、P+基区和N+发射区构成;两个衬底N+Deep区设置在N-Epi区的两侧;P+基区的位置在N+发射区的上方,并在围绕TVS管的阳极中心位置等距离的地方留出能让门极触发时阴极短路孔上具有相同电位的阴极短路孔。The main discharge channel is composed of two substrate N+Deep regions, N-Epi regions, P+ base regions and N+ emitter regions in sequence from bottom to top; the two substrate N+Deep regions are arranged on two sides of the N-Epi region. The position of the P+ base region is above the N+ emitter region, and a cathode short-circuit hole that can have the same potential on the cathode short-circuit hole when the gate is triggered is left equidistant around the center of the anode of the TVS tube.
上述器件为双沟槽工艺器件,沟槽提供器件隔离,沟槽用于连接衬底与N+IOS以及表面P+区。该器件是外延型低容器件,N-Epi为器件提供低容支持。该器件是单向器件,可通过阵列原包结构构成双路、多路保护器件。The above-mentioned device is a double-trench process device, the trench provides device isolation, and the trench is used to connect the substrate with the N+IOS and the surface P+ region. The device is an epitaxial low-capacitance device, and N-Epi provides low-capacitance support for the device. The device is a one-way device, which can form a dual-channel and multi-channel protection device through the original package structure of the array.
如图2所示,低残压ESD浪涌防护器件的制作工艺是:高参杂的P+衬底材料上通过注入退火方式,形成N+埋层区;生长外延层N-Epi,通过注入退火形成N+Deep区,再通过注入退火方式,分别形成N+扩区和P+扩区;深槽刻蚀形成沟槽,沟槽内填充二氧化硅,再通过湿法腐蚀工艺,形成台面沟槽,淀积金属层形成金属互连,使得金属与衬底N+Deep区、P+区以及N-Epi区连接。As shown in Figure 2, the manufacturing process of the low residual voltage ESD surge protection device is as follows: an N+ buried layer region is formed on a highly impurity P+ substrate material by implantation annealing; an epitaxial layer N-Epi is grown and formed by implantation annealing N+Deep area, and then through implantation annealing method, respectively form N+ expansion area and P+ expansion area; deep trench etching forms trenches, the trenches are filled with silicon dioxide, and then wet etching process is used to form mesa trenches, depositing A metal layer is deposited to form a metal interconnection, so that the metal is connected to the N+Deep region, the P+ region and the N-Epi region of the substrate.
本发明设计合理,实现的单向大骤回SCR结构的保护器件,通过双沟槽工艺,实现了极低电容的SCR结构保护器件,能够满足当前低残压保护需求,且该器件具有低电容、低钳位和大浪涌通流能力等特点。The present invention has a reasonable design, realizes a protection device with a unidirectional large snapback SCR structure, and realizes a protection device with an extremely low capacitance SCR structure through a double trench process, which can meet the current low residual voltage protection requirements, and the device has a low capacitance. , low clamping and large surge current capability.
本发明的保护范围并不仅局限于上述实施例,凡属于本发明思路下的技术方案均属于本发明的保护范围。应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明原理前提下的若干改进和润饰,这些改进和润饰也应视为本发明的保护范围。The protection scope of the present invention is not limited to the above-mentioned embodiments, and all technical solutions that belong to the idea of the present invention belong to the protection scope of the present invention. It should be pointed out that for those skilled in the art, some improvements and modifications without departing from the principle of the present invention should also be regarded as the protection scope of the present invention.
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