CN106784021A - A kind of improved channel schottky rectifying device and its manufacture method - Google Patents
A kind of improved channel schottky rectifying device and its manufacture method Download PDFInfo
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- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
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Abstract
本发明公开了一种改进的沟槽式肖特基整流器件及其制造方法，本发明的改进的沟槽式肖特基整流器件，包括：第一导电类型衬底，第一导电类型导电层，沟槽，导电多晶硅，栅绝缘层，金属电极层，相邻两个沟槽之间的第一导电类型导电层上表层内设有第二导电类型区，所述金属电极层设置于所述第一导电类型导电层、导电多晶硅以及第二导电类型区之上，本发明提高反向电压抗击能力，同时改善因沟槽距离小引起的正向导通压降变大的问题。
The invention discloses an improved trench type Schottky rectifier device and a manufacturing method thereof. The improved trench type Schottky rectifier device of the present invention includes: a first conductivity type substrate, a first conductivity type conduction layer , trench, conductive polysilicon, gate insulating layer, metal electrode layer, a second conductivity type region is arranged in the upper surface layer of the first conductivity type conduction layer between two adjacent trenches, and the metal electrode layer is arranged on the On the conductive layer of the first conductivity type, the conductive polysilicon and the region of the second conductivity type, the present invention improves the reverse voltage resistance capability, and at the same time improves the problem of large forward conduction voltage drop caused by small trench distances.
Description
技术领域technical field
本发明涉及半导体器件，特别涉及一种沟槽式肖特基整流器件及其制造方法。The invention relates to a semiconductor device, in particular to a trench type Schottky rectifier device and a manufacturing method thereof.
技术背景technical background
肖特基二极管作为整流器件已经在电源应用领域使用了数十年。相对于PN结二极管而言，肖特基二极管具有正向开启电压低和开关速度快的优点，这使其非常适合应用于开关电源以及高频场合。肖特基二极管的反向恢复时间非常短，该时间主要由器件的寄生电容决定，而不像PN结二极管那样由少子复合时间决定。因此，肖特基二极管整流器件可以有效的降低开关功率损耗。Schottky diodes have been used in power supply applications for decades as rectification devices. Compared with PN junction diodes, Schottky diodes have the advantages of low forward turn-on voltage and fast switching speed, which makes them very suitable for switching power supplies and high-frequency applications. The reverse recovery time of the Schottky diode is very short, which is mainly determined by the parasitic capacitance of the device, not by the minority carrier recombination time like the PN junction diode. Therefore, the Schottky diode rectifier device can effectively reduce switching power loss.
传统的肖特基整流器件采用了台面工艺，金属(如铝、钼)与掺杂的半导体导电层结合构成了肖特基势垒，其具有整流特性，阳极为金属，阴极为掺杂的半导体，金属半导体接触的肖特基势垒为单边结，在提高器件速度的同时也引入了较大的反向漏电。The traditional Schottky rectifier device adopts the mesa technology, and the metal (such as aluminum, molybdenum) is combined with the doped semiconductor conductive layer to form the Schottky barrier, which has rectification characteristics, the anode is metal, and the cathode is doped semiconductor , the Schottky barrier of the metal-semiconductor contact is a unilateral junction, which also introduces a large reverse leakage while increasing the device speed.
为改善传统的台面肖特基结构存在的不足，现有肖特基整流器在在传统肖特基二极管结构中，加入沟槽MOS结构，在沟槽内，氧化层和填入的掺杂多晶硅材料构成MOS结构的栅极，并围绕肖特基势垒区，利用MOS电容产生的耗尽层夹断肖特基势垒区，将肖特基势垒区的反向电场引入器件内部，以提高肖特基的抗反向电压能力。要保证MOS电容产生的耗尽层能够夹断肖特基势垒区，需要相邻两沟槽距离要足够小，但是，相邻两沟槽之间的距离太小，会影响金属和半导体导电层的肖特基接触面积，使导通区域变窄，正向导通压降变大，两者相互矛盾。In order to improve the deficiencies of the traditional mesa Schottky structure, the existing Schottky rectifier adds a trench MOS structure to the traditional Schottky diode structure, and in the trench, the oxide layer and the doped polysilicon material filled The gate of the MOS structure is surrounded by the Schottky barrier region, and the depletion layer generated by the MOS capacitor is used to pinch off the Schottky barrier region, and the reverse electric field of the Schottky barrier region is introduced into the device to improve Schottky's anti-reverse voltage capability. To ensure that the depletion layer generated by the MOS capacitor can pinch off the Schottky barrier region, the distance between two adjacent trenches needs to be small enough. However, the distance between two adjacent trenches is too small, which will affect the conduction of metals and semiconductors. The Schottky contact area of the layer narrows the conduction area and increases the forward conduction voltage drop, which contradicts each other.
发明内容Contents of the invention
本发明的目的是提供一种改进的沟槽式肖特基整流器件，提高反向电压抗击能力，同时改善因沟槽距离小引起的正向导通压降变大的问题。The purpose of the present invention is to provide an improved trench type Schottky rectifier device, which can improve the reverse voltage resistance and improve the problem of large forward conduction voltage drop caused by small trench distance.
本发明的另一目的是提供上述改进的沟槽式肖特基整流器件的制造方法。Another object of the present invention is to provide a method for manufacturing the above-mentioned improved trench Schottky rectifier device.
为实现上述目的，本发明采用如下技术方案：To achieve the above object, the present invention adopts the following technical solutions:
一种改进的沟槽式肖特基整流器件，包括：第一导电类型衬底，形成于所述第一导电类型衬底上的第一导电类型导电层，形成于所述第一导电类型导电层上表层中的沟槽，填充所述沟槽的导电多晶硅，形成于所述沟槽与所述导电多晶硅之间的栅绝缘层，形成于所述第一导电类型导电层表面上的金属电极层，相邻两个沟槽之间的第一导电类型导电层上表层内设有第二导电类型区，所述金属电极层设置于所述第一导电类型导电层、导电多晶硅以及第二导电类型区之上。An improved trench type Schottky rectifier device, comprising: a first conductivity type substrate, a first conductivity type conduction layer formed on the first conductivity type substrate, and a first conductivity type conduction layer formed on the first conductivity type conduction layer A trench in the upper surface layer of the layer, conductive polysilicon filling the trench, a gate insulating layer formed between the trench and the conductive polysilicon, and a metal electrode formed on the surface of the first conductivity type conduction layer layer, the upper surface layer of the first conductivity type conduction layer between two adjacent grooves is provided with a second conductivity type region, and the metal electrode layer is arranged on the first conductivity type conduction layer, conductive polysilicon and second conductivity type above the type area.
优选地，所述第二导电类型区位于相邻两沟槽中间。Preferably, the region of the second conductivity type is located between two adjacent trenches.
优选地，所述第二导电类型区包括轻掺杂第二导电类型区以及位于轻掺杂第二导电类型区上表层内的重掺杂第二导电类型区。Preferably, the second conductivity type region includes a lightly doped second conductivity type region and a heavily doped second conductivity type region located in the upper surface layer of the lightly doped second conductivity type region.
优选地，所述第二导电类型区正下方形成掺杂浓度大于第一导电类型导电层的第一导电类型增强区。Preferably, an enhancement region of the first conductivity type having a doping concentration higher than that of the conduction layer of the first conductivity type is formed directly under the region of the second conductivity type.
优选地，所述第一导电类型增强区与所述第二导电类型区不接触。Preferably, the enhanced region of the first conductivity type is not in contact with the region of the second conductivity type.
优选地，所述第一导电类型增强层与第一导电类型衬底接触。Preferably, the enhancement layer of the first conductivity type is in contact with the substrate of the first conductivity type.
优选地，所述第一导电类型为N型，第二导电类型为P型。Preferably, the first conductivity type is N type, and the second conductivity type is P type.
一种沟槽式肖特基整流器件的制造方法，包括以下步骤：A method for manufacturing a trench type Schottky rectifier device, comprising the following steps:
(1)在第一导电类型衬底上外延生长第一导电类型导电层；(1) epitaxially growing a first conductivity type conduction layer on a first conductivity type substrate;
(2)在第一导电类型导电层上形成绝缘介质层，光刻所述绝缘介质层，部分漏出第一导电类型导电层，形成沟槽刻蚀区；(2) forming an insulating dielectric layer on the first conductive type conductive layer, photoetching the insulating dielectric layer, and partially leaking the first conductive type conductive layer to form a trench etching region;
(3)以光刻过的绝缘介质层为掩膜版，刻蚀沟槽刻蚀区，形成沟槽；(3) using the photoetched insulating dielectric layer as a mask, etching the groove etching area to form a groove;
(4)在沟槽内壁形成栅绝缘层，然后沉积导电多晶硅填满沟槽；(4) Form a gate insulating layer on the inner wall of the trench, and then deposit conductive polysilicon to fill the trench;
(5)制作硬质掩膜层，在相邻两个沟槽之间的第一导电类型导电层上表层内掺杂形成第二导电类型区；(5) making a hard mask layer, doping in the upper surface layer of the first conductivity type conduction layer between two adjacent trenches to form a second conductivity type region;
(6)去除第一导电类型导电层上的绝缘介质层，在第一导电类型导电层、导电多晶硅以及第二导电类型区形成的表面上沉积金属，形成金属电极层。(6) Remove the insulating dielectric layer on the first conductivity type conduction layer, deposit metal on the surface formed by the first conductivity type conduction layer, conductive polysilicon and the second conductivity type region, to form a metal electrode layer.
优选地，第(2)步第一导电类型导电层分两次沉积形成，第一次沉积后在其上表层掺杂形成第一导电类型增强区。Preferably, in step (2), the conduction layer of the first conductivity type is deposited in two steps, and after the first deposition, the upper surface layer is doped to form the enhancement region of the first conductivity type.
优选地，所述绝缘介质层为氧化硅、氮化硅或者氮氧化硅。Preferably, the insulating dielectric layer is silicon oxide, silicon nitride or silicon oxynitride.
相对于现有技术，本发明具有以下有益效果：Compared with the prior art, the present invention has the following beneficial effects:
本发明的沟槽式肖特基整流器件相邻两个沟槽之间的第一导电类型导电层上表层内设有第二导电类型区，第二导电类型区与金属电极层接触，第二导电类型区与第一导电类型导电层形成PN结。肖特基整流器件施加反向偏压时，导电多晶硅、栅绝缘层以及第一导电类型导电层构成的MOS结构在第一导电类型导电层内形成耗尽，同时第二导电类型区与第一导电类型导电层形成的PN结也反向偏置，形成PN结耗尽，MOS电容产生的耗尽层与PN结耗尽层相连将肖特基势垒区夹断，所以沟槽间距相同的情况下，相对于只有MOS电容产生的耗尽层夹断肖特基势垒区的夹断速度更快，夹断电压更低，使反向漏电流更小，抗击反向电压能力更强，换而言之，若要到达相同的抗电压能力，本发明所需的沟槽间距更大，金属与半导体接触面积更大，肖特基整流器件施加正向偏压时，PN结也正向偏置，所以金属与半导体接触面积变大，有效改善了正向导通压降。In the trench type Schottky rectifier device of the present invention, a second conductivity type region is provided in the upper surface layer of the first conductivity type conduction layer between two adjacent trenches, and the second conductivity type region is in contact with the metal electrode layer, and the second conductivity type region is in contact with the metal electrode layer. The conductivity type region forms a PN junction with the first conductivity type conduction layer. When the Schottky rectifier device is applied with a reverse bias, the MOS structure composed of conductive polysilicon, gate insulating layer and the first conductivity type conduction layer is depleted in the first conductivity type conduction layer, while the second conductivity type region and the first conductivity type The PN junction formed by the conductivity type conductive layer is also reverse biased to form a PN junction depletion, and the depletion layer generated by the MOS capacitor is connected to the PN junction depletion layer to pinch off the Schottky barrier region, so the same trench spacing In this case, compared with only the depletion layer generated by the MOS capacitor, the pinch-off speed of the Schottky barrier region is faster, the pinch-off voltage is lower, the reverse leakage current is smaller, and the ability to resist reverse voltage is stronger. In other words, to achieve the same voltage resistance capability, the trench spacing required by the present invention is larger, and the contact area between the metal and the semiconductor is larger. When the Schottky rectifier device is applied with a forward bias, the PN junction is also forward biased Bias, so the metal-semiconductor contact area becomes larger, which effectively improves the forward conduction voltage drop.
附图说明Description of drawings
图1为第一实施例结构示意图；Fig. 1 is a schematic structural diagram of the first embodiment;
图1A-图1F为第一实施例制造流程示意图；1A-1F are schematic diagrams of the manufacturing process of the first embodiment;
图2为第二实施例结构示意图。Fig. 2 is a schematic structural diagram of the second embodiment.
具体实施方式detailed description
下面结合附图以及实施例对本发明进行介绍，实施例仅用于对本发明进行解释，并不对本发明有任何限定作用。The present invention will be introduced below in conjunction with the accompanying drawings and embodiments, and the embodiments are only used to explain the present invention and do not limit the present invention in any way.
第一实施例first embodiment
如图1所示，本实施例的改进的沟槽式肖特基整流器件，包括：第一导电类型衬底10，形成于所述第一导电类型衬底10上的第一导电类型导电层20，形成于所述第一导电类型导电层20上表层中的沟槽30，填充所述沟槽30的导电多晶硅40，形成于所述沟槽30与所述导电多晶硅40之间的栅绝缘层50，形成于所述第一导电类型导电层20表面上的金属电极层60，相邻两个沟槽30之间的第一导电类型导电层20上表层内设有第二导电类型区70，所述金属电极层60设置于所述第一导电类型导电层20、导电多晶硅40以及第二导电类型区70之上。As shown in Figure 1, the improved trench Schottky rectifier device of this embodiment includes: a first conductivity type substrate 10, a first conductivity type conduction layer formed on the first conductivity type substrate 10 20, the trench 30 formed in the upper surface layer of the first conductivity type conduction layer 20, the conductive polysilicon 40 filling the trench 30, and the gate insulation formed between the trench 30 and the conductive polysilicon 40 layer 50, a metal electrode layer 60 formed on the surface of the first conductivity type conduction layer 20, and a second conductivity type region 70 is provided in the upper surface layer of the first conductivity type conduction layer 20 between two adjacent trenches 30 , the metal electrode layer 60 is disposed on the first conductivity type conduction layer 20 , the conductive polysilicon 40 and the second conductivity type region 70 .
本实施例所述第一导电类型为N型，第二导电类型为P型，也可以第一导电类型为P型，第二导电类型为N型，下面以第一导电类型为N型，第二导电类型为P型进行介绍。In this embodiment, the first conductivity type is N-type, the second conductivity type is P-type, or the first conductivity type is P-type, and the second conductivity type is N-type. In the following, the first conductivity type is N-type, and the second conductivity type is N-type. The second conductivity type is P-type for introduction.
本实施例所述第一导电类型衬底10可为高掺杂浓度的N型单晶硅衬底，所述第一导电类型导电层20为低掺杂浓度的N型外延层；所述栅绝缘层50可为氧化硅，所述金属电极层60为与第一导电类型导电层形成肖特基接触的金属，例如N型外延层材料为GaN时，金属电极层60材料可为金、银铂以及铝等，考虑成本原因，可选用铝。The first conductivity type substrate 10 in this embodiment can be an N-type single crystal silicon substrate with a high doping concentration, and the first conductivity type conduction layer 20 is an N-type epitaxial layer with a low doping concentration; the gate The insulating layer 50 can be silicon oxide, and the metal electrode layer 60 is a metal that forms a Schottky contact with the first conductivity type conduction layer. For example, when the material of the N-type epitaxial layer is GaN, the material of the metal electrode layer 60 can be gold or silver. Platinum and aluminum, etc., considering cost reasons, aluminum can be used.
本实施例沟槽式肖特基整流器件相邻两个沟槽30之间的第一导电类型导电层20上表层内设有第二导电类型区70，第二导电类型区70与金属电极层60接触，优选地第二导电类型区70包括轻掺杂第二导电类型区71以及位于轻掺杂第二导电类型区71上表层内的重掺杂第二导电类型区72，轻掺杂第二导电类型区71与第一导电类型导电层20形成PN结耗尽，重掺杂第二导电类型区72可与金属电极层60更好地形成欧姆接触，减小接触电阻。The second conductivity type region 70 is arranged in the upper surface layer of the first conductivity type conduction layer 20 between two adjacent grooves 30 of the trench Schottky rectifier device in this embodiment, and the second conductivity type region 70 is connected with the metal electrode layer. 60 contact, preferably the second conductivity type region 70 includes a lightly doped second conductivity type region 71 and a heavily doped second conductivity type region 72 located in the upper surface layer of the lightly doped second conductivity type region 71, the lightly doped second conductivity type region 72 The second conductivity type region 71 forms a PN junction depletion with the first conductivity type conduction layer 20 , and the heavily doped second conductivity type region 72 can better form an ohmic contact with the metal electrode layer 60 and reduce contact resistance.
第二导电类型区70与第一导电类型导电层20形成PN结，肖特基整流器件施加反向偏压时，导电多晶硅,4、栅绝缘层50以及第一导电类型导电层20构成的MOS结构在第一导电类型导电层20内形成耗尽，同时第二导电类型区70与第一导电类型导电层20形成的PN结也反向偏置，形成PN结耗尽，MOS电容产生的耗尽层与PN结耗尽层相连将肖特基势垒区夹断，所以沟槽间距相同的情况下，相对于只有MOS电容产生的耗尽层夹断肖特基势垒区的夹断速度更快，夹断电压更低，使反向漏电流更小，抗击反向电压能力更强，换而言之，若要到达相同的抗电压能力，本实施例所需的沟槽间距更大，金属与半导体接触面积更大，肖特基整流器件施加正向偏压时，PN结也正向偏置，所以金属与半导体接触面积变大，有效改善了正向导通压降，优选地，所述第二导电类型区70位于相邻两沟槽30中间，MOS结构相对于PN结结构对称设置，更均匀地实现肖特基势垒区的耗尽夹断。The second conductivity type region 70 and the first conductivity type conduction layer 20 form a PN junction. When the Schottky rectifier device is applied with a reverse bias, the MOS composed of conductive polysilicon, 4, gate insulating layer 50 and the first conductivity type conduction layer 20 The structure forms depletion in the conduction layer 20 of the first conduction type, and at the same time, the PN junction formed by the region 70 of the second conduction type and the conduction layer 20 of the first conduction type is also reversely biased to form a depletion of the PN junction, and the depletion produced by the MOS capacitance The depletion layer is connected to the PN junction depletion layer to pinch off the Schottky barrier region, so when the trench spacing is the same, the pinch-off speed of the Schottky barrier region is pinched off compared to the depletion layer generated by only MOS capacitors Faster, lower pinch-off voltage, smaller reverse leakage current, and stronger ability to resist reverse voltage. In other words, to achieve the same voltage resistance, the groove spacing required by this embodiment is larger , the metal-semiconductor contact area is larger, and when the Schottky rectifier device is forward-biased, the PN junction is also forward-biased, so the metal-semiconductor contact area becomes larger, which effectively improves the forward conduction voltage drop. Preferably, The second conductivity type region 70 is located between two adjacent trenches 30, and the MOS structure is arranged symmetrically with respect to the PN junction structure, so that the depletion pinch-off of the Schottky barrier region can be achieved more uniformly.
本实施例沟槽式肖特基整流器件的制造方法如图1A-图1F，包括以下步骤：The manufacturing method of the grooved Schottky rectifier device in this embodiment is shown in Fig. 1A-Fig. 1F, including the following steps:
(1)在第一导电类型衬底10上外延生长第一导电类型导电层20；(1) epitaxially growing the first conductivity type conduction layer 20 on the first conductivity type substrate 10;
(2)在第一导电类型导电层上形成绝缘介质层80，光刻所述绝缘介质层80，部分漏出第一导电类型导电层20，形成沟槽刻蚀区；(2) Forming an insulating dielectric layer 80 on the first conductivity type conduction layer, photoetching the insulation dielectric layer 80, and partially leaking the first conductivity type conduction layer 20 to form a trench etching region;
所述绝缘介质层可为氧化硅、氮化硅或者氮氧化硅，可通过PECVD法沉积形成。The insulating dielectric layer can be silicon oxide, silicon nitride or silicon oxynitride, and can be deposited and formed by PECVD.
(3)以光刻过的绝缘介质层80为掩膜版，刻蚀沟槽刻蚀区，形成沟槽30；(3) Using the photoetched insulating dielectric layer 80 as a mask, etch the trench etching area to form the trench 30;
(4)在沟槽30内壁形成栅绝缘层50，然后沉积导电多晶硅40填满沟槽30；(4) Form a gate insulating layer 50 on the inner wall of the trench 30, and then deposit conductive polysilicon 40 to fill the trench 30;
(5)制作硬质掩膜层，在相邻两个沟槽30之间的第一导电类型导电层20上表层内掺杂形成第二导电类型区70；(5) Make a hard mask layer, doping in the upper surface layer of the first conductivity type conduction layer 20 between two adjacent trenches 30 to form a second conductivity type region 70;
优选地，第二导电类型区70包括轻掺杂第二导电类型区71以及位于轻掺杂第二导电类型区71上表层内的重掺杂第二导电类型区72，首先在第一导电类型导电层20上表层内掺杂形成轻掺杂第二导电类型区71，然后在轻掺杂第二导电类型区71上表层内掺杂形成重掺杂第二导电类型区72。Preferably, the second conductivity type region 70 includes a lightly doped second conductivity type region 71 and a heavily doped second conductivity type region 72 located in the upper surface layer of the lightly doped second conductivity type region 71. The upper surface of the conductive layer 20 is internally doped to form a lightly doped second conductivity type region 71 , and then the upper surface of the lightly doped second conductivity type region 71 is doped to form a heavily doped second conductivity type region 72 .
(6)去除第一导电类型导电层20上的绝缘介质层80，在第一导电类型导电层20、导电多晶硅40以及第二导电类型区70形成的表面上沉积金属，形成金属电极层60。(6) Remove the insulating medium layer 80 on the first conductivity type conduction layer 20 , deposit metal on the surface formed by the first conductivity type conduction layer 20 , the conductive polysilicon 40 and the second conductivity type region 70 to form the metal electrode layer 60 .
第二实施例second embodiment
如图2所示，本实施例沟槽式肖特基整流器件与第一实施例技术方案基本相同，不同之处在于，本实施例所述第二导电类型区70正下方形成掺杂浓度大于第一导电类型导电层20的第一导电类型增强区90，第一导电类型增强区90形成在第二导电类型区70正下方，不影响PN结与MOS结构横向耗尽夹断肖特基势垒区的情况下，即在不影响反向抗压能力的情况下，增加了导电层载流子浓度，降低了正向导通压降。As shown in Figure 2, the trench Schottky rectifier device of this embodiment is basically the same as the technical solution of the first embodiment, the difference is that the doping concentration is greater than The first conductivity type enhancement region 90 of the first conductivity type conduction layer 20, the first conductivity type enhancement region 90 is formed directly under the second conductivity type region 70, and does not affect the lateral depletion of the PN junction and the MOS structure to pinch off the Schottky potential In the case of the barrier region, that is, without affecting the reverse withstand voltage capability, the carrier concentration of the conductive layer is increased, and the forward conduction voltage drop is reduced.
优选地，所述第一导电类型增强区90与所述第二导电类型70不接触，第二导电类型70与掺杂浓度更低的第一导电类型导电层20接触形成PN结更宽，增强器件对反向电压的抗击能力。Preferably, the enhancement region 90 of the first conductivity type is not in contact with the second conductivity type 70, and the second conductivity type 70 is in contact with the conduction layer 20 of the first conductivity type with a lower doping concentration to form a wider PN junction, enhancing Device immunity to reverse voltage.
优选地，所述第一导电类型增强层90与第一导电类型衬底10接触，最大限度地增加导电层载流子浓度，降低正向了导通压降。Preferably, the enhancement layer 90 of the first conductivity type is in contact with the substrate 10 of the first conductivity type, so as to maximize the carrier concentration of the conductive layer and reduce the forward voltage drop.
本实施例沟槽式肖特基整流器件制造方法，在第一实施例的基础上，第(2)步第一导电类型导电层20分两次沉积形成，第一次沉积后在其上表层掺杂形成第一导电类型增强区90。In the manufacturing method of the trench type Schottky rectifier device of this embodiment, on the basis of the first embodiment, the first conduction type conduction layer 20 of step (2) is formed by two depositions, and after the first deposition, the upper surface layer Doping forms the enhanced region 90 of the first conductivity type.
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| US12199192B1 (en) * | 2023-08-08 | 2025-01-14 | Diodes Incorporated | Trench Schottky barrier rectifier and method for fabricating same |
| WO2025030731A1 (en) * | 2023-08-08 | 2025-02-13 | 达尔科技股份有限公司 | Semiconductor rectifier device and manufacturing method therefor |
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| CN102683428A (en) * | 2005-12-27 | 2012-09-19 | 美商科斯德半导体股份有限公司 | Ultrafast recovery diode |
| CN105789331A (en) * | 2014-12-25 | 2016-07-20 | 无锡华润上华半导体有限公司 | Semiconductor rectifying device and manufacturing method therefor |
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| CN102683428A (en) * | 2005-12-27 | 2012-09-19 | 美商科斯德半导体股份有限公司 | Ultrafast recovery diode |
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| US12199192B1 (en) * | 2023-08-08 | 2025-01-14 | Diodes Incorporated | Trench Schottky barrier rectifier and method for fabricating same |
| WO2025030731A1 (en) * | 2023-08-08 | 2025-02-13 | 达尔科技股份有限公司 | Semiconductor rectifier device and manufacturing method therefor |
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