CN110676321A - Trench MOSFET and method of manufacturing the same - Google Patents

Abstract

The present application provides a trench MOSFET and a method for manufacturing the same. The trench MOSFET includes: a substrate with a first conductivity type; an epitaxial layer with the first conductivity type formed on the substrate, the doping concentration of the epitaxial layer is lower than that of the substrate; formed on the epitaxial layer a trench in the layer; a gate structure filled in the trench, the gate structure includes a shielding gate electrode, a control gate electrode located above the shielding gate electrode, a dielectric layer covering the shielding gate electrode and filling the side of the control gate electrode; forming a plurality of implanted regions with the first conductivity type in the epitaxial layer, the plurality of implanted regions are arranged from top to bottom and are located on the side of the shielding gate electrode, and the doping concentration of the implanted regions is greater than that of the epitaxial layer; formed in A body region with a second conductivity type in the epitaxial layer and above the plurality of implanted regions; a source region with the first conductivity type formed in the epitaxial layer and over the body region, the doping concentration of the source region is greater than that of the body region doping concentration.

Description

Trench MOSFET and method of making the same

technical field

The present application relates to the field of semiconductor technology, and in particular, to a trench MOSFET and a method for manufacturing the same.

Background technique

In the development of the semiconductor field, for low-voltage MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor, metal-oxide-semiconductor field-effect transistors), reducing on-resistance has become the focus of research.

SGTMOS (Shield Gate Trench MOS, shielded gate trench MOS) includes a substrate, an epitaxial layer located on the substrate, and a device structure located in the epitaxial layer. The doping concentration of the epitaxial layer of SGTMOS in the prior art is constant, and the specific on-resistance (on-resistance per unit area) of SGTMOS can be reduced by increasing the doping concentration of the epitaxial layer, but at the same time, it will also lead to SGTMOS The withstand voltage is reduced. Therefore, the conventional SGTMOS cannot further reduce the specific on-resistance of the SGTMOS without lowering the withstand voltage of the SGTMOS.

SUMMARY OF THE INVENTION

According to a first aspect of the embodiments of the present application, a trench MOSFET is provided, including:

a substrate having a first conductivity type;

an epitaxial layer with a first conductivity type formed on the substrate, the doping concentration of the epitaxial layer is lower than the doping concentration of the substrate;

a trench formed in the epitaxial layer;

a gate structure filled in the trench, the gate structure including a shielded gate electrode;

A plurality of implanted regions with a first conductivity type are formed in the epitaxial layer, the plurality of implanted regions are arranged from top to bottom and are located on the side of the shielding gate electrode, and the doping concentration of the implanted regions is greater than the doping concentration of the epitaxial layer;

a body region having a second conductivity type formed in the epitaxial layer over a plurality of the implanted regions;

A source region having a first conductivity type formed in the epitaxial layer and over the body region, the source region having a doping concentration greater than that of the body region.

In one embodiment of the present application, the distance h1 between the bottom of the lowest implanted region and the upper surface of the substrate is the same as the distance h1 between the bottom of the shielded gate electrode and the upper surface of the substrate. The difference from the distance h2 is in the range of -0.2 μm to 0.2 μm, and the distance h3 between the top of the uppermost implanted region and the upper surface of the substrate is different from the top of the shielded gate electrode and the upper surface of the substrate. The distance h4 between the surfaces differs in the range of -0.2 μm to 0.2 μm.

In an embodiment of the present application, the number of the injection regions is two to five.

In an embodiment of the present application, a plurality of the implanted regions are evenly spaced.

In an embodiment of the present application, the doping concentrations of the plurality of implanted regions are the same.

In an embodiment of the present application, the doping concentrations of the plurality of implanted regions increase or decrease sequentially from top to bottom.

In an embodiment of the present application, the gate structure further includes a control gate electrode located above the shielding gate electrode, a dielectric layer covering the shielding gate electrode and filling the side of the control gate electrode. According to a second aspect of the embodiments of the present application, there is provided a method for manufacturing a trench MOSFET, the method comprising:

preparing an epitaxial layer with a first conductivity type on a substrate with a first conductivity type, the doping concentration of the epitaxial layer is less than that of the substrate;

preparing a plurality of implanted regions with a first conductivity type in the epitaxial layer, the plurality of implanted regions are arranged from top to bottom, and the doping concentration of the implanted regions is greater than the doping concentration of the epitaxial layer;

preparing trenches in the epitaxial layer;

A gate structure is prepared in the trench, the gate structure includes a shielding gate electrode, a control gate electrode located above the shielding gate electrode, and a dielectric covering the shielding gate electrode and filling the side of the control gate electrode layer, the shielding gate electrodes are located on the sides of a plurality of the injection regions;

preparing a body region of a second conductivity type over a plurality of the implanted regions in the epitaxial layer;

A source region having a first conductivity type is prepared in the epitaxial layer over the body region, the source region having a doping concentration greater than that of the body region.

In one embodiment of the present application, the distance h1 between the bottom of the lowest implanted region and the upper surface of the substrate is the same as the distance h1 between the bottom of the shielded gate electrode and the upper surface of the substrate. The difference from the distance h2 is in the range of -0.2 μm to 0.2 μm, and the distance h3 between the top of the uppermost implanted region and the upper surface of the substrate is different from the top of the shielded gate electrode and the upper surface of the substrate. The distance h4 between the surfaces differs in the range of -0.2 μm to 0.2 μm.

In an embodiment of the present application, a plurality of the implanted regions are evenly spaced.

In the trench MOSFET and the manufacturing method thereof provided by the embodiments of the present application, by forming a plurality of injection regions arranged from top to bottom on the side of the control gate electrode in the epitaxial layer, the position of the epitaxial layer on the control gate electrode can be adjusted. Doping concentration at different locations of the section within the height range. When the trench MOSFET is subjected to a reverse voltage, the electric field within the height range of the control gate electrode is significantly increased, so that the withstand voltage of the trench MOSFET can be improved. In addition, since the doping concentration of the plurality of implanted regions is greater than that of the epitaxial layer, the specific on-resistance of the trench MOSFET can be reduced.

Description of drawings

1 is a schematic structural diagram of a trench MOSFET according to an embodiment of the present application;

2 is a schematic structural diagram of another trench MOSFET provided by an embodiment of the present application;

3 is a schematic structural diagram of yet another trench MOSFET provided by an embodiment of the present application;

4 is a schematic structural diagram of yet another trench MOSFET provided by an embodiment of the present application;

5 is a schematic diagram of a trench MOSFET structure and electric field distribution without an implanted region;

6 is a schematic diagram of the structure and electric field distribution of a trench MOSFET provided by an embodiment of the present application;

FIG. 7 is a flowchart of a method for manufacturing a trench MOSFET according to an embodiment of the present application.

The reference numbers in the figure are:

1. Substrate;

2. Epitaxial layer;

3. Groove;

4. Gate structure;

401. Shield grid electrode;

402. Control gate electrode;

403. dielectric layer;

5. Injection area;

6. Body area;

7. Source area;

8. Source;

9. Drain;

10. Insulation layer;

11. Fill the hole.

Detailed ways

Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. Where the following description refers to the drawings, the same numerals in different drawings refer to the same or similar elements unless otherwise indicated. The implementations described in the illustrative examples below are not intended to represent all implementations consistent with this application. Rather, they are merely examples of means consistent with some aspects of the present application as recited in the appended claims.

The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the application. Unless otherwise defined, technical or scientific terms used in this application shall have the ordinary meaning as understood by those of ordinary skill in the art to which this invention belongs. Words like "a" or "an" used in the specification and claims of this application also do not denote a quantitative limitation, but rather denote the presence of at least one. Words like "include" or "include" mean that the elements or items appearing before "including" or "including" cover the elements or items listed after "including" or "including" and their equivalents, and do not exclude other elements or objects. "Connected" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Plurality" includes two, equivalent to at least two. As used in this specification and the appended claims, the singular forms "a," "the," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It will also be understood that the term "and/or" as used herein refers to and includes any and all possible combinations of one or more of the associated listed items.

The shielded gate trench MOSFET and the fabrication method in the embodiments of the present application will be described in detail below with reference to the accompanying drawings. Features in the embodiments and implementations described below may complement each other or be combined with each other without conflict.

1 to FIG. 4 are schematic structural diagrams of a trench MOSFET provided by an embodiment of the present application, FIG. 5 is a schematic diagram of the structure and electric field distribution of a trench MOSFET provided by an embodiment of the present application, and FIG. 6 is an embodiment of the present application. A schematic diagram of the structure and electric field distribution of the trench MOSFET is provided. The trench MOSFET provided by the embodiment of the present application is a low-voltage (less than 100V) MOSFET.

In the embodiments of the present application, the direction from the substrate to the epitaxial layer is upward.

Referring to FIG. 1 to FIG. 4 , the trench MOSFET provided by the embodiment of the present application includes:

a substrate 1 with a first conductivity type;

The epitaxial layer 2 with the first conductivity type is formed on the substrate 1, and the doping concentration of the epitaxial layer 2 is lower than the doping concentration of the substrate 1;

the trench 3 formed in the epitaxial layer 2;

The gate structure 4 filled in the trench 3, the gate structure 4 includes a shielding gate electrode 401;

A plurality of implanted regions 5 with the first conductivity type formed in the epitaxial layer 2, the plurality of implanted regions 5 are arranged from top to bottom and are located on the side of the shielding gate electrode 401, and the doping concentration of the implanted regions 5 is greater than that of the epitaxial layer 2 doping concentration;

a body region 6 of the second conductivity type formed in the epitaxial layer 2 and above the plurality of implanted regions 5;

a source region 7 of the first conductivity type formed in the epitaxial layer 2 and located above the body region 6, the doping concentration of the source region 7 is greater than the doping concentration of the body region 6;

source 8; and

Drain 9.

In the trench MOSFET provided by the embodiment of the present application, by forming a plurality of implantation regions 5 arranged from top to bottom on the side of the shielding gate electrode 401 in the epitaxial layer 2, the position of the epitaxial layer 2 on the shielding gate electrode 401 can be adjusted. The doping concentration at different positions of the section within the height range. Comparing FIG. 5 and FIG. 6, it can be seen that by forming a plurality of injection regions 5 in the part of the epitaxial layer 2 within the height range of the shielding gate electrode 401, when the trench MOSFET is subjected to reverse voltage, the shielding gate electrode 401 can be The electric field in the height range is significantly increased, so the withstand voltage of the trench MOSFET can be improved. And since the doping concentration of the plurality of implanted regions 5 is greater than that of the epitaxial layer 2, the specific on-resistance of the trench MOSFET can be reduced by 15%-20%.

In one embodiment of the present application, the distance h1 between the bottom of the lowermost implanted region 5 and the upper surface of the substrate 1 is different from the distance h2 between the bottom of the shielded gate electrode 401 and the upper surface of the substrate 1 The range is -0.2 μm to 0.2 μm, and the distance h3 between the top of the uppermost implanted region 5 and the upper surface of the substrate 1 is different from the distance h4 between the top of the shielded gate electrode 401 and the upper surface of the substrate 1 The range is -0.2 μm to 0.2 μm. Referring to FIG. 5 , it can be seen that the electric field distribution of the epitaxial layer 2 of the trench MOSFET without the implantation region 5 is formed at a portion corresponding to the shielding gate electrode 401 . The formation of a plurality of implanted regions 5 in the region of the epitaxial layer 2 corresponding to the shielding gate electrode 401 can increase the electric field at the region of the epitaxial layer 2 corresponding to the shielding gate electrode 401, so that the electric field distribution in this region is closer to a rectangle, Thereby, the withstand voltage of the trench MOSFET is improved.

In an embodiment of the present application, the gate structure 4 further includes a control gate electrode 402 located above the shielding gate electrode 401 , a dielectric layer 403 covering the shielding gate electrode 401 , and a dielectric layer 403 filling the side of the control gate electrode 402 . The dielectric layer 403 includes a field oxide layer covering the shielding gate electrode 401 and a gate oxide layer filling the side of the control gate electrode 402 . The field oxide layer located at the bottom and side of the shielded gate electrode 401 can be formed by thermal oxidation deposition, and the field oxide layer located between the shielded gate electrode 401 and the control gate electrode 402 can be formed by high-density plasma chemical vapor deposition (HDP). ) process formed.

In one embodiment of the present application, the number of implanted regions 5 is two to five. The greater the number of implanted regions 5, the closer the electric field distribution of the trench MOSFET is to a rectangle, but at the same time, the complexity of the fabrication process of the trench MOSFET is also increased. Considering the electric field distribution and the complexity of the manufacturing process, the number of implanted regions 5 is preferably three.

In an embodiment of the present application, the plurality of implanted regions 5 are evenly spaced. The plurality of implanted regions 5 are arranged at intervals. Compared with continuous distribution, the manufacturing process is simpler and the manufacturing cost is lower.

In an embodiment of the present application, the doping concentrations of the plurality of implanted regions 5 are the same.

In another embodiment of the present application, the doping concentrations of the plurality of implanted regions 5 increase or decrease sequentially from top to bottom. In other embodiments, the doping concentrations of the plurality of implanted regions 5 may also be distributed irregularly.

For MOSFETs with different sizes and different trench depths, the doping concentration of different distribution ranges can be selected to make the electric field distribution closer to a rectangle. The doping concentration of the implanted region should be determined according to the withstand voltage of the MOSFET.

In one embodiment of the present application, the trench MOSFET further includes an insulating layer 10 over the control gate electrode 402 and the source region 7 . Filled holes 11 are formed in the insulating layer 10 , the body region 6 and the source region 7 . The source electrode 8 includes a metal layer above the insulating layer 10 and a metal filled in the filling hole 11 .

In an embodiment of the present application, the first conductivity type is N-type, and the second conductivity type is P-type. That is, the substrate 1 is an N-type substrate, the epitaxial layer 2 is an N-type epitaxial layer, the body region 6 is formed by P-type doping, the source region 7 is formed by N-type doping, and the implantation region 5 is N-type doping. form.

In the trench MOSFET provided by the embodiment of the present application, the doping concentration and thickness of the epitaxial layer 2 and the implantation region 5 can be determined according to the withstand voltage requirements of the trench MOSFET.

FIG. 7 is a flowchart of a method for manufacturing a trench MOSFET according to an embodiment of the present application. Referring to FIG. 7 , the preparation method includes the following steps 201-210.

In step 201, an epitaxial layer having a first conductivity type is prepared on a substrate having a first conductivity type, and the doping concentration of the epitaxial layer is lower than that of the substrate.

In an embodiment of the present application, the first conductivity type is N-type, and the second conductivity type is P-type.

In an embodiment of the present application, an N-type doped semiconductor may be used as a substrate, and an N-type lightly doped semiconductor may be deposited on the substrate by an epitaxial growth method to form an epitaxial layer.

In step 202, a plurality of implanted regions having the first conductivity type are prepared in the epitaxial layer from top to bottom, and the doping concentration of the implanted regions is greater than that of the epitaxial layer.

Wherein, when preparing multiple injection regions, the multiple injection regions are prepared in the order from bottom to top, that is, the injection regions located below are prepared first, and then the injection regions located above are prepared.

In an embodiment of the present application, the difference between the distance h1 between the bottom of the lowermost implanted region and the upper surface of the substrate and the distance h2 between the bottom of the shielded gate electrode and the upper surface of the substrate is -0.2 μm to 0.2 μm, the difference between the distance h3 between the top of the uppermost implanted region and the upper surface of the substrate and the distance h4 between the top of the shield gate electrode and the upper surface of the substrate is in the range of −0.2 μm to 0.2 μm .

In one embodiment of the present application, a plurality of N-type implanted regions are formed in the epitaxial layer by implanting impurities and annealing.

In one embodiment of the present application, the number of implanted regions is two to five, for example, three.

In one embodiment of the present application, the plurality of implanted regions are evenly spaced. A plurality of implanted regions are arranged at intervals. Compared with continuous distribution, the fabrication process is simpler and the fabrication cost is lower.

In one embodiment of the present application, the doping concentrations of the plurality of implanted regions are the same.

In another embodiment of the present application, the doping concentrations of the plurality of implanted regions increase or decrease sequentially from top to bottom. In other embodiments, the doping concentrations of the plurality of implanted regions may also be randomly distributed.

In step 203, trenches are prepared in the epitaxial layer.

In one embodiment of the present application, trenches are formed in the epitaxial layer by photolithography and etching techniques.

In step 204, a gate structure is prepared in the trench, the gate structure includes a shielded gate electrode.

In the embodiment of the present application, the gate structure further includes a control gate electrode located above the shielding gate electrode, covering the shielding gate electrode and a dielectric layer filled on the side of the control gate electrode, and the shielding gate electrode is located on the side of the plurality of injection regions.

In an embodiment of the present application, the dielectric layer covering the shielding gate electrode is a field oxide layer, and the dielectric layer filling the side of the control gate electrode is a gate oxide layer.

In one embodiment of the present application, a field oxide layer is formed on the bottom and lower sidewalls of the trench by thermal oxidation deposition, a shielded gate electrode is formed by polysilicon deposition and etching technology, and a high-density plasma chemical vapor Deposition (HDP) and etching processes form a field oxide layer above the shielded gate electrode, form a gate oxide layer on the sidewall on the upper side of the trench by thermal oxidation deposition, and form a control layer above the field oxide layer by polysilicon deposition and etching technology gate electrode.

In step 205, a body region of the second conductivity type is prepared in the epitaxial layer over the plurality of implanted regions.

In one embodiment of the present application, the P-type body region is formed in the epitaxial layer by implanting impurities and processing through an annealing process. The P-type body region is spaced apart from the uppermost implanted region.

In step 206 , a source region with a first conductivity type is prepared in the epitaxial layer over the body region, and the doping concentration of the source region is greater than the doping concentration of the body region.

In one embodiment of the present application, an N-type source region is formed on the upper portion of the body region by implanting impurities and annealing.

In step 207, an insulating layer is formed over the control gate electrode and the source region.

In one embodiment of the present application, the insulating layer is formed over the trench and the source region by chemical vapor deposition.

In step 208, contact holes are prepared in the insulating layer, the body region and the source region.

In one embodiment of the present application, contact holes are formed in the insulating layer, the body region and the source region by photolithography and etching techniques.

In step 209, a source electrode is prepared in the contact hole and over the insulating layer.

In an embodiment of the present application, metal is filled in the contact hole and a metal layer is formed over the insulating layer by a metal sputtering process, and the metal and the metal layer in the contact hole constitute a source electrode.

In step 210, a drain is prepared under the substrate.

In one embodiment of the present application, the drain electrode is formed through a metal evaporation process.

In the method for fabricating a trench MOSFET provided by the embodiment of the present application, by forming a plurality of implantation regions located on the side of the control gate electrode from top to bottom in the epitaxial layer, the height of the epitaxial layer on the control gate electrode can be adjusted. The doping concentration at different locations of the section within the range. When the trench MOSFET is subjected to a reverse voltage, the electric field within the height range of the control gate electrode is significantly increased, so that the withstand voltage of the trench MOSFET can be improved. And since the doping concentration of the multiple implanted regions is greater than the doping concentration of the epitaxial layer, the specific on-resistance of the trench MOSFET can be reduced by 15%-20%.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application in any form. Although the present application has been disclosed above with preferred embodiments, it is not intended to limit the present application. Personnel, without departing from the scope of the technical solution of the present application, can make some changes or modifications to equivalent examples of equivalent changes by using the technical content disclosed above, provided that any content that does not depart from the technical solution of the present application, according to this Any simple modifications, equivalent changes and modifications made to the above embodiments by the technical essence of the application still fall within the scope of the technical solutions of the present application.

The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the present application. within the scope of protection.

Claims (10)

1. A trench MOSFET, comprising:

a substrate (1) having a first conductivity type;

an epitaxial layer (2) of a first conductivity type formed over the substrate (1), the doping concentration of the epitaxial layer (2) being lower than the doping concentration of the substrate (1);

a trench (3) formed in the epitaxial layer (2);

a gate structure (4) filled in the trench (3), the gate structure (4) comprising a shield gate electrode (401);

a plurality of injection regions (5) with a first conductivity type formed in the epitaxial layer (2), wherein the plurality of injection regions (5) are arranged from top to bottom and are positioned at the side part of the shielding gate electrode (401), and the doping concentration of the injection regions (5) is greater than that of the epitaxial layer (2);

a body region (6) of a second conductivity type formed in said epitaxial layer (2) and located above said plurality of implanted regions (5);

a source region (7) of the first conductivity type formed in the epitaxial layer (2) and located above the body region (6), the source region (7) having a doping concentration greater than a doping concentration of the body region (6).

2. The trench MOSFET of claim 1 wherein a distance h1 between the bottom of the lowermost implant region (5) and the upper surface of the substrate (1) differs from a distance h2 between the bottom of the shield gate electrode (401) and the upper surface of the substrate (1) by a range of-0.2 μm to 0.2 μm, and a distance h3 between the top of the uppermost implant region (5) and the upper surface of the substrate (1) differs from a distance h4 between the top of the shield gate electrode (401) and the upper surface of the substrate (1) by a range of-0.2 μm to 0.2 μm.

3. The trench MOSFET of claim 1 wherein the number of implanted regions (5) is two to five.

4. The trench MOSFET of claim 1 wherein the plurality of implanted regions (5) are uniformly spaced.

5. Trench MOSFET according to claim 1, characterized in that the doping concentration of a plurality of said implanted regions (5) is the same.

6. The trench MOSFET of claim 1 wherein the doping concentration of the plurality of implanted regions (5) increases or decreases sequentially from top to bottom.

7. The trench MOSFET of claim 1 wherein the gate structure (4) further comprises a control gate electrode (402) over the shield gate electrode (401), a dielectric layer (403) encapsulating the shield gate electrode (401) and filling the sides of the control gate electrode (402).

8. A method of fabricating a trench MOSFET, the method comprising:

preparing an epitaxial layer with a first conductivity type on a substrate with the first conductivity type, wherein the doping concentration of the epitaxial layer is less than that of the substrate;

preparing a plurality of injection regions with a first conductivity type in the epitaxial layer, wherein the plurality of injection regions are distributed from top to bottom, and the doping concentration of the injection regions is greater than that of the epitaxial layer;

preparing a groove in the epitaxial layer;

preparing a gate structure in the trench, wherein the gate structure comprises a shielding gate electrode, a control gate electrode positioned above the shielding gate electrode, a dielectric layer covering the shielding gate electrode and filling the side part of the control gate electrode, and the shielding gate electrode is positioned on the side part of the injection regions;

preparing a body region with a second conductivity type above the plurality of implanted regions in the epitaxial layer;

preparing a source region with the first conductivity type above the body region in the epitaxial layer, wherein the doping concentration of the source region is greater than that of the body region.

9. The method of claim 8, wherein a distance h1 between a bottom of the lowermost implant region and the upper surface of the substrate is in a range of-0.2 μm to 0.2 μm from a distance h2 between a bottom of the shield gate electrode and the upper surface of the substrate, and a distance h1 between a top of the uppermost implant region and the upper surface of the substrate is in a range of-0.2 μm to 0.2 μm from a distance h3 between the top of the shield gate electrode and the upper surface of the substrate.

10. The method of claim 8 wherein the plurality of implanted regions are uniformly spaced.

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