CN107968124A - A kind of semiconductor device structure and preparation method thereof - Google Patents

Abstract

The present invention relates to thin film transistor (TFT) manufacturing field, more particularly to a kind of semiconductor device structure and preparation method thereof, and after being prepared in grid, lightly doped district is formed in substrate using vertical ion injection technology；Continue to prepare barrier layer, with forming side wall on the side wall of grid；Using above-mentioned grid and side wall as mask, vertical ion injection technology is carried out again, and to form the heavily doped region as source-drain electrode in above-mentioned lightly doped district, and lightly doped district is located at region the blocking due to side wall below side wall, its ion concentration still maintains constant, using the lightly doped drain as device（LDD）Area；Due to using vertical ion injection technology, and based on the heavily doped region re-formed on the basis of lightly doped district as source-drain area, the implantation dosage for each region intermediate ion to be formed can be accurately controlled, the depth of injection ion can also be improved at the same time, and can neatly adjust the size of LDD region by adjusting the thickness of side wall.

Description

A kind of semiconductor device structure and preparation method thereof

technical field

The invention relates to the technical field of manufacturing thin film transistors, in particular to a semiconductor device structure and a manufacturing method thereof.

Background technique

With the continuous development of thin film transistor manufacturing technology, its integration level is getting higher and higher, which leads to the continuous shrinking of the length of the conductive channel, and the shorter conductive channel will cause the leakage current of the source and drain to increase and the hot carrier effect generation, which will greatly degrade the performance of thin film transistors.

At present, in order to avoid the above problems, the industry generally adopts the LDD (lightly doped drain) process to improve the performance of the device, that is, by doping the gate inside the gate with a lower dose than the source and drain. Form a lightly doped region under the oxide layer, and then form a doping concentration gradient between the source and drain and the channel to form a higher series resistance at the source and drain, so as to achieve the purpose of suppressing leakage current and hot carrier effect .

However, the dose of ion implantation in the current LDD process is difficult to control, and the depth of ion implantation is limited, which cannot effectively suppress the leakage current and hot carrier effect.

Contents of the invention

In view of the above technical problems, the present invention provides a semiconductor device structure with an LDD region and a manufacturing method thereof, which can accurately control the dose of ion implantation, adjust the size of the LDD region, and increase the depth of ion implantation.

The main technical scheme that the present invention solves the problems of the technologies described above is:

A semiconductor device structure, characterized in that, comprising:

A semiconductor substrate provided with a heavily doped region and a lightly doped drain (LDD) region in contact with the heavily doped region;

a gate disposed on the semiconductor substrate; and

a side wall, disposed on the semiconductor substrate and covering the side wall of the gate;

Wherein, the region where the sidewall is disposed on the semiconductor substrate corresponds to the lightly doped drain region in the semiconductor substrate, and the heavily doped region is located at the lightly doped drain region away from the gate pole side.

Preferably, in the above semiconductor device structure, the semiconductor substrate includes a substrate and a silicon nitride layer, a silicon oxide layer and an N-type substrate covering the substrate in sequence from bottom to top, and the Both the LDD region and the heavily doped region are disposed in the N-type substrate; and

The LDD region is a P-type lightly doped region, and the heavily doped region is a P-type heavily doped region.

Preferably, in the above-mentioned semiconductor device structure, the semiconductor substrate includes a substrate and a silicon nitride layer, a silicon oxide layer and a P-type substrate covering the substrate in sequence from bottom to top, and the Both the LDD region and the heavily doped region are disposed in the P-type substrate; and

The LDD region is an N-type lightly doped region, and the heavily doped region is an N-type heavily doped region.

Preferably, in the above semiconductor device structure, the semiconductor substrate further includes:

The second silicon oxide layer covers the N-type substrate or the P-type substrate, and the gate is arranged on the second silicon oxide layer.

Preferably, in the above semiconductor device structure, the material of the gate includes molybdenum.

Preferably, the above-mentioned semiconductor device structure also includes:

a barrier layer covering the upper surface and sidewalls of the gate, and the exposed upper surface of the semiconductor substrate, and the barrier layer covering the sidewalls of the gate forms the sidewall; wherein ,

The height of the barrier layer is greater than the thickness of the barrier layer.

Preferably, the above-mentioned semiconductor device structure also includes:

The second gate layer covers the barrier layer on the upper surface and the sidewall of the gate, and the material of the second gate layer includes molybdenum.

Preferably, in the above semiconductor device structure, a silicon nitride film is further arranged between the second gate layer and the barrier layer.

Based on the above-mentioned semiconductor device structure, the present invention also provides a method for preparing a semiconductor device structure, which is characterized in that it includes:

providing a semiconductor substrate prepared with a gate;

Using the gate as a mask, using a first vertical ion implantation process to form a lightly doped region in the semiconductor substrate;

preparing sidewalls covering the sidewalls of the gate; and

Using the sidewall and the gate as a mask, using a second vertical ion implantation process in the semiconductor substrate to form a part of the lightly doped region into a heavily doped region;

Wherein, in the second vertical ion implantation process, the lightly doped region that has not been doped twice forms an LDD region.

Preferably, in the above preparation method, silicon oxide or silicon nitride is used to prepare the sidewall.

Preferably, in the above preparation method, the ion concentration implanted by the second vertical ion implantation process is greater than the ion concentration implanted by the first vertical ion implantation process.

Preferably, in the above-mentioned preparation method, the semiconductor substrate includes a substrate and a silicon nitride layer, a silicon oxide layer and an N-type substrate disposed on the substrate in sequence from bottom to top, and the LDD Both the region and the heavily doped region are disposed in the N-type substrate;

Wherein, the LDD region is a P-type lightly doped region, and the heavily doped region is a P-type heavily doped region.

Preferably, in the above preparation method, the semiconductor substrate includes a substrate and a silicon nitride layer, a silicon oxide layer and a P-type substrate arranged on the substrate in sequence from bottom to top, and the LDD Both the region and the heavily doped region are disposed in the P-type substrate;

Wherein, the LDD region is an N-type lightly doped region, and the heavily doped region is an N-type heavily doped region.

Preferably, in the above preparation method, the semiconductor substrate further includes:

The second silicon oxide layer covers the N-type substrate or the P-type substrate, and the gate is arranged on the second silicon oxide layer.

Preferably, in the above preparation method, the width of the LDD region is consistent with the thickness of the sidewall; and

The width of the LDD region is adjusted by adjusting the thickness of the sidewall.

Preferably, in the above preparation method, the step of preparing the sidewall covering the sidewall of the gate comprises:

preparing a barrier layer covering the upper surface and sidewalls of the gate, and the exposed upper surface of the semiconductor substrate, wherein the barrier layer covering the sidewalls of the gate forms the sidewalls, and the The height of the side wall is greater than the thickness of the side wall.

Preferably, in the above preparation method, before performing the second vertical ion implantation process, the preparation method further includes:

Etching the blocking layer partially covering the exposed upper surface of the semiconductor substrate in a vertical orientation, so as to increase the ion implantation depth of the heavily doped region.

Preferably, in the above preparation method, after the step of forming the heavily doped region and the LDD region, the method further includes:

A second gate layer is formed by sputtering on the gate to increase the capacitance formed between the gate and the gate.

The above technical solution has the following advantages or beneficial effects:

The present invention forms a lightly doped region in the substrate by using a vertical ion implantation process after the grid is prepared; continues to prepare the oxide film layer to form a side wall on the side wall of the grid; The wall is used as a mask, and the vertical ion implantation process is performed again to form a heavily doped region as a source and drain in the lightly doped region, and the lightly doped region is located under the sidewall due to the shielding of the sidewall and the gate. , its ion concentration remains unchanged to serve as the LDD region of the device; since the vertical ion implantation process is adopted, and the heavily doped region as the source and drain region is formed on the basis of the lightly doped region, it can be precisely controlled The implantation dose of ions in each formed region can also increase the depth of implanted ions, and the size of the LDD region can be flexibly adjusted by adjusting the thickness of the sidewall.

Description of drawings

Embodiments of the present invention are more fully described with reference to the accompanying drawings. However, the accompanying drawings are for illustration and illustration only, and do not limit the scope of the present invention.

Fig. 1 is the flow chart of the preparation method of semiconductor device structure of the present invention;

2 to 4 are structural diagrams of various steps in the manufacturing process of the semiconductor device structure of the present invention.

Detailed ways

In the following description, numerous specific details are given in order to provide a more thorough understanding of the present invention. Of course, the present invention can also have other embodiments besides these detailed descriptions.

The semiconductor device structure with the LDD region and the preparation method thereof provided by the present invention are aimed at precisely controlling the dose of ion implantation, and adjusting the size of the LDD region by adjusting the thickness of the sidewall, so as to provide more adjustment parameters for the process; at the same time Combined with the method of directional etching part of the barrier layer perpendicular to the substrate, the depth of ion implantation is increased; after the ion implantation is completed, the second gate layer can be continuously formed or the second gate layer can be sputtered after continuing to deposit silicon nitride film, thereby Adjust the capacity of the capacitance formed between the two layers of gates.

The structure of the semiconductor device and its manufacturing method of the present invention will be described in detail below in conjunction with specific embodiments and accompanying drawings.

With reference to shown in Figure 1, the preparation method of semiconductor device structure of the present invention comprises the following steps:

In the first step, a semiconductor substrate 1 prepared with a gate 2 is provided, and its specific structure is _shown in FIG. A silicon layer (SiO _x ) 12 , an N-type substrate (N—Si) 13 and a second silicon oxide layer (SiO _x ) 14 , and the gate 2 is disposed on the second silicon oxide layer 14 . It should be noted that this embodiment uses the N-type substrate (N-Si) 13 as an example for illustration, and in practical applications, it can also be replaced with a P-type substrate (P-Si) according to the requirements of the thin film transistor to be prepared. In this embodiment, ions are subsequently implanted into the N-type substrate 13 to form a P-doped region. If it is a P-type substrate in other embodiments, ions are subsequently implanted to form an N-doped region.

As a preferred embodiment, the material of the gate 2 may include metal molybdenum (Mo), which has the advantages of high melting point, low expansion coefficient and low secondary electron emission rate.

In the second step, using the gate 2 as a mask, the first vertical ion implantation process is used to form a lightly doped region 3 in the substrate 13 of the semiconductor substrate 1 (because the substrate 13 of this embodiment is an N-type substrate, therefore The implanted ions are P-type ions, that is, the formed lightly doped region 3 is a P-type lightly doped region (P−)).

As a preferred embodiment, in the second step, because the vertical ion implantation process is adopted, that is, the angle of ion implantation is perpendicular to the substrate 10, it can be ensured that no ions are implanted in the substrate 13 below the gate 2, that is, light The doped P-region 3 is only formed on the surface of the remaining substrate 13 except the substrate 13 vertically corresponding to the gate 2, so as to facilitate subsequent ion implantation in the lightly doped P-region 3 formed on the substrate 13. source drain.

The third step, referring to FIG. 3 , prepares a barrier layer 5 covering the upper surface and sidewalls of the gate 2, and the exposed upper surface of the semiconductor substrate 1 (that is, the upper surface of the second silicon oxide layer 14 not covered by the gate 2 ). surface), the barrier layer 5 forms sidewalls 50 on the sidewalls of the gate 2 . In this step, the thickness of the barrier layer 5 deposited on the upper surface of the gate 2 is consistent with the thickness deposited on the exposed upper surface of the semiconductor substrate 1 .

Continue to the fourth step, continue to refer to FIG. 3, use the sidewall 50 and the gate 2 as a mask, and adopt the second vertical ion implantation process (similar to the first vertical ion implantation process in the second step, the angle of the ion implantation is controlled to be vertical For the substrate 10, it can be ensured that the substrate 13 below the gate 2 and the sidewall 50 is not implanted with ions, that is, the second vertical ion implantation process is controlled to only implant ions except those vertically corresponding to the gate 2 and the sidewall 50. lightly doped P-region 3 other than the lightly doped P-region 3 ) to form a heavily doped region (P+) 4 in the lightly doped region 3 .

As a preferred embodiment, after the heavily doped region (P+) 4 is formed, only the region 30 vertically corresponding to the sidewall 50 remains in the lightly doped P- region 3, and this region 30 is the LDD to be prepared in the present invention ( lightly doped drain (lightly doped drain) region, that is, the LDD region 30 is located in the substrate 13 adjacent to the gate 2, and the heavily doped region 4 is located on the other side of the LDD region 30 relative to the gate 2 and is connected to the LDD District 30 contacts. Preferably, the width of the LDD region 30 is consistent with the thickness of the sidewall 50, and by adjusting the thickness of the sidewall 50, the width of the LDD region 30 can be flexibly adjusted to achieve precise control of the dose of ion implantation; and by adjusting the thickness of the sidewall Adjusting the size of the LDD region 30 with a thickness of 50 can provide more adjustment parameters for the manufacturing process of the thin film transistor, so as to flexibly adapt to the manufacturing of thin film transistors with different requirements.

In this embodiment, due to the barriers of the gate 2 and the sidewall 50, the heavily doped region (P+) 4 can be precisely formed in the lightly doped P- Zone 3. At the same time, it should be noted that because the barrier layer 5 has the function of inhibiting ion penetration, it is necessary to ensure that a better mask blocking effect is formed under the LDD region 30 and the gate 2 in the second vertical ion implantation process, covering the second oxide layer. The thickness of the barrier layer 5 on the exposed upper surface of the silicon layer 14 should be smaller than the thickness of the barrier layer 5 covering the upper surface and sidewalls of the gate 2; etch the barrier layer 5 partially covering the exposed upper surface of the second silicon oxide layer 14 (that is, partially etch the barrier layer 5 above the heavily doped region 4 to be formed perpendicular to the substrate 10) to improve the heavily doped region to be formed. The ion implantation depth of impurity region 4.

As a preferred embodiment, the barrier layer 5 may be made of silicon oxide (SiO _x ) or silicon nitride (SiN _x ).

Preferably, the heavily doped region 4 can be used as the source and drain of the thin film transistor. Due to the existence of the lightly doped LDD region 30, a doping concentration gradient can be formed between the source and drain and the channel, so that the source and drain The terminal forms a higher series resistance, so as to achieve the purpose of suppressing leakage current and hot carrier effect.

After the ion implantation forms the heavily doped region 4 and the LDD region 30, it may also include:

In the fifth step, referring to FIG. 4 , the second gate layer 7 is formed by sputtering on the gate 2 to achieve the purpose of adjusting the capacitance formed between the second gate layer 7 and the gate 2 . Preferably, the material of the second gate layer 7 may include molybdenum.

Further, before forming the second gate layer 7 by sputtering, a layer of silicon nitride (SiN _x ) film 6 can be deposited on the barrier layer 5, and then the corresponding gate 2 can be deposited on the silicon nitride film 6 The position of sputtering forms the second gate layer 7, thereby adjusting the capacity of the capacitance formed between the two gate layers.

In summary, the semiconductor device structure with LDD region and its preparation method provided by the present invention, after the gate is prepared, a lightly doped region is formed in the substrate by using a vertical ion implantation process; continue to prepare the barrier film layer, Forming sidewalls on the sidewalls of the gate; using the above-mentioned gate and sidewalls as masks, performing a vertical ion implantation process again to form heavily doped regions as source and drain in the above-mentioned lightly doped regions, The area of the lightly doped region under the sidewall is shielded by the sidewall and the gate, and its ion concentration remains unchanged to serve as the LDD region of the device; due to the vertical ion implantation process, it is based on the lightly doped region Based on the formation of heavily doped regions as the source and drain regions, the implantation dose of ions in each region formed can be precisely controlled; at the same time, the depth of implanted ions can be increased by directional etching of part of the barrier layer perpendicular to the substrate , and the size of the LDD region can be flexibly adjusted by adjusting the thickness of the sidewall.

Various changes and modifications will no doubt become apparent to those skilled in the art upon reading the foregoing description. Therefore, the appended claims should be considered to cover all changes and modifications within the true intent and scope of the invention. Any and all equivalent scope and content within the scope of the claims should still be deemed to be within the intent and scope of the present invention.

Claims (18)

1. A semiconductor device structure, characterized in that, comprising: A semiconductor substrate is provided with a heavily doped region and a lightly doped drain region in contact with the heavily doped region; a gate disposed on the semiconductor substrate; and a side wall, disposed on the semiconductor substrate and covering the side wall of the gate; Wherein, the region where the sidewall is disposed on the semiconductor substrate corresponds to the lightly doped drain region in the semiconductor substrate, and the heavily doped region is located at the lightly doped drain region away from the gate pole side. 2. The semiconductor device structure according to claim 1, wherein the semiconductor substrate comprises a substrate and a silicon nitride layer, a silicon oxide layer and an N-type substrate that are sequentially stacked and covered on the substrate, and Both the lightly doped drain region and the heavily doped region are disposed in the N-type substrate; wherein, Both the lightly doped drain region and the heavily doped region are P-type doped regions. 3. The semiconductor device structure according to claim 1, wherein the semiconductor substrate comprises a substrate and a silicon nitride layer, a silicon oxide layer and a P-type substrate that are sequentially stacked and covered on the substrate, and Both the lightly doped drain region and the heavily doped region are disposed in the P-type substrate; wherein, Both the lightly doped drain region and the heavily doped region are N-type doped regions. 4. The semiconductor device structure according to claim 2 or 3, wherein the semiconductor substrate further comprises: The second silicon oxide layer covers the N-type substrate or the P-type substrate, and the gate is arranged on the second silicon oxide layer. 5. The semiconductor device structure according to claim 1, wherein the material of the gate comprises molybdenum. 6. The semiconductor device structure according to claim 1, further comprising: a barrier layer covering the upper surface and sidewalls of the gate, and part of the upper surface of the semiconductor substrate, and the barrier layer covering the sidewalls of the gate forms the sidewall; wherein , The height of the barrier layer is greater than the thickness of the barrier layer. 7. The semiconductor device structure according to claim 6, further comprising: The second gate layer covers the barrier layer on the upper surface and the sidewall of the gate, and the material of the second gate layer includes molybdenum. 8. The semiconductor device structure according to claim 7, wherein a silicon nitride film is further disposed between the second gate layer and the barrier layer. 9. A method for preparing a semiconductor device structure, comprising: providing a semiconductor substrate prepared with a gate; Using the gate as a mask, using a first vertical ion implantation process to form a lightly doped region in the semiconductor substrate; preparing sidewalls with the sidewalls of the gate; and Using the sidewall and the gate as a mask, using a second vertical ion implantation process in the semiconductor substrate to form a part of the lightly doped region into a heavily doped region; Wherein, in the second vertical ion implantation process, the lightly doped region that has not been doped twice forms a lightly doped drain region. 10 . The preparation method according to claim 9 , wherein the sidewall is prepared by silicon oxide or silicon nitride. 11 . 11. The manufacturing method according to claim 9, wherein the concentration of ions implanted by the second vertical ion implantation process is greater than the concentration of ions implanted by the first vertical ion implantation process. 12. The preparation method according to claim 9, wherein the semiconductor substrate comprises a substrate and a silicon nitride layer, a silicon oxide layer, and an N-type substrate arranged sequentially on the substrate from bottom to top. a substrate, and both the lightly doped drain region and the heavily doped region are disposed in the N-type substrate; Wherein, both the lightly doped drain region and the heavily doped region are P-type doped regions. 13. The preparation method according to claim 9, wherein the semiconductor substrate comprises a substrate and a silicon nitride layer, a silicon oxide layer, and a P-type substrate arranged sequentially on the substrate from bottom to top. a substrate, and both the lightly doped drain region and the heavily doped region are disposed in the P-type substrate; Wherein, both the lightly doped drain region and the heavily doped region are N-type doped regions. 14. The preparation method according to claim 12 or 13, wherein the semiconductor substrate further comprises: The second silicon oxide layer covers the N-type substrate or the P-type substrate, and the gate is arranged on the second silicon oxide layer. 15. The preparation method according to claim 9, wherein the width of the lightly doped drain region is consistent with the thickness of the sidewall; and The width of the lightly doped drain region is adjusted by adjusting the thickness of the sidewall. 16. The preparation method according to claim 9, wherein the step of preparing a sidewall covering the sidewall of the gate comprises: preparing a barrier layer covering the upper surface and sidewalls of the gate, and the exposed upper surface of the semiconductor substrate, wherein the barrier layer covering the sidewalls of the gate forms the sidewalls, and the The height of the side wall is greater than the thickness of the side wall. 17. The preparation method according to claim 16, wherein, before performing the second vertical ion implantation process, the preparation method further comprises: Etching the blocking layer partially covering the exposed upper surface of the semiconductor substrate in a vertical orientation, so as to increase the ion implantation depth of the heavily doped region. 18. The preparation method according to claim 9, characterized in that, after the step of forming the heavily doped region and the lightly doped drain region, the method further comprises: A second gate layer is formed by sputtering on the gate to increase the capacitance formed between the gate and the gate.