CN110658439B - Test method and system for protection circuit - Google Patents
Test method and system for protection circuit Download PDFInfo
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- CN110658439B CN110658439B CN201910867074.8A CN201910867074A CN110658439B CN 110658439 B CN110658439 B CN 110658439B CN 201910867074 A CN201910867074 A CN 201910867074A CN 110658439 B CN110658439 B CN 110658439B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
- G01R31/2827—Testing of electronic protection circuits
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Abstract
本发明提供了一种保护电路的测试方法及系统，本发明通过将芯片控制电路分别连接至GUI操作界面端和待测主板端，将GUI控制芯片与安装有GUI操作界面的计算机通过USB3.0接口连接，另外与待测主板通过I2C接口连接，将模拟电路控制芯片与I2C接口连接，并在模拟电路控制芯片上连接多个可调精密电阻，从而实现在GUI操作界面中对待测主板上的电流进行测试，在测试过程中，只需连接好仪器，打开GUI操作界面即可进行测试，测试成本低且操作简单，提高了工作效率以及测试精确度，减少人力工时。
The invention provides a testing method and system for a protection circuit. The invention connects the chip control circuit to the GUI operation interface end and the mainboard end to be tested respectively, and connects the GUI control chip and the computer with the GUI operation interface through USB3.0 Interface connection, in addition to the motherboard to be tested through the I2C interface, the analog circuit control chip is connected to the I2C interface, and multiple adjustable precision resistors are connected to the analog circuit control chip, so as to realize the GUI operation interface on the motherboard to be tested. During the test process, you only need to connect the instrument and open the GUI operation interface to conduct the test. The test cost is low and the operation is simple, which improves the work efficiency and test accuracy, and reduces labor hours.
Description
Technical Field
The invention relates to the technical field of protection circuit testing, in particular to a method and a system for testing a protection circuit.
Background
Along with the deepening of artificial intelligence, the requirements on power and performance of a server are higher and higher, and more server mainboards and other board cards need to introduce a design protection circuit in the development stage so as to prevent a 12V power supply link from being burnt.
The performance of the current server is more and more demanding, and the transition from the previous 2-way to the 4-way and 8-way is already carried out, and the 12V power supply provided by the power supply is simultaneously used as the input of a plurality of groups of secondary lines. In order to prevent the situation that a main board is burnt out due to overcurrent input caused by overcurrent in one group of secondary circuits, a circuit protection design is often required to be introduced, for the circuit protection design, a chip register address is identified through BMC I2C, and currents at two ends of a sense resistor or a sense inductor are read through BMC.
In the operation process, software is needed to debug the BMC, the corresponding sense resistor or sense inductor is found through the debugging software, and the address of a chip register is identified, so that the test is not stable enough and the operation is complex due to BMC interference in the process.
Disclosure of Invention
The invention aims to provide a test method and a test system of a protection circuit, which aim to solve the problems of instability and complex operation caused by BMC interference in the prior art in the test of the protection circuit, realize the test of the current on a mainboard to be tested in a GUI operation interface, improve the working efficiency and the test accuracy and reduce the labor hour.
In order to achieve the technical purpose, the invention provides a test method of a protection circuit, which comprises the following steps:
s1, connecting the chip control circuit to the GUI operation interface end and the main board end to be tested respectively;
s2, after the mainboard to be tested is electrified, selecting the model of the chip and the register address of the channel to be tested, and determining a test circuit;
s3, selecting a channel to be tested, setting the resistance value of the measured resistance of the channel to be tested, and inputting a voltage protection value into the channel to be tested of the OTC;
and S4, selecting a channel to be tested on the GUI operation interface, monitoring the current, and indicating and alarming when the loading current exceeds the designed current value.
Preferably, the connection mode of the chip control circuit, the GUI operation interface end and the main board end to be tested is as follows:
the chip control circuit is connected with the GUI operation interface end through a USB3.0 interface and connected with the mainboard end to be tested through an I2C interface;
the chip control circuit comprises a GUI control chip and an analog circuit control chip, the GUI control chip is connected with a USB3.0 interface and an I2C interface respectively, the analog circuit control chip is connected with an I2C interface, and the analog circuit control chip is further connected with a plurality of adjustable resistors.
Preferably, the I2C interface transfers Data, CLK, and GND signals.
Preferably, the number of the adjustable resistors is 4.
The invention also provides a test system of the protection circuit, which comprises:
the circuit connection module is used for respectively connecting the chip control circuit to the GUI operation interface end and the main board end to be tested;
the test circuit determination module is used for selecting the model of the chip and the register address of the channel to be tested after the mainboard to be tested is powered on, and determining the test circuit;
the parameter setting module is used for selecting a channel to be tested, setting the resistance value of the measured resistance of the channel to be tested, and inputting a voltage protection value into the channel to be tested of the OTC;
and the current monitoring module is used for checking a channel to be tested on the GUI operation interface and indicating and alarming when the loading current exceeds the designed current value.
Preferably, the connection mode of the chip control circuit, the GUI operation interface end and the main board end to be tested is as follows:
the chip control circuit is connected with the GUI operation interface end through a USB3.0 interface and connected with the mainboard end to be tested through an I2C interface;
the chip control circuit comprises a GUI control chip and an analog circuit control chip, the GUI control chip is connected with a USB3.0 interface and an I2C interface respectively, the analog circuit control chip is connected with an I2C interface, and the analog circuit control chip is further connected with a plurality of adjustable resistors.
Preferably, the I2C interface transfers Data, CLK, and GND signals.
Preferably, the number of the adjustable resistors is 4.
The effect provided in the summary of the invention is only the effect of the embodiment, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:
compared with the prior art, the invention has the advantages that the chip control circuit is respectively connected to the GUI operation interface end and the main board end to be tested, the GUI control chip is connected with the computer provided with the GUI operation interface through the USB3.0 interface, in addition, the GUI control chip is connected with the main board to be tested through the I2C interface, the analog circuit control chip is connected with the I2C interface, and the analog circuit control chip is connected with the plurality of adjustable precision resistors, so that the current on the main board to be tested in the GUI operation interface can be tested only by connecting the instrument in the test process, the GUI operation interface can be opened for testing, the test cost is low, the operation is simple, the work efficiency and the test precision are improved, and the labor hour is reduced.
Drawings
Fig. 1 is a flowchart of a method for testing a protection circuit according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a chip control circuit structure according to an embodiment of the present invention;
fig. 3 is a block diagram of a test system of a protection circuit according to an embodiment of the present invention.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
The following describes a test method and a test system for a protection circuit according to an embodiment of the present invention in detail with reference to the accompanying drawings.
As shown in fig. 1, the present invention discloses a method for testing a protection circuit, the method comprising the steps of:
s1, connecting the chip control circuit to the GUI operation interface end and the main board end to be tested respectively;
s2, after the mainboard to be tested is electrified, selecting the model of the chip and the register address of the channel to be tested, and determining a test circuit;
s3, selecting a channel to be tested, setting the resistance value of the measured resistance of the channel to be tested, and inputting a voltage protection value into the channel to be tested of the OTC;
and S4, checking a channel to be tested on the GUI operation interface, and when the loading current exceeds the designed current value, indicating and alarming.
The GUI operation interface is installed on a personal computer, the GUI operation interface is connected to a chip control circuit through a USB interface, and then is connected to a mainboard to be tested through Data, CLK and GND signal transmission lines of I2C, the chip control scheme is shown in figure 2, the GUI control chip is connected to an I2C interface of the mainboard to be tested through Data, CLK and GND signal transmission lines, and is connected to a computer provided with a GUI operation system through a USB3.0 interface, the analog circuit control chip is connected with a plurality of adjustable precision resistors, the number of the resistors is preferably 4, and when different channels are tested, the resistance value of the resistors can be adjusted according to circuit design.
For current monitoring, current detection of 4 channels can be included, currents under different output loading conditions of each channel are read and displayed into a 16-system representation, and when the loading current exceeds the current value required by circuit design, an alarm is given on a current display interface. For the current display, when the output loading current of the circuit changes, the current change can be accurately observed in real time through displaying by a real-time current scroll bar.
When connecting the chip, chip discernment can appear, thereby distinguish the chip model, then can confirm this chip, after having confirmed the chip model, through I2C discernment burn board-proof chip register address, after the chip address is confirmed, can select the passageway that needs the test, adjust the resistance to the resistance of precision resistance through adjusting the slide rheostat, simulate mainboard precision resistance, detect mainboard electric current through the GUI interface through I2C, can set up the withstand voltage value of precision resistance through the GUI interface simultaneously, thereby set up the OCP point, when reaching the OCP electric current, the warning suggestion of GUI interface.
During testing, the chip control circuit board is connected to the interface end through the USB interface, and the chip control circuit board is connected to the mainboard to be tested through the I2C at the interface end. And electrifying the mainboard to be tested, selecting the model of the chip by connecting the chip, and then selecting the register address of the channel to be tested to determine the circuit to be tested. According to the circuit design requirement parameters, selecting a channel to be tested, setting a sense resistor resistance value filled in the tested channel, inputting a voltage protection value in the circuit design requirement in a channel to be tested of the OTC, converting the voltage into 16-system input according to the chip specification, and observing whether the current protection value of the channel to be tested at the channel setting position meets the design requirement. After the relevant setting is finished, switching to a current display interface, and checking a channel to be tested, namely obtaining the current value flowing through the precision resistor under different conditions of outputting the loading current, wherein the current value is displayed in a 16-system mode, when the loading current exceeds the current value required by circuit design, a red light at an OC position in the current display interface is lightened, and when the current value does not exceed the current value, a green light at the OC position is displayed.
In the embodiment of the invention, the chip control circuit is respectively connected to the GUI operation interface end and the main board end to be tested, the GUI control chip is connected with a computer provided with the GUI operation interface through a USB3.0 interface, and is also connected with the main board to be tested through an I2C interface, the analog circuit control chip is connected with an I2C interface, and a plurality of adjustable precision resistors are connected on the analog circuit control chip, so that the current on the main board to be tested in the GUI operation interface can be tested only by connecting an instrument and opening the GUI operation interface in the testing process, the testing cost is low, the operation is simple, the working efficiency and the testing precision are improved, and the labor hour is reduced.
As shown in fig. 3, an embodiment of the present invention further discloses a test system for a protection circuit, where the test system includes:
the circuit connection module is used for respectively connecting the chip control circuit to the GUI operation interface end and the main board end to be tested;
the test circuit determination module is used for selecting the model of the chip and the register address of the channel to be tested after the mainboard to be tested is powered on, and determining the test circuit;
the parameter setting module is used for selecting a channel to be tested, setting the resistance value of the measured resistance of the channel to be tested, and inputting a voltage protection value into the channel to be tested of the OTC;
and the current monitoring module is used for checking a channel to be tested on the GUI operation interface and indicating and alarming when the loading current exceeds the designed current value.
The GUI operation interface is installed on a personal computer, the GUI operation interface is connected to a chip control circuit through a USB interface, and then is connected to a mainboard to be tested through Data, CLK and GND signal transmission lines of I2C, the chip control scheme is shown in figure 2, the GUI control chip is connected to an I2C interface of the mainboard to be tested through Data, CLK and GND signal transmission lines, and is connected to a computer provided with a GUI operation system through a USB3.0 interface, the analog circuit control chip is connected with a plurality of adjustable precision resistors, the number of the resistors is preferably 4, and when different channels are tested, the resistance value of the resistors can be adjusted according to circuit design.
For current monitoring, current detection of 4 channels can be included, currents under different output loading conditions of each channel are read and displayed into a 16-system representation, and when the loading current exceeds the current value required by circuit design, an alarm is given on a current display interface. For the current display, when the output loading current of the circuit changes, the current change can be accurately observed in real time through displaying by a real-time current scroll bar.
When connecting the chip, chip discernment can appear, thereby distinguish the chip model, then can confirm this chip, after having confirmed the chip model, through I2C discernment burn board-proof chip register address, after the chip address is confirmed, can select the passageway that needs the test, adjust the resistance to the resistance of precision resistance through adjusting the slide rheostat, simulate mainboard precision resistance, detect mainboard electric current through the GUI interface through I2C, can set up the withstand voltage value of precision resistance through the GUI interface simultaneously, thereby set up the OCP point, when reaching the OCP electric current, the warning suggestion of GUI interface.
During testing, the chip control circuit board is connected to the interface end through the USB interface, and the chip control circuit board is connected to the mainboard to be tested through the I2C at the interface end. And electrifying the mainboard to be tested, selecting the model of the chip by connecting the chip, and then selecting the register address of the channel to be tested to determine the circuit to be tested. According to the circuit design requirement parameters, selecting a channel to be tested, setting a sense resistor resistance value filled in the tested channel, inputting a voltage protection value in the circuit design requirement in a channel to be tested of the OTC, converting the voltage into 16-system input according to the chip specification, and observing whether the current protection value of the channel to be tested at the channel setting position meets the design requirement. After the relevant setting is finished, switching to a current display interface, and checking a channel to be tested, namely obtaining the current value flowing through the precision resistor under different conditions of outputting the loading current, wherein the current value is displayed in a 16-system mode, when the loading current exceeds the current value required by circuit design, a red light at an OC position in the current display interface is lightened, and when the current value does not exceed the current value, a green light at the OC position is displayed.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (2)
1. A method of testing a protection circuit, the method comprising the steps of:
s1, connecting the chip control circuit to the GUI operation interface end and the main board end to be tested respectively;
s2, after the mainboard to be tested is electrified, selecting the model of the chip and the register address of the channel to be tested, and determining a test circuit;
s3, selecting a channel to be tested, setting the resistance value of the measured resistance of the channel to be tested, and inputting a voltage protection value into the channel to be tested of the OTC;
s4, selecting a channel to be tested on the GUI operation interface, monitoring the current, and when the loading current exceeds the designed current value, giving an indication alarm;
the connection mode of the chip control circuit, the GUI operation interface end and the main board end to be tested is as follows:
the chip control circuit is connected with the GUI operation interface end through a USB3.0 interface and connected with the mainboard end to be tested through an I2C interface;
the chip control circuit comprises a GUI control chip and an analog circuit control chip, wherein the GUI control chip is respectively connected with a USB3.0 interface and an I2C interface, the analog circuit control chip is connected with an I2C interface, and the analog circuit control chip is also connected with a plurality of adjustable resistors;
the I2C interface transfers Data, CLK, and GND signals;
the number of the adjustable resistors is 4.
2. A test system for a protection circuit, the test system comprising:
the circuit connection module is used for respectively connecting the chip control circuit to the GUI operation interface end and the main board end to be tested;
the test circuit determination module is used for selecting the model of the chip and the register address of the channel to be tested after the mainboard to be tested is powered on, and determining the test circuit;
the parameter setting module is used for selecting a channel to be tested, setting the resistance value of the measured resistance of the channel to be tested, and inputting a voltage protection value into the channel to be tested of the OTC;
the current monitoring module is used for checking a channel to be tested on a GUI operation interface and giving an indication alarm when the loading current exceeds a designed current value;
the connection mode of the chip control circuit, the GUI operation interface end and the main board end to be tested is as follows:
the chip control circuit is connected with the GUI operation interface end through a USB3.0 interface and connected with the mainboard end to be tested through an I2C interface;
the chip control circuit comprises a GUI control chip and an analog circuit control chip, wherein the GUI control chip is respectively connected with a USB3.0 interface and an I2C interface, the analog circuit control chip is connected with an I2C interface, and the analog circuit control chip is also connected with a plurality of adjustable resistors;
the I2C interface transfers Data, CLK, and GND signals;
the number of the adjustable resistors is 4.
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| CN201910867074.8A CN110658439B (en) | 2019-09-12 | 2019-09-12 | Test method and system for protection circuit |
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| CN112906076B (en) * | 2021-02-19 | 2022-11-25 | 山东英信计算机技术有限公司 | Control method and system of over-current protection chip and related components |
| CN113868040B (en) * | 2021-08-30 | 2023-07-25 | 浪潮(山东)计算机科技有限公司 | Psys automatic test system, psys automatic test method, psys automatic test construction method and Psys automatic test construction device |
| CN114019267B (en) * | 2021-09-30 | 2024-01-19 | 苏州浪潮智能科技有限公司 | Overcurrent protection test method, device, equipment and readable storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101650411A (en) * | 2009-07-31 | 2010-02-17 | 迈普通信技术股份有限公司 | Universal power-aging testing system |
| CN201876522U (en) * | 2009-12-31 | 2011-06-22 | 杭州士兰微电子股份有限公司 | General test equipment |
| CN103268144A (en) * | 2013-06-07 | 2013-08-28 | 张宁 | Power monitoring device and overcurrent protection method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100761175B1 (en) * | 2004-10-22 | 2007-09-21 | 엘지전자 주식회사 | Monitor integrated circuit error test apparatus and method |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101650411A (en) * | 2009-07-31 | 2010-02-17 | 迈普通信技术股份有限公司 | Universal power-aging testing system |
| CN201876522U (en) * | 2009-12-31 | 2011-06-22 | 杭州士兰微电子股份有限公司 | General test equipment |
| CN103268144A (en) * | 2013-06-07 | 2013-08-28 | 张宁 | Power monitoring device and overcurrent protection method |
Non-Patent Citations (1)
| Title |
|---|
| "基于TOP244Y的12V新型本安电源的设计";刘峥等;《电子世界》;20131231;第60-61页 * |
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