CN110649140A - Processing method of display chip and double-layer wafer plate - Google Patents

Abstract

The invention discloses a display chip processing method and a double-layer wafer board. The method mainly includes: providing a first wafer, the first wafer including a plurality of first chips arranged in a matrix; providing a second wafer A wafer, the second wafer includes a plurality of second chips arranged in a matrix; the first wafer and the second wafer are bonded to form a double-layer wafer board, the double-layer wafer The first chips are electrically connected to the second chips in one-to-one correspondence; the double-layer wafer plate is cut to obtain a plurality of display chip modules, each display chip module includes a first chip and a second chip. Through the method, the process complexity of the display chip module processing is reduced, and the efficient processing of the display chip module is realized.

Description

A processing method of a display chip and a double-layer wafer board

technical field

Embodiments of the present invention relate to the field of enhanced display technology, and in particular, to a processing method of a display chip and a double-layer wafer plate.

Background technique

With the development of display technology, people's requirements for display devices are getting higher and higher. In recent years, Micro-LED Display, as a new generation of display technology, has the advantages of self-illumination, simple structure, small size and energy saving. people's attention. Micro-LED is a display technology that miniaturizes and matrixes the traditional LED structure, and uses integrated circuit technology to make a driving circuit to realize the address control and individual driving of each pixel.

The existing process flow of making Micro-LED display chip modules is to cut the wafer with multiple Micro-LED driver chips and the wafer with multiple Micro-LED chips respectively to obtain a single micro-LED chip. LED driver chip and Micro-LED chip, and then bond the Micro-LED driver chip and Micro-LED chip one by one to form a Micro-LED display chip module.

The processing method has the following defects: two cutting operations are required in the process of making the Micro-LED display chip module, and the process is relatively complicated; when making the Micro-LED display chip module, only a single bonding can be performed, and the bonding efficiency is low; The bonding operation also makes the consistency of different Micro-LED display chip modules poor.

SUMMARY OF THE INVENTION

In view of this, the present invention provides a processing method of a display chip and a double-layer wafer plate, so as to realize the efficient processing of the display chip module.

In a first aspect, an embodiment of the present invention provides a method for processing a display chip, including the following steps:

providing a first wafer, the first wafer includes a plurality of first chips arranged in a matrix;

providing a second wafer, the second wafer includes a plurality of second chips arranged in a matrix;

bonding the first wafer and the second wafer to form a double-layer wafer board, and the first chips of the double-layer wafer are electrically connected to the second chips in one-to-one correspondence;

The double-layer wafer plate is cut to obtain a plurality of display chip modules, each of which includes a first chip and a second chip that are electrically connected.

Specifically, the providing the first wafer includes: forming the silicon wafer into a first wafer including a plurality of first chips arranged in a matrix.

Specifically, the providing the second wafer includes: forming a gallium nitride epitaxial wafer into a second wafer including a plurality of second chips arranged in a matrix.

Preferably, the first chip is a Micro-LED driver chip;

The second chip is a Micro-LED chip.

Preferably, the size and number of the first chip and the second chip are the same.

Specifically, the bonding of the first wafer and the second wafer to form a double-layer wafer board includes:

Alignment marks are set on the first wafer and the second wafer, and the first wafer and the second wafer are aligned according to the alignment marks and then bonded.

Further, the alignment mark includes: a first alignment mark and a second alignment mark;

the first alignment mark is disposed on the first wafer;

the second alignment mark is disposed on the second wafer;

The bonding after aligning the first wafer and the second wafer according to the alignment marks includes:

The first wafer and the second wafer are bonded after aligning the first alignment mark with the corresponding second alignment mark.

Preferably, the cutting of the double-layer wafer plate includes:

The double-layer wafer plate is cut along the preset cutting position of the double-layer wafer plate by using the invisible laser cutting technology.

In a second aspect, an embodiment of the present invention further includes a double-layer wafer board, including: a first wafer and a second wafer;

The first wafer includes a plurality of first chips arranged in a matrix;

the second wafer includes a plurality of second chips arranged in a matrix;

The first chips are electrically connected to the second chips in a one-to-one correspondence to form a display chip module.

Further, the first chip is a Micro-LED driver chip;

The second chip is a Micro-LED chip.

In the method for processing a display chip and the double-layer wafer plate provided by the embodiments of the present invention, a double-layer wafer is formed by bonding a first wafer including a plurality of first chips and a second wafer including a plurality of second chips. A circular plate, so that the first chip is electrically connected to the second chip one by one, and then the double-layer wafer plate is cut to obtain a plurality of display chip modules, which reduces the process complexity of the display chip module processing and realizes the display Efficient processing of chip modules.

Description of drawings

FIG. 1 is a flowchart of a processing method of a display chip in Embodiment 1 of the present invention;

FIG. 2 is a schematic structural diagram of a first wafer in Embodiment 1 of the present invention;

3 is a schematic structural diagram of a second wafer in Embodiment 1 of the present invention;

4 is a schematic structural diagram of a display chip module in Embodiment 1 of the present invention;

5 is a flowchart of a processing method of a display chip in Embodiment 2 of the present invention;

6 is a schematic structural diagram of a first wafer in Embodiment 2 of the present invention;

7 is a schematic structural diagram of a first wafer in a single square area according to Embodiment 2 of the present invention;

8 is a schematic structural diagram of a second wafer in Embodiment 2 of the present invention;

9(a)-(c) are schematic structural diagrams of the second wafer in a single square area in Embodiment 2 of the present invention;

10 is a schematic structural diagram of an independent display chip module in Embodiment 2 of the present invention;

11 is a schematic structural diagram of a double-layer wafer plate in Embodiment 3 of the present invention;

12 is a schematic structural diagram of a first wafer in Embodiment 3 of the present invention;

FIG. 13 is a schematic structural diagram of a second wafer in Embodiment 3 of the present invention.

Detailed ways

The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention, but not to limit the present invention. In addition, it should be noted that, for the convenience of description, the drawings only show some but not all structures related to the present invention.

It should also be noted that, unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the present invention. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. And in order to avoid obscuring the present invention due to unnecessary details, only structures and/or processing steps closely related to the solution according to the present invention are shown in the drawings, and other details that are not related to the present invention are omitted. .

Furthermore, the terms "first," "second," etc. may be used herein to describe various directions, acts, steps or elements, etc., but are not limited by these terms. These terms are only used to distinguish a first direction, act, step or element from another direction, act, step or element. For example, a first alignment mark could be referred to as a second alignment mark, and, similarly, a second alignment mark could be referred to as a first alignment mark, without departing from the scope of the present invention. Both the first alignment mark and the second alignment mark are alignment marks, but they are not the same alignment mark. The terms "first", "second" and the like should not be understood as indicating or implying relative importance or implying the number of technical features indicated. Thus, a feature defined as "first" or "second" may expressly or implicitly include one or more of that feature. In the description of the present invention, "plurality" means at least two, such as two, three, etc., unless otherwise expressly and specifically defined.

Example 1

FIG. 1 is a flowchart of a processing method of a display chip provided in Embodiment 1 of the present invention, and this embodiment can be applied to a processing process of a Micro-LED display chip. The processing method of the display chip provided by the embodiment of the present invention includes:

S100, providing a first wafer.

Specifically, FIG. 2 is a schematic structural diagram of a first wafer. As shown in FIG. 2 , the first wafer 10 includes a plurality of first chips 11 arranged in a matrix.

Preferably, the first chip 11 includes, but is not limited to, conventional LED driver chips, small-pitch LED driver chips, miniLED driver chips, and Micro-LED driver chips.

Preferably, the providing the first wafer 10 includes: forming the silicon wafer into a first wafer 10 including a plurality of first chips 11 arranged in a matrix.

S110, providing a second wafer.

Specifically, FIG. 3 is a schematic structural diagram of the second wafer. As shown in FIG. 3 , the second wafer 20 includes a plurality of second chips 21 arranged in a matrix.

Preferably, the second chip 21 includes, but is not limited to, conventional LED chips, small-pitch LED chips, mini LED chips, and Micro-LED chips.

Preferably, the providing the second wafer 20 includes: forming a gallium nitride epitaxial wafer into a second wafer 20 including a plurality of second chips 21 arranged in a matrix.

Preferably, in order to electrically connect the first chips 11 to the second chips 21 in one-to-one correspondence, the sizes and numbers of the first chips 11 and the second chips 21 are the same.

S120, bonding the first wafer and the second wafer.

Specifically, bonding the first wafer 10 and the second wafer 20 includes: electrically connecting the first chip 11 and the second chip 21 in a one-to-one correspondence to form a double-layer wafer board.

S130, cutting the double-layer wafer plate.

Figure 4 is a schematic diagram of the structure of the display chip module. The double-layer wafer plate can be cut by grinding wheel cutting technology, diamond knife cutting technology or laser cutting technology to obtain multiple display chip modules, wherein each The display chip module includes a first chip 11 and a second chip 21 that are electrically connected.

In the method for processing a display chip provided by the embodiment of the present invention, a first wafer including a plurality of first chips and a second wafer including a plurality of second chips are bonded to form a double-layer wafer board, so that the first wafer The chips are electrically connected to the second chips one by one, and then the double-layer wafer plate is cut to obtain a plurality of independent display chip modules, which reduces the process complexity of the display chip module processing and realizes the display chip module. Efficient processing.

Embodiment 2

FIG. 5 is a flowchart of the processing method of the display chip provided by the second embodiment of the present invention. The processing method of the display chip provided by the second embodiment of the present invention mainly includes the following steps:

S200, providing a first wafer.

Specifically, FIG. 6 is a schematic structural diagram of a first wafer according to Embodiment 2 of the present invention. As shown in FIG. 6 , the first wafer 30 includes a plurality of first chips 31 arranged in a matrix. The first chip 31 is a Micro-LED driver chip.

Specifically, the providing the first wafer 30 includes: forming the silicon wafer into the first wafer 30 including a plurality of first chips 31 arranged in a matrix.

In an optional embodiment, as shown in FIG. 7 is a schematic structural diagram of the first wafer 30 in a single square area, the step of making the silicon wafer into the first wafer 30 includes: on the silicon wafer 300 The square regions arranged in a matrix are doped according to preset functions to form the circuit element structure layer 310 ; the first electrode 320 and the second electrode 330 are formed on the circuit element structure layer 310 . The materials of the first electrode 320 and the second electrode 330 may be the same or different, including one of Ti (titanium), Al (aluminum), Au (gold), Cr (chromium), Pt (platinum), and Ni (nickel). one or more compositions for bonding with the second wafer. The gap between the first electrode 320 and the second electrode 330 is filled with insulating material to form the first insulating layer 340 . In this embodiment, the preset function may be a Micro-LED switch driving function or a Micro-LED blinking driving function or the like.

S210, providing a second wafer.

Specifically, FIG. 8 is a schematic structural diagram of the second wafer 40 according to the second embodiment of the present invention. As shown in FIG. 8 , the second wafer 40 includes a plurality of second chips 41 arranged in a matrix. The second chip 41 is a Micro-LED chip.

Specifically, the providing the second wafer 40 includes: forming a gallium nitride epitaxial wafer into a second wafer 40 including a plurality of second chips 41 arranged in a matrix.

In an optional embodiment, the forming of the gallium nitride epitaxial wafer into a second wafer 40 including a plurality of second chips 41 arranged in a matrix includes:

In step a, as shown in FIG. 9( a ), the gallium nitride epitaxial wafer includes a sapphire substrate 400 , a GaN (gallium nitride)-based buffer layer 410 , and an N-type semiconductor layer 420 stacked in sequence. The material of the N-type semiconductor layer 420 is n-type GaN. The gallium nitride epitaxial wafer is divided into a plurality of square regions arranged in a matrix, and a multiple quantum well light-emitting layer 430, a P-type semiconductor layer 440 and a current spreading layer 450 are sequentially formed on the gallium nitride epitaxial wafer in each region. The material of the multiple quantum well light-emitting layer 430 is InGaN (indium gallium nitride) and/or GaN; the material of the p-type semiconductor layer 440 is p-type GaN; the material of the current spreading layer 450 includes ITO (indium tin oxide), IZO (Indium Zinc Oxide) etc.

In step b, as shown in FIG. 9(b), the structure obtained in step a is etched to expose the N-type semiconductor layer 420 and form a connection through the current spreading layer 450, the P-type semiconductor layer 440 and the multiple quantum well light-emitting layer 430. hole.

Step c, as shown in FIG. 9(c), on the basis of the structure obtained in step b, the third electrode 460 is deposited in the through hole, the fourth electrode 470 is deposited on the current spreading layer 450, and the third electrode 460 and An insulating material is filled between the fourth electrodes 470 to form an insulating layer 480 . The materials of the third electrode 460 and the fourth electrode 470 may be the same or different, including one or more of Ti, Al, Au, Cr, Pt, and Ni.

Thus, the gallium nitride epitaxial wafer is formed into a second wafer including a plurality of Micro-LED chips arranged in a matrix. The Micro-LED chip includes: a multiple quantum well light-emitting layer 430 , a P-type semiconductor layer 440 , a current spreading layer 450 , a third electrode 460 and a fourth electrode 470 .

Further, in order to electrically connect the first chips to the second chips one by one, the size and number of the square regions divided by the silicon wafer are the same as the size and number of the gallium nitride epitaxial wafers, so that the first The size and number of the chips 31 and the second chips 41 are the same.

S220, bonding the first wafer and the second wafer.

Specifically, bonding the first wafer 30 and the second wafer 40 includes:

S221 , setting alignment marks on the first wafer and the second wafer, and aligning the first wafer and the second wafer according to the alignment marks and then bonding.

The alignment marks include first alignment marks 32 and second alignment marks 42 , the first alignment marks 32 are arranged on the first wafer 30 , and the second alignment marks 42 are arranged on the corresponding second wafer 40 . The number of the first alignment marks 32 and the second alignment marks 42 is at least two. When bonding the first wafer 30 and the second wafer 40 , it is only necessary to align the first alignment marks 32 of the first wafer 30 with the corresponding second alignment marks 42 of the second wafer 40 . , the first electrode 320 of the first wafer 30 is bonded to the third electrode 460 of the second wafer 40 , and the second electrode 330 of the first wafer 30 is bonded 470 to the fourth electrode of the second wafer 40 , a double-layer wafer plate can be obtained.

S230, cutting the double-layer wafer plate.

Specifically, cutting the double-layer wafer plate includes:

S231 , cutting the double-layer wafer plate along the preset cutting position of the double-layer wafer plate by using the invisible laser cutting technology.

In the embodiment of the present invention, the invisible laser cutting technology is used to divide the double-layer wafer plate, which can reduce the scratches and damages on the surface of the double-layer wafer plate caused by cutting. As shown in Figure 10, first, the double-layer wafer plate is filmed and placed in a cutting machine, the parameters of the cutting machine are set to cut the double-layer wafer plate, and then the cut double-layer wafer plate is split to A plurality of independent display chip modules 50 are formed, and then the split double-layer wafer plate is expanded to completely separate the plurality of independent display chip modules 50 . As a variant, the method of cutting the double-layer wafer plate in step S231 is not limited, and can use invisible laser cutting technology, grinding wheel cutting technology, diamond knife cutting technology or other cutting technology.

In the method for processing a display chip provided by the embodiment of the present invention, a double-layer wafer board is formed by bonding a first wafer including a plurality of first chips and a second wafer including a plurality of second chips according to alignment marks , so that the first chip is more accurately connected to the second chip one by one, and then the double-layer wafer board is cut by invisible laser cutting technology to obtain multiple independent display chip modules, which reduces the double-layer wafer board. Scratches and damages in the cutting process reduce the process complexity of the display chip module processing, and realize the efficient processing of the display chip module.

Embodiment 3

The third embodiment of the present invention provides a double-layer wafer board. FIG. 11 is a schematic structural diagram of the double-layer wafer board in the third embodiment of the present invention, including: a first wafer 60 and a second wafer 70 .

Specifically, as shown in FIG. 12 , the first wafer 60 includes a plurality of first chips 61 arranged in a matrix. The first chip 61 is a Micro-LED driver chip.

Specifically, as shown in FIG. 13 , the second wafer 70 includes a plurality of second chips 71 arranged in a matrix. The second chip is a Micro-LED chip.

Preferably, the size and quantity of the first chip 61 and the second chip 71 are the same, so that the first chips 61 are electrically connected to the second chips 71 in a one-to-one correspondence to form a display chip module.

Further, an alignment mark is also included. The alignment mark includes a first alignment mark 62 and a second alignment mark 72. The first alignment mark 62 is provided on the first wafer 60, and the second alignment mark 72 is provided on the At the position corresponding to the second wafer 70 , the number of the first alignment marks 62 and the second alignment marks 72 is at least two. During the bonding process of the first wafer 60 and the second wafer 70, the first alignment marks 62 and the second alignment marks 72 are aligned to align the first wafer 60 and the second wafer 70, thereby realizing The bonding of the first wafer 60 and the second wafer 70 is performed to realize the accurate one-to-one electrical connection of the first chips 61 to the second chips 71 . Thus, a double-layer wafer sheet can be obtained.

Further, the double-layer wafer plate can also be cut, for example, the double-layer wafer plate can be cut along the preset cutting position of the double-layer wafer plate by using invisible laser technology, so as to obtain a plurality of independent display chip molds. Group.

The double-layer wafer board provided by the embodiment of the present invention includes a bonded first wafer and a second wafer, wherein the first chips on the first wafer are electrically connected to the second chips on the second wafer in a one-to-one correspondence. For chips, the double-layer wafer board can be cut by invisible laser cutting technology to obtain multiple independent display chip modules, which reduces the scratches and damages during the cutting process of the double-layer wafer board, and reduces the display chip modules. The process complexity of processing realizes the efficient processing of display chip modules.

Note that the above are only preferred embodiments of the present invention and applied technical principles. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and can also include more other equivalent embodiments without departing from the concept of the present invention. The scope is determined by the scope of the appended claims.

Claims (10)

1. A processing method of a display chip is characterized by comprising the following steps:

providing a first wafer, wherein the first wafer comprises a plurality of first chips which are arranged in a matrix manner;

providing a second wafer, wherein the second wafer comprises a plurality of second chips which are arranged in a matrix manner;

bonding the first wafer and the second wafer to form a double-layer wafer plate, wherein the first chips of the double-layer wafer are electrically connected with the second chips in a one-to-one correspondence manner;

and cutting the double-layer wafer plate to obtain a plurality of display chip modules, wherein each display chip module comprises a first chip and a second chip which are electrically connected.

2. The method of claim 1, wherein the providing the first wafer comprises: a silicon wafer is fabricated into a first wafer including a plurality of first chips arranged in a matrix.

3. The method of claim 1, wherein the providing the second wafer comprises: and manufacturing the gallium nitride epitaxial wafer into a second wafer comprising a plurality of second chips arranged in a matrix.

4. The method of claim 1,

the first chip is a Micro-LED driving chip;

the second chip is a Micro-LED chip.

5. The method of claim 1, wherein the first chip and the second chip are the same size and number.

6. The method of claim 1, wherein bonding the first wafer to a second wafer comprises:

and arranging alignment marks on the first wafer and the second wafer, and aligning and bonding the first wafer and the second wafer according to the alignment marks.

7. The method of claim 6,

the alignment mark comprises: a first alignment mark and a second alignment mark;

the first alignment mark is arranged on the first wafer;

the second alignment mark is arranged on the second wafer;

the aligning and bonding the first wafer and the second wafer according to the alignment mark comprises:

and bonding the first wafer and the second wafer after aligning the first alignment mark and the corresponding second alignment mark.

8. The method of claim 1, wherein said cutting said bilayer wafer plate comprises:

and cutting the double-layer crystal circular plate along the preset cutting position of the double-layer crystal circular plate by adopting an invisible laser cutting technology.

9. A dual layer wafer plate, comprising: a first wafer and a second wafer;

the first wafer comprises a plurality of first chips which are arranged in a matrix manner;

the second wafer comprises a plurality of second chips which are arranged in a matrix;

the first chips are electrically connected with the second chips in a one-to-one correspondence manner to form a display chip module.

10. The double-layered wafer sheet of claim 9,

the first chip is a Micro-LED driving chip;

the second chip is a Micro-LED chip.

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