CN110647206A - Band-gap reference voltage source for improving fluctuation upper limit of power supply voltage - Google Patents
Band-gap reference voltage source for improving fluctuation upper limit of power supply voltage Download PDFInfo
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- CN110647206A CN110647206A CN201810674999.6A CN201810674999A CN110647206A CN 110647206 A CN110647206 A CN 110647206A CN 201810674999 A CN201810674999 A CN 201810674999A CN 110647206 A CN110647206 A CN 110647206A
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- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is DC
- G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
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Abstract
The invention discloses a band-gap reference voltage source for improving the fluctuation upper limit of power supply voltage, which comprises MOS (metal oxide semiconductor) transistors M1-14, triodes Q1-Q5 and resistors R1-R2. The invention adopts the three-stage cascode current mirror technology, improves the supply mode of grid bias, furthest increases the power supply voltage range supported by the band-gap reference circuit, greatly prolongs the service life of the circuit, enlarges the service environment of the circuit, and can be flexibly integrated into various integrated circuit chips.
Description
Technical Field
The invention belongs to the technical field of integrated circuit design, and particularly relates to a band-gap reference voltage source for improving the fluctuation upper limit of power supply voltage.
Background
The band-gap reference circuit is widely applied to analog circuits, digital circuits and digital-analog hybrid circuits, and the power supply voltage range enabling the band-gap reference voltage source to work normally plays a crucial role in the performance and the service life of the whole system.
A typical bandgap reference Voltage consists of a PTAT Voltage (Proportional to Absolute Temperature Voltage) and a CTAT Voltage (Complementary to Absolute Temperature Voltage), as shown in fig. 1. The CTAT voltage can be obtained by a BJT transistor, and the PTAT voltage can be achieved by biasing the difference between the two VBEs of the BJT transistor at different current densities. BJT tube Δ VBE relationship is as follows:
ΔV_BE＝V_BE1-V_BE2＝V_T ln(I_C2/I_C1) (1)
dividing Δ VBE by resistor R yields a PTAT current source:
I_PTAT＝(ΔV_BE)/R＝KT/qR ln(I_C2/I_C1) (2)
and the relationship between VBE and absolute temperature T of a BJT tube can be expressed by equation (3):
V_BE＝V_G(T_r)+T/T_r×[V_BE(T_r)-V_G(T_r)]-(n-1)kT/q ln(T/T_r) (3)
v _ G (T _ r) is a band gap reference voltage of the semiconductor material at a reference temperature; q is the charge of one electron; n is a process constant; k is the boltzmann constant; t is the absolute temperature; i _ C is the collector current; v _ BE (T _ r) is the base and emitter differential pressure at the reference temperature. The last higher order term in equation (3) is small and negligible, which results in the desired CTAT voltage. Therefore, the output voltage of the reference can be expressed by equation (4):
V_BER＝V_BE+KΔV_BE (4)
since the CTAT voltage VBE has a negative temperature coefficient and the PTAT voltage Δ VBE has a positive temperature coefficient, K can make the temperature coefficient of V _ BER zero as long as it is chosen properly.
For a range of supply voltages that can function properly, a classical first order voltage mode bandgap reference circuit is typically employed. As shown in fig. 2, M1, M2, M4 and M5 form a primary cascode current mirror to control the currents of Q1 and Q2 to be equal, so as to generate a positive temperature current, so that the lower limit and the upper limit of the power voltage range can be calculated respectively:
lower limit of VDD: and under VDD, VTH + Vddsat + VBE, wherein VTH is the threshold voltage of the MOS transistor, and Vddsat is the overdrive voltage of the MOS transistor.
Lower limit of VDD: it is known that when the power supply voltage increases by x, the overdrive voltages of M2 and M4 also increase by x, and the currents of M2 and M4 also increase slightly, and it is generally considered in the art that no change can be considered when the error of the current change is within 2%. Therefore, it can be assumed that the maximum overdrive voltage increment causing this current error is Vmax, and the power supply voltage at this time is the upper limit, and VDD is VTH + Vdsat + Vmax + VBE.
The range of supply voltages for this classical first-order bandgap reference of fig. 2 can thus be obtained as:
VTH+Vdsat+VBE<VDD<VTH+Vdsat+Vmax+VBE
it can be seen that the upper limit of the power supply voltage fluctuation range is limited and cannot be greatly changed by adopting a simple primary cascode current mirror structure, so that the whole fluctuation range is limited.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art. Therefore, the invention mainly aims to provide a pulse modulation circuit with a high-frequency limiting function, and aims to solve the problem that the upper limit of the fluctuation range of the power supply voltage of the traditional primary cascode current mirror structure is limited and cannot be large, so that the whole fluctuation range of the power supply voltage is limited.
The purpose of the invention is realized by the following technical scheme: a band-gap reference voltage source for improving the fluctuation upper limit of power supply voltage comprises MOS (metal oxide semiconductor) transistors M1-14, triodes Q1-Q5 and resistors R1-R2;
the drain and gate of the transistor are connected together and to GND,
the gate of M1 is connected with the gate of M2, the drain of M1 and the drain of M2 are respectively connected with the drain of M3 and the drain of M4, and the source of M3 and the source of M4 are respectively connected with the drain of M5 and the drain of M6; the gate of M5 is connected with the gate of M6, and the source of M5 and the source of M6 are respectively connected with the drain of M7 and the drain of M8; the grid of the M7 is connected with the grid of the M8; the source of M7 is connected with the source of Q1 through a resistor R1, and the source of M8 is connected with the source of Q2;
the gate of M3 is connected with the gate of M12, the drain of M12 is connected with the drain of M11, the gate of M11 is connected with the gate of M7 and the drain of M6, and the source of M11 is connected with the source of Q4;
the gate of M2 is connected with the gate of M13, the drain of M13 is connected with the drain of M14, the gate of M14 is connected with the gate of M4, the source of M14 is connected with the source of Q5 through R2, and the source of M14 is connected with Vref;
the gate of M1 is connected with the gate of M9, the drain of M9 is connected with the drain of M10, the drain of M10 is connected with the source of M9, the gate of M10 and the gate of M5, respectively, and the source of M10 is connected with the source of Q3;
m9, M1, M2 and M13 are connected and then connected with Vdd.
Furthermore, M1-M4 are PMOS tubes, and M5-M8 are NMOS tubes.
Furthermore, the band-gap reference voltage source for increasing the fluctuation upper limit of the power supply voltage supports the power supply voltage in the range of 2.5-5.5V.
Further, M12 and M10 provide voltage bias for the gates of M3, M4 and M5, M6, respectively.
Compared with the prior art, the invention has at least the following advantages:
the invention adopts the three-stage cascode current mirror technology, improves the supply mode of grid bias, furthest increases the power supply voltage range supported by the band-gap reference circuit, greatly prolongs the service life of the circuit, enlarges the service environment of the circuit, and can be flexibly integrated into various integrated circuit chips.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
Fig. 1 is a schematic circuit diagram of the bandgap reference principle.
Fig. 2 is a schematic diagram of a classic first-order voltage mode bandgap reference circuit.
Fig. 3 is a schematic circuit diagram of a bandgap reference voltage source for increasing the upper limit of power supply voltage fluctuation according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
Descriptions in this specification as relating to "first", "second", etc. are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicit to any indicated technical feature or quantity. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature.
In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the present invention, unless otherwise expressly stated or limited, the terms "connected," "secured," and the like are to be construed broadly, and for example, "secured" may be a fixed connection, a removable connection, or an integral part; can be mechanically or electrically connected; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In addition, the technical solutions in the embodiments of the present invention may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination of technical solutions should not be considered to exist, and is not within the protection scope of the present invention.
Example 1
As shown in FIG. 3, a bandgap reference voltage source for increasing the upper limit of power supply voltage fluctuation comprises MOS transistors M1-14, transistors Q1-Q5, and resistors R1-R2;
the drain and gate of the transistor are connected together and to GND,
the gate of M1 is connected with the gate of M2, the drain of M1 and the drain of M2 are respectively connected with the drain of M3 and the drain of M4, and the source of M3 and the source of M4 are respectively connected with the drain of M5 and the drain of M6; the gate of M5 is connected with the gate of M6, and the source of M5 and the source of M6 are respectively connected with the drain of M7 and the drain of M8; the grid of the M7 is connected with the grid of the M8; the source of M7 is connected with the source of Q1 through a resistor R1, and the source of M8 is connected with the source of Q2;
the gate of M3 is connected with the gate of M12, the drain of M12 is connected with the drain of M11, the gate of M11 is connected with the gate of M7 and the drain of M6, and the source of M11 is connected with the source of Q4;
the gate of M2 is connected with the gate of M13, the drain of M13 is connected with the drain of M14, the gate of M14 is connected with the gate of M4, the source of M14 is connected with the source of Q5 through R2, and the source of M14 is connected with Vref;
the gate of M1 is connected with the gate of M9, the drain of M9 is connected with the drain of M10, the drain of M10 is connected with the source of M9, the gate of M10 and the gate of M5, respectively, and the source of M10 is connected with the source of Q3;
m9, M1, M2 and M13 are connected and then connected with Vdd.
Wherein, M1-M4 are PMOS tubes, and M5-M8 are NMOS tubes.
M12 and M10 provide voltage bias to the gates of M3, M4 and M5, M6, respectively.
The band-gap reference voltage source for increasing the fluctuation upper limit of the power supply voltage supports the power supply voltage in the range of 2.5-5.5V.
The fluctuation upper limit of the power supply voltage of the circuit structure of the embodiment is calculated, and the derivation of the power supply voltage range of the classic first-order bandgap reference already knows that the overdrive voltage increment Vmax causing the maximum current error needs to be calculated to obtain the upper limit of the power supply voltage range of the circuit. As can be seen from fig. 3, when the power supply voltage increases by x, the overdrive voltage of M7 and M5 and the corresponding increase by x, and similarly, the overdrive voltage of the other branch M2 and M4 also increases by x. Similarly, if the maximum overdrive voltage increment causing the 2% current error is Vmax, then the increment of the power supply voltage at this time is the sum of the overdrive voltage increments of the two MOS transistors, which is 2Vmax, so that the upper limit of the power supply voltage fluctuation range of the circuit of the embodiment can be obtained:
on VDD ═ VTH +2Vdsat +2Vmax + VBE;
the lower limit of the power supply voltage fluctuation of the circuit structure of the present embodiment is calculated in this way, because a special bias structure is used, the threshold voltage VTH of one MOS transistor is reduced by the lower limit of VTH +2Vdsat + VBE under VDD of a 3-stage cascode structure without using a special bias compared with the threshold voltage VTH of 2VTH +2Vdsat + VBE under VDD of a 3-stage cascode structure without using a special bias, and for the MOS process, an overdrive voltage Vdsat is much smaller than a threshold voltage VTH, so the lower limit of the power supply voltage fluctuation range of the present embodiment is increased by only one Vdsat compared with a classical circuit, and the increment of the upper limit of the increment ratio is basically negligible.
According to experiments, it can be found that for a MOS process, a Vmax is about 2V, and a Vdsat is only about 200mV, so that the upper limit of the embodiment is raised more remarkably compared with the increment of the lower limit of the power supply voltage fluctuation range. Therefore, we can conclude that the fluctuation range of the power supply voltage for normal operation of the present embodiment is greatly improved compared with the conventional structure.
The embodiment adopts a three-stage cascode current mirror technology, improves the providing mode of gate bias, furthest increases the power supply voltage range supported by the band-gap reference circuit, greatly prolongs the service life of the circuit, enlarges the service environment of the circuit, and can be flexibly integrated into various integrated circuit chips.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are also included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (4)
1. A band-gap reference voltage source for improving the fluctuation upper limit of power supply voltage is characterized by comprising MOS transistors M1-14, triodes Q1-Q5 and resistors R1-R2;
the drain and gate of the transistor are connected together and to GND,
the gate of M1 is connected with the gate of M2, the drain of M1 and the drain of M2 are respectively connected with the drain of M3 and the drain of M4, and the source of M3 and the source of M4 are respectively connected with the drain of M5 and the drain of M6; the gate of M5 is connected with the gate of M6, and the source of M5 and the source of M6 are respectively connected with the drain of M7 and the drain of M8; the grid of the M7 is connected with the grid of the M8; the source of M7 is connected with the source of Q1 through a resistor R1, and the source of M8 is connected with the source of Q2;
the gate of M3 is connected with the gate of M12, the drain of M12 is connected with the drain of M11, the gate of M11 is connected with the gate of M7 and the drain of M6, and the source of M11 is connected with the source of Q4;
the gate of M2 is connected with the gate of M13, the drain of M13 is connected with the drain of M14, the gate of M14 is connected with the gate of M4, the source of M14 is connected with the source of Q5 through R2, and the source of M14 is connected with Vref;
the gate of M1 is connected with the gate of M9, the drain of M9 is connected with the drain of M10, the drain of M10 is connected with the source of M9, the gate of M10 and the gate of M5, respectively, and the source of M10 is connected with the source of Q3;
m9, M1, M2 and M13 are connected and then connected with Vdd.
2. The bandgap reference voltage source for increasing the upper limit of power supply voltage fluctuation as claimed in claim 1, wherein M1-M4 is PMOS transistor, and M5-M8 is NMOS transistor.
3. The bandgap reference voltage source for increasing the upper limit of power supply voltage fluctuation according to claim 1, wherein the bandgap reference voltage source for increasing the upper limit of power supply voltage fluctuation supports a power supply voltage in a range of 2.5V to 5.5V.
4. The bandgap reference voltage source for increasing the upper limit of power supply voltage fluctuation according to claim 1, wherein M12 and M10 provide voltage bias for the gates of M3, M4, M5 and M6, respectively.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113114117A (en) * | 2021-04-08 | 2021-07-13 | 唐太平 | Biasing circuit for common-gate tube of cascode radio-frequency low-noise amplifier |
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