CN110635795B - High power supply voltage selection circuit suitable for medium and high voltage work and implementation method thereof - Google Patents
High power supply voltage selection circuit suitable for medium and high voltage work and implementation method thereof Download PDFInfo
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Abstract
The invention discloses a high power supply voltage selection circuit suitable for medium-high voltage work, which mainly solves the problem that the existing maximum voltage selection circuit is not suitable for high-voltage power supply selection. The circuit comprises low-voltage 5V NMOS devices MN 0-MN 6,5V PMOS devices MP0 and MP1, asymmetric high-voltage PMOS devices MP1H and MP2H, asymmetric high-voltage NMOS devices MNH1 and MNH2, and two matching resistors R1 and R2 with the same size and area. The hysteresis of the comparator controls the resistors R3 MP2H and MP1H and the gate controls the resistors R4 and R5. Zener voltage stabilizing diodes D0-D3. The analog current source Ib may be replaced with a resistor. A buffer A1 having improved driving capability. An inverted output Schmitt trigger I0, and inverters I1 and I2. Through the design, the circuit is suitable for a circuit for selecting a high-voltage power supply, realizes the selection of the high-voltage power supply, and simultaneously meets the characteristics of low cost, low power consumption and the like. Therefore, the method has high use value and popularization value.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a high-power-supply-voltage selection circuit suitable for medium-high voltage work and an implementation method thereof.
Background
The maximum voltage selection circuit is mainly used for selecting one maximum voltage from a plurality of existing voltages to output for other circuits in the integrated circuit.
Fig. 1 shows a power selection circuit in a conventional low-voltage 5V conventional application, where V1 and V2 have maximum operating voltages of 5V, mp1 and MP2 are both PMOS transistors of 5V, A1 is a comparator with hysteresis, and of course, the comparator A1 is implemented by a 5V device, and the function of the circuit is to make VOUT equal to the higher voltage of V1 and V2, so as to implement the function of selecting a high power voltage.
The limitation of the conventional power selection circuit shown in fig. 1 is that it is only suitable for the conventional 5V. For more and more medium-high voltage application scenes at present, the circuit needs to be changed and innovated; if all the devices in fig. 1 are replaced by symmetrical high-voltage devices (symmetry HVMOS), the layout area must be greatly increased, which is not favorable for the trend of low power consumption and low cost, and the precision of the symmetrical HVMOS is much worse than that of 5V devices, and is generally not used for analog operation; however, in the mainstream process at present, an asymmetric high voltage device (asymmetric HVMOS) is basically applied, and a VGS junction of the asymmetric HVMOS cannot withstand high voltage and is still at the traditional voltage withstanding level of 5V, so that the application limitation of the traditional circuit is obvious.
Disclosure of Invention
The invention aims to provide a high-power supply voltage selection circuit suitable for medium-high voltage work and an implementation method thereof, and mainly solves the problem that the existing maximum voltage selection circuit is not suitable for high-voltage power supply selection.
In order to realize the purpose, the technical scheme adopted by the invention is as follows:
a high power supply voltage selection circuit suitable for medium and high voltage work comprises a resistor R1 connected with a medium and high voltage power supply voltage input end V1, an NMOS tube MN0 with a grid electrode and a drain electrode both connected with the other end of the resistor R1, NMOS tubes MN1 and MN2 with a grid electrode connected with the grid electrode of the NMOS tube MN0, a Zener voltage stabilizing diode D3 with a negative electrode connected with the source electrodes of the NMOS tubes MN0, MN1 and MN2, NMOS tubes MN3 and MN4 with a grid electrode connected with the positive electrode of the Zener voltage stabilizing diode D3, an NMOS tube MN5 with a drain electrode connected with the source electrode of the NMOS tube MN4, a trigger I0 with an input end connected with the drain electrode of the NMOS tube MN4 and an output end connected with the grid electrode of the NMOS tube MN5, inverters I1 and I2 with an input end connected with the output end of the trigger I0 after series connection, an NMOS tube MNH1 and an NMOS tube MNH1 with a grid electrode connected with the output end of the inverter I1, an NMOS tube MNH2 and a buffer A with a negative electrode connected with the Zener diode D0, a PMOS tube MP0, MP1 whose source is connected to the output terminal of the buffer A1, a resistor R2 whose one end is connected to the middle-high voltage supply voltage input terminal V2 and whose other end is connected to the drain of the NMOS tube MN6, a resistor R3 whose one end is connected to the drain of the NMOS tube MN6 and whose other end is connected to both the source of the NMOS tube MN6 and the drain of the NMOS tube MN1, a PMOS tube MP2H whose drain is connected to the middle-high voltage supply voltage input terminal V2, a resistor R4 whose one end is connected to the gate of the PMOS tube MP2H and whose other end is connected to the drain of the NMOS tube MNH2, a Zener diode D2 whose positive stage is connected to the positive stage of the PMOS tube MP2H and whose negative stage is connected to the drain of the NMOS tube MNH2, a PMOS tube MP1H whose drain is connected to the middle-high voltage supply voltage input terminal V1, a resistor R4 whose one end is connected to the gate of the PMOS tube MP1H and whose other end is connected to the drain of the NMOS tube MNH1, a Zener diode D1 whose positive stage is connected to the positive stage of the PMOS tube MP2H and whose negative stage is connected to the drain of the NMOS tube MNH1, and an analog current source Ib with one end connected with the high-voltage selection output end VOUT and the other end connected with the input end of the buffer A1; the source electrodes of the NMOS transistors MN 0-MN 3, MN5, MNH1 and MNH2 are connected, and the source electrode of the PMOS transistor MP1H, MP H is connected with the high-voltage selection output end VOUT.
Further, the current source Ib is replaced by a resistor.
The invention also provides a method for realizing the high power supply voltage selection circuit suitable for medium and high voltage work, which comprises the following steps:
(1) The voltage U1 input from the voltage input end V1 of the medium-high voltage power supply is converted into currents through the resistor R1 and flows into the MN0, the MN1 and the MN2 respectively; the voltage U2 input from the medium-high voltage power supply voltage input end V2 is converted into currents through the resistor R2 and flows into MN1, MN3, MN4 and MN6 respectively;
(2) Pull-up current I of node D with drain of MN1 connected to resistor R3 R2 And a pull-down current I MN1 Forming a comparator output stage;
(3) According to the change of U1, such that I MN1 The voltage of each node in the circuit is changed, and the MOS tube is controlled to be switched on and off, so that higher voltage is selected to be output.
Specifically, in step (3):
(A1) When U1 is increased, so that I MN1 Increasing, pulling the node D low, turning off the MN3 and the MN4, increasing the current of the MP1 to enhance the effect of pulling up the node E of the NMOS tube connected with the Schmitt trigger, and finally pulling up the node E to be high;
(A2) When the node E is pulled up to high, the node C of the output end of the phase inverter I2 connected with the grid electrode of the NMOS tube MNH2 becomes low, and the node G of the output end of the phase inverter I1 connected with the grid electrode of the NMOS tube MNH1 becomes high;
(A3) A node H connected with the drain electrode of the NMOS tube MNH2 through the resistor R4 floats upwards to turn off the grid electrode of the NMOS tube MNH2, and a node H connected with the drain electrode of the NMOS tube MNH1 through the resistor R5 is pulled down to turn on the grid electrode of the NMOS tube MNH 1;
(A4) The higher voltage U1 selected by VOUT is output.
Specifically, in step (3):
(B1) When U1 is reduced to below U2, make I MN1 Is reduced to be lower than I R2 The node D is pulled up and raised; node E, node G are pulled up to high;
(B2) Node E and node G become low, and node C becomes high;
(B3) MP1H is turned off, MP2H is turned on;
(A4) The higher voltage U2 selected by VOUT is output.
Further, in step (1), the current flowing into MN0, MN1 and MN2 is:
I MN0 ＝I MN1 ＝I MN2 ＝I R1 ＝U1/R1 (1)。
specifically, when U1 is higher than U2, the current flowing into MN1, MN3, MN4, MN6 has the following magnitude:
I MN1’ ＝I MN3 ＝I MN4 ＝I MN6 ＝I R2 ＝U2/R2 (2)；
when U1 is gradually decreased to below U2, the current flowing into MN1, MN3, MN4, MN6 is:
I MN1’ ＝I MN3 ＝I MN4 ＝I MN6 ＝I R2 ＝U2/(R2+R3) (3)。
specifically, in the case where U2 is constant:
the increase in the inversion point voltage of V1 is:
U1 RISE ＝U2*R1/R2 (4)；
the voltage at the turning point when V1 decreases is:
U1 FALL ＝U2*R1/(R2+R3) (5)。
compared with the prior art, the invention has the following beneficial effects:
(1) The invention converts the high voltage V1 and V2 into current, compares the current with a current comparator formed by low voltage 5V devices, the analog operation comparison process is completely realized by a high-precision 5V CMOS, and the asymmetric high voltage device does not participate in the analog operation process, thereby greatly improving the precision of the circuit. The 5V comparison operation part circuit is driven by a 5V analog source generated by the circuit, and an external additional bias is not required to be increased. The circuit is more suitable for the circuit of high-voltage power supply selection, the selection of the high-voltage power supply is realized, and the characteristics of low cost, low power consumption and the like are met.
(2) The invention has simple structure and easy realization, thereby having high application value and being suitable for popularization and application.
Drawings
Fig. 1 is a schematic diagram of a low-voltage power selection circuit in the prior art.
Fig. 2 is a schematic circuit diagram of the present invention.
FIG. 3 is a waveform diagram illustrating the operation of the present invention when U1 is higher than U2.
Detailed Description
The present invention will be further described with reference to the following description and examples, which include but are not limited to the following examples.
Examples
As shown in FIG. 2, the high power supply voltage selection circuit suitable for medium and high voltage operation disclosed by the present invention comprises a resistor R1 connected with a medium and high voltage power supply voltage input end V1, an NMOS tube MN0 with a grid and a drain both connected with the other end of the resistor R1, NMOS tubes MN1 and MN2 with a grid connected with the grid of the NMOS tube MN0, a Zener diode D3 with a cathode connected with the sources of the NMOS tubes MN0, MN1 and MN2, NMOS tubes MN3 and MN4 with a grid connected with the anode of the Zener diode D3, an NMOS tube MN5 with a drain connected with the source of the NMOS tube MN4, a trigger I0 with an input connected with the drain of the NMOS tube MN4 and an output connected with the grid of the NMOS tube MN5, inverters I1 and I2 with an input connected with the output of the trigger I0 after series connection, an NMOS tube MNH1 with a grid connected with the output of the inverter I1, NMOS tube MNH2 and a zener diode D0 with a cathode connected with the source of the NMOS tube MNH1, a buffer A1 having an input terminal connected to a negative electrode of a Zener diode D0, PMOS tubes MP0 and MP1 having a source terminal connected to an output terminal of the buffer A1, a resistor R2 having one end connected to a middle-high voltage power supply voltage input terminal V2 and the other end connected to a drain terminal of an NMOS tube MN6, a resistor R3 having one end connected to a drain terminal of the NMOS tube MN6 and the other end connected to both the source terminal of the NMOS tube MN6 and the drain terminal of the NMOS tube MN1, a PMOS tube MP2H having a drain terminal connected to the middle-high voltage power supply voltage input terminal V2, a resistor R4 having one end connected to a gate terminal of the PMOS tube MP2H and the other end connected to a drain terminal of the NMOS tube MNH2, a Zener diode D2 having a positive terminal connected to a positive terminal of the PMOS tube MP2H and a negative terminal connected to a drain terminal of the NMOS tube MNH2, a PMOS tube MP1H having a drain terminal connected to the drain terminal of the PMOS tube MP1H and the other terminal connected to a drain terminal of the NMOS tube MNH1, a Zener voltage stabilizing diode D1 with the positive stage connected with the original pole of the PMOS tube MP2H and the negative connected with the drain electrode of the NMOS tube MNH1, and an analog current source Ib with one end connected with the high-voltage selection output end VOUT and the other end connected with the input end of the buffer A1; the source electrodes of the NMOS transistors MN 0-MN 3, MN5, MNH1 and MNH2 are connected, and the source electrode of the PMOS transistor MP1H, MP H is connected with the high-voltage selection output end VOUT.
Wherein, MN 0-MN 6 are low-voltage 5V NMOS devices, MP0, MP1 are 5V PMOS devices, MP1H and MP2H are asymmetric high-voltage PMOS devices (asymmetric high-voltage MOS characteristics: the gate and the source can only bear 5V voltage, the drain and the source can bear high voltage, the area is small, and the on-resistance is low), MNH1 and MNH2 are asymmetric high-voltage NMOS devices, and R1 and R2 are two matching resistors with the same area. R3 is the hysteresis control resistor of the comparator, and R4 and R5 are the gate control resistors of MP2H and MP1H, respectively. Ib is an analog current source that can be replaced by a resistor. A1 is a buffer that improves the driving capability. I0 is a Schmitt trigger with inverted output, and I1 and I2 are inverters.
The invention also provides a method for realizing the high power supply voltage selection circuit suitable for medium and high voltage work, which comprises the following steps:
(1) The voltage U1 input from the medium-high voltage power supply voltage input end V1 is converted into current through a resistor R1 and flows into MN0, MN1 and MN2 respectively; the voltage U2 input from the medium-high voltage power supply voltage input terminal V2 is converted into currents through the resistor R2 to flow into MN1, MN3, MN4, and MN6, respectively.
(2) Pull-up current I of node D with drain of MN1 connected to resistor R3 R2 And a pull-down current I MN1 Forming a comparator output stage.
(3) According to the change of U1, such that I MN1 The current of each node in the circuit is changed, and the MOS tube is controlled to be opened and closedAnd thus a higher voltage output.
When U1 is increased, so that I MN1 And when the current of the MP1 is increased, the effect of enhancing the node E of the pull-up NMOS tube connected with the Schmitt trigger is enhanced, and finally the node E is pulled up to be high.
The node E is pulled up to high, the node C of the output end of the inverter I2 connected with the grid electrode of the NMOS tube MNH2 becomes low, and the node G of the output end of the inverter I1 connected with the grid electrode of the NMOS tube MNH1 becomes high.
A node H connected with the drain electrode of the NMOS tube MNH2 through the resistor R4 floats upwards to turn off the grid electrode of the NMOS tube MNH2, and a node H connected with the drain electrode of the NMOS tube MNH1 through the resistor R5 is pulled down to turn on the grid electrode of the NMOS tube MNH 1; d1 is clamped to ensure that the gate and source voltages of MP1H are within a safe range.
The higher voltage U1 selected by VOUT is output. In a state where V1 is higher than V2, MN6 is short-circuited, and R2 and R3 become series-connected. The working waveform diagram is shown in fig. 3.
Similarly, when U1 is gradually decreased to be lower than U2, I is enabled MN1 Is reduced to be lower than I R2 The node D is pulled up and raised; node E, node G are pulled up to high, node E, node G go low, node C goes high, MP1H is turned off, MP2H is turned on, and VOUT selects the higher voltage U2 to output. The same principle. The gate of MP2H is protected by D2 clamp during pull-down.
In step (1), the current flowing into MN0, MN1 and MN2 is:
I MN0 ＝I MN1 ＝I MN2 ＝I R1 ＝U1/R1 (1)。
specifically, when U1 is higher than U2, the current flowing into MN1, MN3, MN4, MN6 has the following magnitude:
I MN1’ ＝I MN3 ＝I MN4 ＝I MN6 ＝I R2 ＝U2/R2 (2)；
when U1 is gradually decreased to below U2, the current flowing into MN1, MN3, MN4, MN6 is:
I MN1’ ＝I MN3 ＝I MN4 ＝I MN6 ＝I R2 ＝U2/(R2+R3) (3)。
specifically, in the case where U2 is constant:
v1 raises the inversion point voltage by:
U1 RISE ＝U2*R1/R2 (4)；
the voltage at the turning point when V1 decreases is:
U1 FALL ＝U2*R1/(R2+R3) (5)。
the invention converts the high voltage V1 and V2 into current, compares the current with a current comparator formed by low voltage 5V devices, the analog operation comparison process is completely realized by a high-precision 5V CMOS, and the asymmetric high voltage device does not participate in the analog operation process, thereby greatly improving the precision of the circuit. The 5V comparison operation part circuit is driven by a 5V analog source generated by the circuit, and an external additional bias is not required to be increased. The circuit is more suitable for the circuit for selecting the high-voltage power supply, the selection of the high-voltage power supply is realized, and the characteristics of low cost, low power consumption and the like are met. Therefore, the method has high use value and popularization value.
The above-mentioned embodiment is only one of the preferred embodiments of the present invention, and should not be used to limit the scope of the present invention, but all the insubstantial modifications or changes made within the spirit and scope of the main design of the present invention, which still solve the technical problems consistent with the present invention, should be included in the scope of the present invention.
Claims (8)
1. A high power supply voltage selection circuit suitable for medium and high voltage work is characterized by comprising a resistor R1 connected with a medium and high voltage power supply voltage input end V1, an NMOS tube MN0 with a grid electrode and a drain electrode both connected with the other end of the resistor R1, NMOS tubes MN1 and MN2 with a grid electrode connected with the grid electrode of the NMOS tube MN0, a Zener voltage stabilizing diode D3 with a cathode electrode connected with the source electrodes of the NMOS tubes MN0, MN1 and MN2, NMOS tubes MN3 and MN4 with a grid electrode connected with the anode of the Zener voltage stabilizing diode D3, an NMOS tube MN5 with a drain electrode connected with the source electrode of the NMOS tube MN4, a trigger I0 with an input end connected with the drain electrode of the NMOS tube MN4 and an output end connected with the grid electrode of the NMOS tube MN5, inverters I1 and I2 with an input end connected with the output end of the trigger I0 after series connection, an NMOS tube MNH1 with a grid electrode connected with the output end of the inverter I1, NMOS tube MNH2 and a Zener voltage stabilizing diode D0 with a cathode electrode connected with the source electrode of the NMOS tube MNH1, a buffer A1 having an input terminal connected to a negative electrode of a Zener diode D0, PMOS tubes MP0 and MP1 having a source terminal connected to an output terminal of the buffer A1, a resistor R2 having one end connected to a middle-high voltage power supply voltage input terminal V2 and the other end connected to a drain terminal of an NMOS tube MN6, a resistor R3 having one end connected to a drain terminal of the NMOS tube MN6 and the other end connected to both the source terminal of the NMOS tube MN6 and the drain terminal of the NMOS tube MN1, a PMOS tube MP2H having a drain terminal connected to the middle-high voltage power supply voltage input terminal V2, a resistor R4 having one end connected to a gate terminal of the PMOS tube MP2H and the other end connected to a drain terminal of the NMOS tube MNH2, a Zener diode D2 having a positive terminal connected to a positive terminal of the PMOS tube MP2H and a negative terminal connected to a drain terminal of the NMOS tube MNH2, a PMOS tube MP1H having a drain terminal connected to the drain terminal of the PMOS tube MP1H and the other terminal connected to a drain terminal of the NMOS tube MNH1, a Zener voltage stabilizing diode D1 with the positive stage connected with the original pole of the PMOS tube MP2H and the negative connected with the drain electrode of the NMOS tube MNH1, and an analog current source Ib with one end connected with the high-voltage selection output end VOUT and the other end connected with the input end of the buffer A1; the source electrodes of the NMOS transistors MN 0-MN 3, MN5, MNH1 and MNH2 are connected, and the source electrode of the PMOS transistor MP1H, MP H is connected with the high-voltage selection output end VOUT.
2. A high supply voltage selection circuit adapted for medium and high voltage operation according to claim 1, characterized in that said current source Ib is replaced by a resistor.
3. A method of implementing a high supply voltage selection circuit adapted for medium-high voltage operation according to any one of claims 1 or 2, comprising the steps of:
(1) The voltage U1 input from the medium-high voltage power supply voltage input end V1 is converted into current through a resistor R1 and flows into MN0, MN1 and MN2 respectively; the voltage U2 input from the medium-high voltage power supply voltage input end V2 is converted into currents through the resistor R2 and flows into MN1, MN3, MN4 and MN6 respectively;
(2) Of MN1Pull-up current I of node D with drain connected to resistor R3 R2 And a pull-down current I MN1 Forming a comparator output stage;
(3) According to the change of U1, such that I MN1 The voltage of each node in the circuit is changed, and the MOS tube is controlled to be switched on and off, so that higher voltage is selected to be output.
4. A method for implementing a high supply voltage selection circuit suitable for medium-high voltage operation as claimed in claim 3, wherein in step (3):
(A1) When U1 is increased, so that I MN1 Increasing, pulling the node D low, turning off the MN3 and the MN4, increasing the current of the MP1 to enhance the effect of pulling up the node E of the NMOS tube connected with the Schmitt trigger, and finally pulling up the node E to be high;
(A2) When the node E is pulled up to high, the node C of the output end of the phase inverter I2 connected with the grid electrode of the NMOS tube MNH2 becomes low, and the node G of the output end of the phase inverter I1 connected with the grid electrode of the NMOS tube MNH1 becomes high;
(A3) A node H connected with the drain electrode of the NMOS tube MNH2 through the resistor R4 floats upwards to turn off the grid electrode of the NMOS tube MNH2, and a node H connected with the drain electrode of the NMOS tube MNH1 through the resistor R5 is pulled down to turn on the grid electrode of the NMOS tube MNH 1;
(A4) The higher voltage U1 output selected by VOUT.
5. A method for implementing a high supply voltage selection circuit suitable for medium and high voltage operation according to claim 3, wherein in step (3):
(B1) When U1 is reduced to below U2, make I MN1 Is reduced to be lower than I R2 The node D is pulled up and raised; node E, node G are pulled up to high;
(B2) Node E and node G become low, and node C becomes high;
(B3) MP1H is turned off, MP2H is turned on;
(A4) The higher voltage U2 selected by VOUT.
6. The method according to claim 3, wherein in step (1), the currents flowing into MN0, MN1 and MN2 are as follows:
I MN0 ＝I MN1 ＝I MN2 ＝I R1 ＝U1/R1(1)。
7. the method for implementing a high power supply voltage selection circuit suitable for medium and high voltage operation as claimed in claim 3, wherein when U1 is higher than U2, the current flowing into MN1, MN3, MN4, MN6 is:
I MN1’ ＝I MN3 ＝I MN4 ＝I MN6 ＝I R2 ＝U2/R2(2)；
when U1 is gradually decreased to below U2, the current flowing into MN1, MN3, MN4, MN6 is:
I MN1’ ＝I MN3 ＝I MN4 ＝I MN6 ＝I R2 ＝U2/(R2+R3) (3)。
8. a method for implementing a high supply voltage selection circuit suitable for medium-high voltage operation as claimed in claim 3, wherein, under a certain U2 condition:
the increase in the inversion point voltage of V1 is:
U1 RISE ＝U2*R1/R2(4)；
the voltage at the turning point when V1 decreases is:
U1 FALL ＝U2*R1/(R2+R3) (5)。
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| WO1999038259A1 (en) * | 1998-01-23 | 1999-07-29 | Maxim Integrated Products, Inc. | Reverse current throttling of a mos transistor |
| JP2004289885A (en) * | 2003-03-19 | 2004-10-14 | Matsushita Electric Ind Co Ltd | Overshoot reduction circuit |
| CN207704303U (en) * | 2018-01-11 | 2018-08-07 | 厦门安斯通微电子技术有限公司 | A kind of regulator circuit for substituting Zener |
| CN109756220A (en) * | 2019-03-07 | 2019-05-14 | 上海长园维安电子线路保护有限公司 | A substrate potential selection circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1999038259A1 (en) * | 1998-01-23 | 1999-07-29 | Maxim Integrated Products, Inc. | Reverse current throttling of a mos transistor |
| JP2004289885A (en) * | 2003-03-19 | 2004-10-14 | Matsushita Electric Ind Co Ltd | Overshoot reduction circuit |
| CN207704303U (en) * | 2018-01-11 | 2018-08-07 | 厦门安斯通微电子技术有限公司 | A kind of regulator circuit for substituting Zener |
| CN109756220A (en) * | 2019-03-07 | 2019-05-14 | 上海长园维安电子线路保护有限公司 | A substrate potential selection circuit |
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