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CN110610991A - Epitaxial structures and low on-voltage transistors - Google Patents

Epitaxial structures and low on-voltage transistors Download PDF

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Publication number
CN110610991A
CN110610991A CN201910921313.3A CN201910921313A CN110610991A CN 110610991 A CN110610991 A CN 110610991A CN 201910921313 A CN201910921313 A CN 201910921313A CN 110610991 A CN110610991 A CN 110610991A
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base electrode
electrode layer
layer
epitaxial structure
emitter
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林科闯
颜志泓
魏鸿基
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Integrated Circuit Co Ltd Is Pacified By Xiamen City Three
Xiamen Sanan Integrated Circuit Co Ltd
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Integrated Circuit Co Ltd Is Pacified By Xiamen City Three
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82Heterojunctions
    • H10D62/824Heterojunctions comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00Bipolar junction transistors [BJT]
    • H10D10/80Heterojunction BJTs
    • H10D10/821Vertical heterojunction BJTs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/177Base regions of bipolar transistors, e.g. BJTs or IGBTs

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  • Electrodes Of Semiconductors (AREA)

Abstract

本申请提供了一种外延结构和低导通电压晶体管,涉及半导体和通信技术领域。低导通电压晶体管包括外延结构。外延结构包括复合基电极层和发射极层。复合基电极层包括第一基电极层和基于所述第一基电极层制作的第二基电极层;其中,所述第一基电极层的材料包括GaAs,所述第二基电极层的材料包括InxGa1‑xAs。复合基电极层能够降低基电极层的能隙,使基电极层与发射极层之间的导电带尖峰效应降低,运用在晶体管中,能够降低导通电压,降低功耗;在第二基电极层上采用Pt形成欧姆接触层更加容易,可以减薄Pt的厚度,使Pt驱入复合基电极层的量减少,从而使器件产生界面复合电流的情况减少,使器件的信赖性测试更加稳定、可靠。

The present application provides an epitaxial structure and a low on-voltage transistor, and relates to the technical fields of semiconductors and communications. The low on-voltage transistor includes an epitaxial structure. The epitaxial structure includes a composite base electrode layer and an emitter layer. The composite base electrode layer includes a first base electrode layer and a second base electrode layer made based on the first base electrode layer; wherein, the material of the first base electrode layer includes GaAs, and the material of the second base electrode layer Including In x Ga 1‑x As. The composite base electrode layer can reduce the energy gap of the base electrode layer, so that the peak effect of the conduction band between the base electrode layer and the emitter layer can be reduced. When used in transistors, it can reduce the on-voltage and power consumption; in the second base electrode It is easier to use Pt on the layer to form an ohmic contact layer, and the thickness of Pt can be reduced, so that the amount of Pt driven into the composite base electrode layer is reduced, so that the interface recombination current of the device is reduced, and the reliability test of the device is more stable. reliable.

Description

外延结构和低导通电压晶体管Epitaxial structures and low on-voltage transistors

技术领域technical field

本申请涉及半导体和通信技术领域,具体而言,涉及一种外延结构和低导通电压晶体管。The present application relates to the field of semiconductor and communication technologies, and in particular, to an epitaxial structure and a low on-voltage transistor.

背景技术Background technique

在目前运用于3G或4G的功率放大器中,附加功率效率(power added efficiency,简称:“PAE”)是非常重要的一个参数。PAE定义为输出功率Pout与输入功率Pin之差与直流输入功率Pdc的比,即:(Pout-Pin)/Pdc。PAE是表示PA的效率质量的指针,该值越大就越能够抑制功率放大器的功率耗损。而直流功耗的改善首推将导通电压(Von)、膝型电压(kneevoltage,简称:“Vk”)与补偿电压(offset voltage,简称:“Voff”)降低。但是,现有的功率放大器中运用的晶体管导通电压过大,并且难以降低,导致器件的功耗较大。In power amplifiers currently used in 3G or 4G, additional power efficiency (power added efficiency, "PAE" for short) is a very important parameter. PAE is defined as the ratio of the difference between the output power Pout and the input power Pin to the DC input power Pdc, namely: (Pout-Pin)/Pdc. PAE is a pointer indicating the efficiency quality of the PA, and the larger the value is, the more the power consumption of the power amplifier can be suppressed. In order to improve the DC power consumption, the on-voltage (Von), the knee voltage (“Vk” for short) and the offset voltage (“Voff” for short) are reduced. However, the on-voltage of the transistor used in the existing power amplifier is too large, and it is difficult to reduce it, resulting in a large power consumption of the device.

因此,设计一种晶体管,能够适用于低导通电压,降低功耗,这是目前亟待解决的技术问题。Therefore, designing a transistor that can be applied to a low turn-on voltage and reduce power consumption is a technical problem that needs to be solved urgently at present.

发明内容SUMMARY OF THE INVENTION

有鉴于此,本申请的目的在于,提供一种外延结构和低导通电压晶体管以改善上述问题。In view of this, the purpose of the present application is to provide an epitaxial structure and a low on-voltage transistor to improve the above problems.

本申请实施例提供一种外延结构,包括:The embodiment of the present application provides an epitaxial structure, including:

复合基电极层,包括第一基电极层和基于所述第一基电极层制作的第二基电极层;a composite base electrode layer, comprising a first base electrode layer and a second base electrode layer fabricated based on the first base electrode layer;

基于所述第二基电极层制作的发射极层;An emitter layer made based on the second base electrode layer;

其中,所述第一基电极层的材料包括GaAs,所述第二基电极层的材料包括InxGa1- xAs。Wherein, the material of the first base electrode layer includes GaAs, and the material of the second base electrode layer includes InxGa1 - xAs .

在上述实施例的所述外延结构的所述InxGa1-xAs中,x的取值保持不变。In the In x Ga 1-x As of the epitaxial structure of the above embodiment, the value of x remains unchanged.

在上述实施例的所述外延结构中,x=0.25。In the epitaxial structure of the above embodiment, x=0.25.

在上述实施例的所述外延结构的所述第二基电极层中,In的组分为25%。In the second base electrode layer of the epitaxial structure of the above embodiment, the composition of In is 25%.

在上述实施例的所述外延结构的所述InxGa1-xAs中,在靠近所述发射极层的方向上,x的取值逐渐增大。In the In x Ga 1-x As of the epitaxial structure of the above embodiment, the value of x increases gradually in the direction close to the emitter layer.

在上述实施例的所述外延结构中,x的取值从0.05逐渐增至0.25。In the epitaxial structure of the above embodiment, the value of x is gradually increased from 0.05 to 0.25.

在上述实施例的所述外延结构的所述第二基电极层中,In的组分范围为5%~25%。In the second base electrode layer of the epitaxial structure of the above embodiment, the composition of In ranges from 5% to 25%.

在上述实施例的所述外延结构中,所述第二基电极层的厚度为5nm或者小于临界厚度。In the epitaxial structure of the above embodiment, the thickness of the second base electrode layer is 5 nm or less than the critical thickness.

在上述实施例的所述外延结构中,所述发射极层的材料包括InGaP。In the epitaxial structure of the above embodiment, the material of the emitter layer includes InGaP.

本申请实施例还提供一种低导通电压晶体管,包括所述的外延结构。Embodiments of the present application further provide a low on-voltage transistor including the epitaxial structure.

本申请实施例提供的外延结构和低导通电压晶体管的有益效果:The beneficial effects of the epitaxial structure and the low on-voltage transistor provided by the embodiments of the present application:

1.在第一基电极层与发射极层之间加入第二基电极层,第二基电极层的材料包括InxGa1-xAs,InxGa1-xAs具有低能隙的优点,能够降低基电极层的能隙,是基电极层与发射极层之间的导电带尖峰效应降低,运用在晶体管中,能够降低导通电压,降低功耗;1. A second base electrode layer is added between the first base electrode layer and the emitter layer, the material of the second base electrode layer includes InxGa1 - xAs , InxGa1 - xAs has the advantage of low energy gap, It can reduce the energy gap of the base electrode layer and reduce the peak effect of the conduction band between the base electrode layer and the emitter layer. When used in transistors, it can reduce the on-voltage and power consumption;

2.因为InxGa1-xAs具有低能隙的优点,在第二基电极层上采用Pt形成欧姆接触层更加容易,可以减薄Pt的厚度,使Pt驱入复合基电极层的量减少,从而使器件产生界面复合电流的情况减少,使器件的信赖性测试更加稳定、可靠。2. Because In x Ga 1-x As has the advantage of low energy gap, it is easier to use Pt to form an ohmic contact layer on the second base electrode layer, which can reduce the thickness of Pt and reduce the amount of Pt driven into the composite base electrode layer. , so that the interface recombination current is reduced in the device, and the reliability test of the device is more stable and reliable.

为使本申请的上述目的、特征和优点能更明显易懂,下文特举较佳实施例,并配合所附附图,作详细说明如下。In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, the preferred embodiments are exemplified below, and are described in detail as follows in conjunction with the accompanying drawings.

附图说明Description of drawings

为了更清楚地说明本申请实施例的技术方案,下面将对实施例中所需要使用的附图作简单地介绍,应当理解,以下附图仅示出了本申请的某些实施例,因此不应被看作是对范围的限定,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他相关的附图。In order to illustrate the technical solutions of the embodiments of the present application more clearly, the following drawings will briefly introduce the drawings that need to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore do not It should be regarded as a limitation of the scope, and for those of ordinary skill in the art, other related drawings can also be obtained according to these drawings without any creative effort.

图1为本申请第一实施例提供的外延结构的示意图。FIG. 1 is a schematic diagram of an epitaxial structure provided by a first embodiment of the present application.

图2为图1中的外延结构的制备方法的流程图。FIG. 2 is a flow chart of a method for fabricating the epitaxial structure in FIG. 1 .

图3为本申请第三实施例提供的低导通电压晶体管的示意图。FIG. 3 is a schematic diagram of a low on-voltage transistor provided by a third embodiment of the present application.

图标:100-外延结构;1-复合基电极层;11-第一基电极层;12-第二基电极层;2-发射极层;3-衬底;4-次集电极层;5-集电极层;6-帽盖层;7-发射极金属接触层;8-基电极金属接触层;9-集电极金属接触层。Icon: 100-epitaxial structure; 1-composite base electrode layer; 11-first base electrode layer; 12-second base electrode layer; 2-emitter layer; 3-substrate; 4-secondary collector layer; 5- Collector layer; 6-cap layer; 7-emitter metal contact layer; 8-base electrode metal contact layer; 9-collector metal contact layer.

具体实施方式Detailed ways

为使本申请实施例的目的、技术方案和优点更加清楚,下面将结合本申请实施例中的附图,对本申请实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例只是本申请的一部分实施例,而不是全部的实施例。通常在此处附图中描述和示出的本申请实施例的组件可以以各种不同的配置来布置和设计。In order to make the purposes, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments It is only a part of the embodiments of the present application, but not all of the embodiments. The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations.

因此,以下对在附图中提供的本申请的实施例的详细描述并非旨在限制要求保护的本申请的范围,而是仅仅表示本申请的选定实施例。基于本申请中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本申请保护的范围。Thus, the following detailed description of the embodiments of the application provided in the accompanying drawings is not intended to limit the scope of the application as claimed, but is merely representative of selected embodiments of the application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

在砷化镓基单异质结晶体管器件中,基电极层的材料为砷化镓(GaAs),发射极层的材料为磷化铟镓(InGaP),GaAs与InGaP在导电带中具有较大的能隙差(ΔEc),使基电极层与发射极层之间的导电带尖峰(conduction band spiking)效应明显,而有较大顺向导通电压。而在同质材料下的基电极层与集电极层之间的能隙差为ΔEc=0,因此,基射极导通电压(Vbe,on)会较基集电极之间更大,使的器件补偿电压(Voff)偏大。In the GaAs-based single heterojunction transistor device, the material of the base electrode layer is gallium arsenide (GaAs), and the material of the emitter layer is indium gallium phosphide (InGaP). The energy gap difference (ΔEc) between the base electrode layer and the emitter layer is obvious, and the conduction band spiking effect between the base electrode layer and the emitter layer is obvious, and there is a larger forward conduction voltage. The energy gap difference between the base electrode layer and the collector layer under the homogeneous material is ΔEc=0, so the base-emitter turn-on voltage (Vbe,on) will be larger than that between the base-collector electrodes, making the The device offset voltage (Voff) is too large.

而铂金属(Pt metal)为基电极上的金属欧姆接触层(Base Ohmic contact)形成的重要材料。铂金属在热退火程序(thermal annealing)形成欧姆接触过程中,因为铂金属与砷化镓基电极层反应,易使基电极电流(base current)产生较高的界面复合电流(interface recombination current),影响器件的信赖性测试结果。And platinum metal (Pt metal) is an important material formed by the metal ohmic contact layer (Base Ohmic contact) on the base electrode. During the thermal annealing process of platinum metal to form ohmic contact, because platinum metal reacts with the GaAs-based electrode layer, it is easy to make the base current (base current) generate a higher interface recombination current (interface recombination current), Affects the reliability test results of the device.

本申请的实施例则提供一种外延结构和低导通电压晶体管,不仅能够降低器件的补偿电压,还能够使器件的信赖性测试结果更为可靠。The embodiments of the present application provide an epitaxial structure and a low on-voltage transistor, which can not only reduce the compensation voltage of the device, but also make the reliability test result of the device more reliable.

第一实施例first embodiment

请参阅图1,本实施例提供一种外延结构100,包括复合基电极层1和基于复合基电极层1制作的发射极层2。Referring to FIG. 1 , this embodiment provides an epitaxial structure 100 including a composite-based electrode layer 1 and an emitter layer 2 fabricated based on the composite-based electrode layer 1 .

其中,复合基电极层1为双层材料结构,包括第一基电极层11和基于第一基电极层11制作的第二基电极层12。第一基电极层11的材料包括GaAs,第二基电极层12的材料包括InxGa1-xAs。InxGa1-xAs相较于GaAs是能隙较低的材料,运用在晶体管中,能够改善导电带尖峰(conduction band spiking)效应影响,降低晶体管的导通电压,降低功耗。The composite base electrode layer 1 is a double-layer material structure, including a first base electrode layer 11 and a second base electrode layer 12 made based on the first base electrode layer 11 . The material of the first base electrode layer 11 includes GaAs, and the material of the second base electrode layer 12 includes InxGa1 - xAs . Compared with GaAs, In x Ga 1-x As is a material with a lower energy gap. When used in transistors, it can improve the influence of the conduction band spiking effect, reduce the on-voltage of the transistor, and reduce power consumption.

在第二基电极层12中,在靠近发射极层2的方向上,In含量相等,也就是说,图1中第二基电极层12从下至上In含量分布均匀、保持相等,InxGa1-xAs中,x的取值保持不变。In the second base electrode layer 12, in the direction close to the emitter layer 2, the In content is equal, that is to say, the second base electrode layer 12 in FIG. In 1-x As, the value of x remains unchanged.

InxGa1-xAs中,x的取值有多种选择,可以选择的范围为0.2~0.3,本实施例中,x的取值选择0.25。也就是说,第二基电极层12中,In的组分范围可以是20%~30%中的任一固定值,本实施例中,选择In的组分为25%。In In x Ga 1-x As, there are various options for the value of x, and the selectable range is 0.2 to 0.3. In this embodiment, the value of x is selected as 0.25. That is to say, in the second base electrode layer 12, the composition range of In can be any fixed value from 20% to 30%. In this embodiment, the composition of In is selected to be 25%.

发射极层2为单层材料结构。发射极层2的材料包括GaInP。发射极层2中In含量为适配于砷化镓基电极层的固定组分。The emitter layer 2 is a single-layer material structure. The material of the emitter layer 2 includes GaInP. The In content in the emitter layer 2 is a fixed composition suitable for the GaAs-based electrode layer.

请参阅图2,本实施例还提供上述外延结构100的制备方法,包括以下步骤:Referring to FIG. 2, the present embodiment also provides a method for fabricating the above-mentioned epitaxial structure 100, including the following steps:

S1:制作第一基电极层11S1: Fabrication of the first base electrode layer 11

第一基电极层11的材料采用GaAs。在第一基电极层11的形成过程中,依材料成长需求以合适莫耳分率(mole ratio)成长该层。The material of the first base electrode layer 11 is GaAs. During the formation of the first base electrode layer 11 , the layer is grown at a suitable mole ratio according to material growth requirements.

S2:制作第二基电极层12S2: Making the second base electrode layer 12

第二基电极层12的材料采用InxGa1-xAs。在第二基电极层12的形成过程中,x的取值选择0.25,从而按比例调制In的莫耳分率、Ga的莫耳分率,逐渐堆积形成适配的高质量第二基电极层12。The material of the second base electrode layer 12 is InxGa1 - xAs . In the process of forming the second base electrode layer 12, the value of x is selected to be 0.25, so that the molar ratio of In and the molar ratio of Ga are adjusted proportionally, and the second base electrode layer of suitable high quality is gradually formed by accumulation. 12.

第二基电极层12的厚度可以设计为5nm或者小于该组分下(x=0.25)的临界厚度。临界厚度是指外延层晶格不失配的情况下,单晶材料最大可成长的薄膜厚度。依理论计算,在InxGa1-xAs中,x=0.25时,第二基电极层12的临界厚度约为40A,但在现今外延技术进步下,其临界厚度可成长至75A。The thickness of the second base electrode layer 12 may be designed to be 5 nm or less than the critical thickness under this composition (x=0.25). The critical thickness refers to the maximum film thickness that a single crystal material can grow without the lattice mismatch of the epitaxial layer. According to theoretical calculation, in InxGa1 - xAs , when x=0.25, the critical thickness of the second base electrode layer 12 is about 40A, but with the current advancement of epitaxy technology, the critical thickness can be grown to 75A.

S3:制作发射极层2S3: Making Emitter Layer 2

发射极层2设计为单层材料结构,发射极层2的材料采用InGaP,在发射极层2的形成过程中,依材料成长需求以合适莫耳分率成长该层,在第二基电极层12上逐渐堆积形成发射极层2。The emitter layer 2 is designed as a single-layer material structure, and the material of the emitter layer 2 is InGaP. During the formation process of the emitter layer 2, the layer is grown at a suitable molar rate according to the material growth requirements. In the second base electrode layer The emitter layer 2 is formed by gradually accumulating on the 12 .

本实施例提供的外延结构100及其制备方法的有益效果:The beneficial effects of the epitaxial structure 100 and the preparation method thereof provided by this embodiment:

1.在第一基电极层11与发射极层2之间加入第二基电极层12,第二基电极层12的材料包括InxGa1-xAs,InxGa1-xAs具有低能隙的优点,能够改善第二基电极层12与发射极层2之间的导电带尖峰效应,运用在晶体管中,能够降低导通电压,降低功耗;1. A second base electrode layer 12 is added between the first base electrode layer 11 and the emitter layer 2. The material of the second base electrode layer 12 includes InxGa1 - xAs , and InxGa1 - xAs has a low energy The advantage of the gap can improve the conduction band peak effect between the second base electrode layer 12 and the emitter layer 2, and when used in a transistor, it can reduce the on-voltage and power consumption;

2.因为InxGa1-xAs具有低能隙的优点,在第二基电极层12上采用Pt形成欧姆接触层更加容易,可以减薄Pt的厚度,使Pt驱入复合基电极层1的量减少,从而使器件产生界面复合电流的情况减少,使器件的信赖性测试更加稳定、可靠;2. Because In x Ga 1-x As has the advantage of a low energy gap, it is easier to use Pt to form an ohmic contact layer on the second base electrode layer 12 , and the thickness of Pt can be reduced so that Pt is driven into the composite base electrode layer 1 . reduce the amount of interfacial recombination current generated by the device, and make the reliability test of the device more stable and reliable;

3.制备方法上只需对应调整原料的供料莫耳分率即可,制备方法便捷,成本较低。3. The preparation method only needs to correspondingly adjust the molar fraction of the raw material, the preparation method is convenient and the cost is low.

第二实施例Second Embodiment

本实施例提供一种外延结构100,其与第一实施例提供的外延结构100的区别在于,第二基电极层12中In的组分不同。This embodiment provides an epitaxial structure 100 , which is different from the epitaxial structure 100 provided by the first embodiment in that the composition of In in the second base electrode layer 12 is different.

外延结构100包括复合基电极层1和发射极层2。复合基电极层1为双层材料结构,包括第一基电极层11和基于第一基电极层11制作的第二基电极层12。其中,第一基电极层11和发射极层2与第一实施例中的相同,这里不再赘述。The epitaxial structure 100 includes a composite base electrode layer 1 and an emitter layer 2 . The composite base electrode layer 1 is a double-layer material structure, including a first base electrode layer 11 and a second base electrode layer 12 made based on the first base electrode layer 11 . The first base electrode layer 11 and the emitter layer 2 are the same as those in the first embodiment, and will not be repeated here.

第二基电极层12中的InxGa1-xAs,在靠近发射极层2的方向上,x的取值逐渐增大。也就是说,图1中的第二基电极层12,In含量随着厚度的增加逐渐递增,递增的速度可以与厚度保持线性关系,也可以按照性能需要灵活设计大小关系,只要使In含量随着高度的增加有增大的趋势,都应该属于本申请要求保护的范围。In the direction of the In x Ga 1-x As in the second base electrode layer 12 , the value of x increases gradually in the direction close to the emitter layer 2 . That is to say, in the second base electrode layer 12 in FIG. 1 , the In content gradually increases as the thickness increases, and the increasing speed can maintain a linear relationship with the thickness, or the size relationship can be flexibly designed according to performance requirements, as long as the In content increases with the thickness. As the height increases, there is an increasing trend, which should belong to the scope of protection claimed in this application.

In含量逐渐增大能够提高电子的载子迁移率,保持阻值在较低的水平,运用在晶体管中,能够保证晶体管的频率特性良好。同时,第二基电极层12与发射极层2之间的导电带尖峰,随着In含量逐渐增大而降低,进一步降低晶体管的导通电压。Gradually increasing the In content can improve the carrier mobility of electrons and keep the resistance value at a low level. When used in transistors, it can ensure good frequency characteristics of the transistors. At the same time, the peak of the conduction band between the second base electrode layer 12 and the emitter layer 2 decreases as the In content gradually increases, which further reduces the turn-on voltage of the transistor.

具体的,第二基电极层12中的InxGa1-xAs,在靠近发射极层2的方向上,x的取值可以选择从0.05逐渐增至0.25。也就是说,第二基电极层12中,In的组分范围为5%~25%。Specifically, in the direction close to the emitter layer 2 of In x Ga 1-x As in the second base electrode layer 12 , the value of x can be selected to gradually increase from 0.05 to 0.25. That is, in the second base electrode layer 12, the composition range of In is 5% to 25%.

在第一基电极层11上制备第二基电极层12的过程中,首先按比例调制In的莫耳分率、Ga的莫耳分率,其中,In的莫耳分率将逐渐增大,Ga的莫耳分率逐渐减小。从而实现在第二基电极层12中从下至上,In含量逐渐增大,Ga含量逐渐减小,As含量保持不变。In the process of preparing the second base electrode layer 12 on the first base electrode layer 11, the molar ratio of In and the molar ratio of Ga are firstly modulated in proportion, wherein the molar ratio of In will gradually increase, The molar fraction of Ga gradually decreases. Therefore, from bottom to top in the second base electrode layer 12 , the In content gradually increases, the Ga content gradually decreases, and the As content remains unchanged.

本实施例提供的外延结构100及其制备方法,除了具有第一实施例中的有益效果之外,还能够提高电子的载子迁移率,保持阻值在较低的水平,运用在晶体管中,能够保证晶体管的频率特性良好。同时,第二基电极层12与发射极层2之间的导电带尖峰,随着In含量逐渐增大而降低,进一步降低晶体管的导通电压。In addition to the beneficial effects of the first embodiment, the epitaxial structure 100 and the preparation method thereof provided in this embodiment can also improve the carrier mobility of electrons, keep the resistance at a low level, and are used in transistors. The frequency characteristic of the transistor can be guaranteed to be good. At the same time, the peak of the conduction band between the second base electrode layer 12 and the emitter layer 2 decreases as the In content gradually increases, which further reduces the turn-on voltage of the transistor.

第三实施例Third Embodiment

本实施例提供一种外延结构100,其在第一实施例或第二实施例提供的外延结构100的基础上,进一步设计成适用于HBT(异质结双极晶体管)的外延结构100。This embodiment provides an epitaxial structure 100 , which is further designed to be an epitaxial structure 100 suitable for HBT (heterojunction bipolar transistor) based on the epitaxial structure 100 provided in the first embodiment or the second embodiment.

请参阅图3,外延结构100包括从下至上依次生长的衬底3、次集电极层4、集电极层5、复合基电极层1、发射极层2和帽盖层6。其中,复合基电极层1和发射极层2采用第一实施例或第二实施例中的结构。Referring to FIG. 3 , the epitaxial structure 100 includes a substrate 3 , a sub-collector layer 4 , a collector layer 5 , a composite base electrode layer 1 , an emitter layer 2 and a cap layer 6 , which are sequentially grown from bottom to top. Among them, the composite base electrode layer 1 and the emitter layer 2 adopt the structures in the first embodiment or the second embodiment.

此外,发射极层2的上方设置有发射极金属接触层7,发射极金属接触层7覆盖于帽盖层6、并与发射极层2欧姆接触,其中,帽盖层6上刻蚀有供发射极金属接触层7穿过的通孔。复合基电极层1上设置有基电极金属接触层8,基电极金属接触层8与复合基电极层1欧姆接触。次集电极层4上设置有集电极金属接触层9,集电极金属接触层9与次集电极层4欧姆接触。In addition, an emitter metal contact layer 7 is arranged above the emitter layer 2 , and the emitter metal contact layer 7 covers the cap layer 6 and is in ohmic contact with the emitter layer 2 , wherein the cap layer 6 is etched with a supply for The through hole through which the emitter metal contact layer 7 passes. The composite base electrode layer 1 is provided with a base electrode metal contact layer 8 , and the base electrode metal contact layer 8 is in ohmic contact with the composite base electrode layer 1 . A collector metal contact layer 9 is provided on the sub-collector layer 4 , and the collector metal contact layer 9 is in ohmic contact with the sub-collector layer 4 .

其中,衬底3、次集电极层4、集电极层5和帽盖层6的材料可以采用GaAs。基电极金属接触层8中从下之上可以依次层叠设置Pt、Ti、Au。在第二基电极层12中,在靠近发射极层2的方向上,In含量相等或逐渐增大,都能够使在第二基电极层12上采用Pt形成欧姆接触层更加容易,可以减薄Pt的厚度,使Pt驱入复合基电极层1的量减少,从而使器件产生界面复合电流的情况减少,使器件的信赖性测试更加稳定、可靠。The materials of the substrate 3 , the sub-collector layer 4 , the collector layer 5 and the cap layer 6 can be GaAs. In the base electrode metal contact layer 8, Pt, Ti, and Au may be stacked in order from bottom to top. In the second base electrode layer 12, in the direction close to the emitter layer 2, the In content is equal or gradually increased, which can make it easier to use Pt to form an ohmic contact layer on the second base electrode layer 12, which can be thinned The thickness of Pt reduces the amount of Pt driven into the composite base electrode layer 1 , thereby reducing the generation of interfacial composite current in the device, and making the reliability test of the device more stable and reliable.

本申请中只详细介绍了将外延结构100运用于HBT的例子,本申请提供的外延结构100当然还可以运用到其它结构形式的晶体管中,在这里不再赘述,只要运用了本申请中提供的复合基电极层1,都应该属于本申请要求保护的范围。In this application, only the example of applying the epitaxial structure 100 to HBT is introduced in detail. Of course, the epitaxial structure 100 provided in this application can also be applied to transistors of other structural forms. The composite base electrode layer 1 should all belong to the scope of protection claimed in this application.

本申请中提供的外延结构100和低导通电压晶体管,还可以运用在功率放大器中,采用了本申请提供的外延结构100和低导通电压晶体管的功率放大器或其它电器,都应该属于本申请要求保护的范围。The epitaxial structure 100 and the low-on-voltage transistor provided in this application can also be used in power amplifiers, and power amplifiers or other electrical appliances using the epitaxial structure 100 and the low-on-voltage transistor provided in this application should belong to this application. Scope of protection claimed.

需要说明的是,本申请中提到的数值,包括组分的取值、厚度的取值等,都只是申请人通过实验和测算获得的较为可靠的数值,而不是严格限定对应的参数只能是这些取值。本领域的技术人员可能会在本申请的方案的基础上,做进一步的实验,获得其他效果相近的取值,这些取值也没有脱离本申请的核心,也应该属于本申请要求保护的范围。It should be noted that the values mentioned in this application, including the values of components and thicknesses, are only relatively reliable values obtained by the applicant through experiments and calculations, rather than strictly limiting the corresponding parameters. are these values. Those skilled in the art may perform further experiments on the basis of the scheme of the present application to obtain other values with similar effects. These values do not depart from the core of the present application, and should also belong to the scope of protection claimed in the present application.

本申请的上述实施例中,复合基电极层1为双层材料结构,根据本申请中的原理,复合基电极层1还可以设计更多数量的层结构,同样能够起到本申请中复合基电极层1的技术效果,所以,在其他实施例中,可以不限定层结构的数量。In the above-mentioned embodiments of the present application, the composite base electrode layer 1 is a double-layer material structure. According to the principle of the present application, the composite base electrode layer 1 can also be designed with a larger number of layer structures, which can also play the role of the composite base electrode in the present application. Therefore, in other embodiments, the number of layer structures may not be limited.

本申请的上述实施例提供的外延结构100和低导通电压晶体管采用低能隙材料,能够降低晶体管的导通电压,降低功耗;同时,第二基电极层12中从下至上In含量逐渐增加,能够提高电子的载子迁移率,保持阻值在较低的水平,保证晶体管的频率特性良好。此外,在制备工艺上只需要对应调整原料的出料速度即可,制备方法简单,成本较低。The epitaxial structure 100 and the low on-voltage transistor provided by the above-mentioned embodiments of the present application use low-energy-gap materials, which can reduce the on-voltage of the transistor and reduce power consumption; at the same time, the In content in the second base electrode layer 12 gradually increases from bottom to top , which can improve the carrier mobility of electrons, keep the resistance at a low level, and ensure good frequency characteristics of the transistor. In addition, in the preparation process, it is only necessary to adjust the discharge speed of the raw materials, the preparation method is simple, and the cost is low.

以上所述仅为本申请的优选实施例而已,并不用于限制本申请,对于本领域的技术人员来说,本申请可以有各种更改和变化。凡在本申请的精神和原则之内,所作的任何修改、等同替换、改进等,均应包含在本申请的保护范围之内。The above descriptions are only preferred embodiments of the present application, and are not intended to limit the present application. For those skilled in the art, the present application may have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this application shall be included within the protection scope of this application.

Claims (10)

1. An epitaxial structure, comprising:
a composite base electrode layer (1) including a first base electrode layer (11) and a second base electrode layer (12) fabricated on the basis of the first base electrode layer (11);
an emitter layer (2) fabricated on the basis of the second base electrode layer (12);
wherein the material of the first base electrode layer (11) comprises GaAs, and the material of the second base electrode layer (12) comprises InxGa1-xAs。
2. The epitaxial structure of claim 1, wherein the InxGa1-xIn As, the value of x remains unchanged.
3. The epitaxial structure of claim 2 wherein x is 0.25.
4. Epitaxial structure according to claim 2, characterized In that the In composition In the second base electrode layer (12) is 25%.
5. The epitaxial structure of claim 1, wherein the InxGa1-xAs, the value of x gradually increases in the direction of approaching the emitter layer (2).
6. Epitaxial structure according to claim 3, characterized in that the value of x increases gradually from 0.05 to 0.25.
7. Epitaxial structure according to claim 2, characterized In that the composition of In the second base electrode layer (12) ranges from 5% to 25%.
8. Epitaxial structure according to claim 1, characterized in that the thickness of the second base electrode layer (12) is 5nm or less than a critical thickness.
9. Epitaxial structure according to claim 1, characterized in that the material of the emitter layer (2) comprises InGaP.
10. A low on-voltage transistor comprising an epitaxial structure according to any of claims 1 to 9.
CN201910921313.3A 2019-09-27 2019-09-27 Epitaxial structures and low on-voltage transistors Pending CN110610991A (en)

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Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10154714A (en) * 1996-11-21 1998-06-09 Sharp Corp Compound semiconductor device and its production
US6188137B1 (en) * 1995-05-25 2001-02-13 Sharp Kabushiki Kaisha Ohmic electrode structure, semiconductor device including such ohmic electrode structure, and method for producing such semiconductor device
TW493224B (en) * 2001-10-22 2002-07-01 Hational Cheng Kung University Composite doped channel heterostructure field-effect transistor
US20040262634A1 (en) * 2003-06-30 2004-12-30 Keiichi Murayama Hetero-junction bipolar transistor and manufacturing method thereof
CN1574388A (en) * 2003-05-28 2005-02-02 株式会社东芝 Semiconductor device
JP2006237045A (en) * 2005-02-22 2006-09-07 Nippon Telegr & Teleph Corp <Ntt> Semiconductor quantum dot structure and manufacturing method thereof
CN1885555A (en) * 2005-06-21 2006-12-27 松下电器产业株式会社 Hetero-junction bipolar transistor and manufacturing method thereof
TW200903800A (en) * 2007-07-09 2009-01-16 Univ Nat Kaohsiung Normal Superlattice-base heterostructure bipolar transistors
CN101533841A (en) * 2008-03-13 2009-09-16 松下电器产业株式会社 Semiconductor device and manufacturing method thereof
US20170200816A1 (en) * 2014-05-26 2017-07-13 Sumitomo Chemical Company, Limited Epitaxial wafer for heterojunction bipolar transistor and heterojunction bipolar transistor
US20190165150A1 (en) * 2017-11-30 2019-05-30 International Business Machines Corporation Lateral bipolar junction transistor with dual base region

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6188137B1 (en) * 1995-05-25 2001-02-13 Sharp Kabushiki Kaisha Ohmic electrode structure, semiconductor device including such ohmic electrode structure, and method for producing such semiconductor device
JPH10154714A (en) * 1996-11-21 1998-06-09 Sharp Corp Compound semiconductor device and its production
TW493224B (en) * 2001-10-22 2002-07-01 Hational Cheng Kung University Composite doped channel heterostructure field-effect transistor
CN1574388A (en) * 2003-05-28 2005-02-02 株式会社东芝 Semiconductor device
US20040262634A1 (en) * 2003-06-30 2004-12-30 Keiichi Murayama Hetero-junction bipolar transistor and manufacturing method thereof
JP2006237045A (en) * 2005-02-22 2006-09-07 Nippon Telegr & Teleph Corp <Ntt> Semiconductor quantum dot structure and manufacturing method thereof
CN1885555A (en) * 2005-06-21 2006-12-27 松下电器产业株式会社 Hetero-junction bipolar transistor and manufacturing method thereof
TW200903800A (en) * 2007-07-09 2009-01-16 Univ Nat Kaohsiung Normal Superlattice-base heterostructure bipolar transistors
CN101533841A (en) * 2008-03-13 2009-09-16 松下电器产业株式会社 Semiconductor device and manufacturing method thereof
US20170200816A1 (en) * 2014-05-26 2017-07-13 Sumitomo Chemical Company, Limited Epitaxial wafer for heterojunction bipolar transistor and heterojunction bipolar transistor
US20190165150A1 (en) * 2017-11-30 2019-05-30 International Business Machines Corporation Lateral bipolar junction transistor with dual base region

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