CN110545091A - a latch circuit - Google Patents

Abstract

This application is applicable to the technical field of latch circuits, and provides a latch circuit, including: a gating control module, a data latch module, and a filtering module; the output end of the gating control module is connected to the an input terminal; the output terminal of the data latch module is connected to the input terminal of the data to be filtered of the filter module, and is connected to the output terminal of the gating control module. The input data is received by the gating control module. When the gating control module is in the off state, the latch circuit is in the latch mode, and the gating control module stops inputting the data to the latch module, and the data latching module stores the received input data Latch, so that when the latch circuit is in the latch mode, the input data can be effectively isolated; by connecting the filter module after the data latch module, the input data can be filtered to effectively filter out the high Pulse glitch.

Description

a latch circuit

technical field

The present application relates to the technical field of latch circuits, in particular to a latch circuit.

Background technique

Latch is to temporarily store the signal to maintain a certain level state. The main function of the latch circuit is to cache, and secondly to complete the asynchronous problem between the high-speed controller and the slow peripheral, then to solve the problem of the driver, and finally to solve the problem that an I/O port can output and input The problem.

The latch circuit can change the state under the action of a specific input pulse level to achieve the purpose of data latching. However, in the existing latch circuit, after the data is locked, the input signal cannot be well isolated, and the input signal may easily affect the latched data.

Contents of the invention

In view of this, the embodiment of the present application provides a latch circuit to solve the problem that the input signal cannot be effectively isolated in the prior art.

The second aspect of the embodiments of the present application provides a latch circuit, including:

Gate control module, data latch module, filter module;

The output terminal of the gate control module is connected to the input terminal of the data latch module; the output terminal of the data latch module is connected to the data input terminal to be filtered of the filter module, and connected to the input terminal of the gate control module output terminal;

The gate control module receives input data, and inputs the input data into the data latch module. When the gate control module is in an off state, the latch circuit is in a latch mode, and the data The latching module latches the input data, and inputs the latched input data as data to be filtered to the filtering module, and the filtering module performs filtering processing on the data to be filtered to obtain output data.

Optionally, the gating control module includes:

a first transistor, a second transistor, a third transistor, and a fourth transistor;

The gate of the first transistor is connected to the gate of the fourth transistor as the first input terminal of the gating control module, the source of the first transistor is connected to a power supply, and the drain of the first transistor The pole is connected to the source of the second transistor;

The gate of the second transistor is the second input terminal of the gating control module, and the drain of the second transistor is connected to the drain of the third transistor;

The gate of the third transistor is the third input terminal of the gating control module, and the source of the third transistor is connected to the drain of the fourth transistor;

The source of the fourth transistor is grounded;

When the second input terminal of the gate control module receives a low level, and the third input terminal of the gate control module receives a high level, the gate control module is in a gate state, and the latch circuit In the gate mode, the gate control module inputs the received input data into the data latch module;

When the second input end of the gating control module receives a high level and the third input end of the gating control module receives a low level, the gating control module is in an off state, and the latch circuit In the latch mode, the gate control module stops inputting the received input data into the data latch module.

Optionally, the data latch module includes:

a first inverter, a second inverter;

The input end of the first inverter is the input end of the data latch module, and is connected to the output end of the gate control module, and the output end of the first inverter is connected to the second inverter the input terminal of the device;

The output end of the second inverter is the output end of the data latch module, and is connected to the input end of the second inverter.

Optionally, the filter module includes:

a first flip-flop, a second flip-flop, a logic gate;

The data input end of the first flip-flop is connected to the data input end of the second flip-flop as the data input end to be filtered of the filtering module, and the clock signal input end of the first flip-flop is the filter circuit The first clock signal input end of the second flip-flop is the second clock signal input end of the filter circuit;

The output end of the first flip-flop is connected to the first input end of the logic gate, and the output end of the second flip-flop is connected to the second input end of the logic gate;

The output terminal of the logic gate is the output terminal of the filtering module.

Optionally, the latch circuit also includes:

a first input module;

The first output end of the first input module is connected to the first input end of the gating control module;

The second output terminal of the first input module is connected to the second input terminal of the gating control module;

When the first input module receives a low-level signal, the first output terminal of the first input module outputs a high-level signal, and the second output terminal of the first input module outputs a low-level signal;

When the first input module receives a high-level signal, the first output terminal of the first input module outputs a low-level signal, and the second output terminal of the first input module outputs a high-level signal.

Optionally, the first input module includes:

The third inverter, the fourth inverter;

The input terminal of the third inverter is the input terminal of the first input module, and the output terminal of the third inverter is the first output terminal of the first input module;

The input terminal of the fourth inverter is connected to the output terminal of the third inverter, and the output terminal of the fourth inverter is the second output terminal of the first input module.

Optionally, the latch circuit also includes:

a second input module;

The first output end of the second input module is connected to the second input end of the filtering module;

The second output terminal of the second input module is connected to the third input terminal of the filter module;

When the second input module receives a low-level signal, the first output terminal of the second input module outputs a high-level signal, and the second output terminal of the second input module outputs a low-level signal;

When the second input module receives a high-level signal, the first output terminal of the second input module outputs a low-level signal, and the second output terminal of the second input module outputs a high-level signal.

Optionally, the second input module includes:

The fifth inverter and the sixth inverter;

The input terminal of the fifth inverter is the input terminal of the second input module, and the output terminal of the fifth inverter is the first output terminal of the second input module;

The input terminal of the sixth inverter is connected to the output terminal of the fifth inverter, and the output terminal of the sixth inverter is the second output terminal of the second input module.

Optionally, the latch circuit also includes:

seventh inverter;

The input terminal of the seventh inverter is connected to the output terminal of the data latch module, and the output terminal of the seventh inverter is connected to the first input terminal of the filter module.

Optionally, the inverter includes:

The fifth transistor, the sixth transistor;

The gate of the fifth transistor and the gate of the sixth transistor are input terminals of the inverter, and the drain of the fifth transistor and the drain of the sixth transistor are outputs of the inverter end;

The source of the fifth transistor is connected to a power supply, and the drain of the fifth transistor is connected to the drain of the sixth transistor;

The source of the sixth transistor is grounded.

Compared with the prior art, the embodiments of the present application have the following beneficial effects:

In the embodiment of the present application, the input data is received by the gating control module. When the gating control module is in the off state, the latch circuit is in the latch mode, and the gating control module stops inputting data to the latch module, and the data latch module will The received input data is latched, so that when the latch circuit is in the latch mode, the input data can be effectively isolated; by connecting the filter module after the data latch module, the input data can be filtered to effectively filter out High pulse glitch in input data.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the accompanying drawings that need to be used in the descriptions of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings in the following description are only for the present application For some embodiments, those of ordinary skill in the art can also obtain other drawings based on these drawings without paying creative efforts.

FIG. 1 is a schematic diagram of a latch circuit provided in an embodiment of the present application;

FIG. 2 is a schematic diagram of a latch circuit provided in another embodiment of the present application;

Fig. 3 is a schematic diagram of a first input module provided by an embodiment of the present application;

Fig. 4 is a schematic diagram of a second input module provided by an embodiment of the present application;

FIG. 5 is a schematic diagram of an inverter provided in an embodiment of the present application;

FIG. 6 is a timing diagram of glitch filtering provided by the embodiment of the present application.

Detailed ways

In the following description, specific details such as specific system structures and technologies are presented for the purpose of illustration rather than limitation, so as to thoroughly understand the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.

It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of described features, integers, steps, operations, elements and/or components, but does not exclude one or more other features. , whole, step, operation, element, component and/or the presence or addition of a collection thereof.

It should also be understood that the terminology used in the specification of this application is for the purpose of describing particular embodiments only and is not intended to limit the application. As used in this specification and the appended claims, the singular forms "a", "an" and "the" are intended to include plural referents unless the context clearly dictates otherwise.

It should also be further understood that the term "and/or" used in the description of the present application and the appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations .

As used in this specification and the appended claims, the term "if" may be construed as "when" or "once" or "in response to determining" or "in response to detecting" depending on the context . Similarly, the phrase "if determined" or "if [the described condition or event] is detected" may be construed, depending on the context, to mean "once determined" or "in response to the determination" or "once detected [the described condition or event] ]” or “in response to detection of [described condition or event]”.

In order to illustrate the technical solutions described in this application, specific examples are used below to illustrate.

FIG. 1 is a schematic diagram of a latch circuit provided in an embodiment of the present application. As shown in the figure, the latch circuit includes:

Strobe control module 100, data latch module 200, filter module 300;

The output end of the gate control module 100 is connected to the input end of the data latch module 200; the output end of the data latch module 200 is connected to the data input end to be filtered of the filtering module 300, and connected to the selected through the output terminal of the control module 100;

The gate control module 100 receives input data, and inputs the input data into the data latch module 200, when the gate control module 100 is in an off state, the latch circuit is in a latch mode, The data latching module 200 latches the input data, and inputs the latched input data as data to be filtered to the filtering module 300, and the filtering module 300 performs filtering processing on the data to be filtered to obtain an output data.

In the embodiment of the present application, the input data is received by the gating control module. When the gating control module is in the off state, the latch circuit is in the latch mode, and the gating control module stops inputting data to the latch module, and the data latch module will The received input data is latched so that the input data can be effectively isolated when the latch circuit is in a latch mode.

FIG. 2 is a schematic diagram of a latch circuit provided in another embodiment of the present application. On the basis of the embodiment shown in FIG. 1, optionally, the gating control module 100 includes:

The first transistor G1, the second transistor G2, the third transistor G3, and the fourth transistor G4.

The gate of the first transistor G1 is connected to the gate of the fourth transistor G4 as the first input terminal of the gating control module 100, the source of the first transistor G1 is connected to a power supply, and the first transistor G1 is connected to a power supply. The drain of a transistor G1 is connected to the source of the second transistor G2.

The gate of the second transistor G2 is the second input terminal of the gating control module 100, and the drain of the second transistor G2 is connected to the drain of the third transistor G3.

The gate of the third transistor G3 is the third input terminal of the gating control module 100, and the source of the third transistor G3 is connected to the drain of the fourth transistor G4.

The source of the fourth transistor G4 is grounded.

When the second input terminal of the gate control module 100 receives a low level, and the third input terminal of the gate control module 100 receives a high level, the gate control module 100 is in a gate state, and the gate control module 100 is in a gate state. The latch circuit is in a gate mode, and the gate control module 100 inputs the received input data into the data latch module.

When the second input terminal of the gating control module 100 receives a high level and the third input terminal of the gating control module 100 receives a low level, the gating control module 100 is in an off state, and the The latch circuit is in a latch mode, and the gate control module 100 stops inputting the received input data into the data latch module.

In practical applications, the first transistor and the second transistor may be PMOS (positive channel Metal Oxide Semiconductor, P-channel MOS), and the third transistor and the fourth transistor may be NMOS (N Metal Oxide Semiconductor, N-channel MOS). In the gating control circuit, the PMOS aspect ratio is 4a, and the NMOS aspect ratio is 4b; in the gating state, the gating control circuit is equivalent to an ordinary inverter with a PMOS aspect ratio of 2a and an NMOS aspect ratio of 2b . The ratio of a and b is determined by the carrier mobility of the PMOS and NMOS of the selected process. The ratio of a and b is the reciprocal of the carrier mobility of the corresponding PMOS and NMOS, so that the PMOS tube and the NMOS tube in the inverter The current drive capability is the same. The ordinary inverter corresponds to a PMOS width-to-length ratio of a, and the NMOS width-to-length ratio is b, then the equivalent MOS tube width-to-length ratio of the inverter corresponding to the gate control circuit in the gate state is twice that of the ordinary inverter , that is, the driving capability is twice that of the ordinary inverter.

Optionally, the data latch module 200 includes:

The first inverter C1 and the second inverter C2.

The input terminal of the first inverter C1 is the input terminal of the data latch module 200, and is connected to the output terminal of the gating control module 100, and the output terminal of the first inverter C1 is connected to the The input terminal of the second inverter C2.

The output terminal of the second inverter C2 is the output terminal of the data latch module 200, and is connected to the input terminal of the first inverter C1.

Optionally, the filtering module 300 includes:

The first flip-flop D1, the second flip-flop D2, and the logic gate L.

The data input end of the first flip-flop D1 is connected to the data input end of the second flip-flop D2 as the data input end to be filtered of the filtering module 300, and the clock signal input end of the first flip-flop D1 is The first clock signal input end of the filter circuit 300 and the clock signal input end of the second flip-flop D2 are the second clock signal input end of the filter circuit 300 .

The output end of the first flip-flop D1 is connected to the first input end of the logic gate, and the output end of the second flip-flop D2 is connected to the second input end of the logic gate L.

The output terminal of the logic gate L is the output terminal of the filtering module 300 .

Exemplarily, referring to FIG. 6 , the second input module inputs clock signals to the first flip-flop and the second flip-flop respectively, so that the phases of the clock signals received by the first flip-flop and the second flip-flop differ by 180 degrees, and The output signals of the first flip-flop and the second flip-flop can be ANDed to filter out high pulse glitches less than 1/2 clock period, while those greater than 1/2 clock period are regarded as valid signals. The burr width to be filtered can be set by adjusting the clock frequency.

Optionally, the latch circuit also includes:

Seventh inverter C7.

The input end of the seventh inverter C7 is connected to the output end of the data latch module 200 , and the output end of the seventh inverter C7 is connected to the first input end of the filtering module 300 .

In the embodiment of the present application, the input data is received by the gating control module. When the gating control module is in the off state, the latch circuit is in the latch mode, and the gating control module stops inputting data to the latch module, and the data latch module will The received input data is latched, so that when the latch circuit is in the latch mode, the input data can be effectively isolated; by connecting the filter module after the data latch module, the input data can be filtered to effectively filter out High pulse glitch in input data.

Fig. 3 is a schematic diagram of the first input module provided by the embodiment of the present application. On the basis of the embodiment shown in Fig. 2, optionally, the latch circuit further includes:

The first input module 400 .

The first output end of the first input module 400 is connected to the first input end of the gating control module 100 .

The second output end of the first input module 400 is connected to the second input end of the gating control module 100 .

When the first input module 400 receives a low level signal, the first output terminal of the first input module 400 outputs a high level signal, and the second output terminal of the first input module 400 outputs a low level signal Signal.

When the first input module 400 receives a high level signal, the first output terminal of the first input module 400 outputs a low level signal, and the second output terminal of the first input module 400 outputs a high level signal Signal.

In practical applications, when the first input module receives a high level, the gating control module is in an off state, and the latch circuit is in a latch mode; when the first input module receives a low level, the gating control module is equivalent to for the inverter.

Optionally, the first input module 400 includes:

The third inverter C3 and the fourth inverter C4.

The input terminal of the third inverter C3 is the input terminal of the first input module 400 , and the output terminal of the third inverter C3 is the first output terminal of the first input module 400 .

The input end of the fourth inverter C4 is connected to the output end of the third inverter C3 , and the output end of the fourth inverter C4 is the second output end of the first input module 400 .

In the embodiment of the present application, the first input module inputs high and low level signals respectively to the second input terminal and the third input of the gating control module, so as to control the off and on states of the gating control module.

Fig. 4 is a schematic diagram of the second input module provided by the embodiment of the present application. On the basis of the embodiment shown in Fig. 2, optionally, the latch circuit further includes:

The second input module 500 .

The first output terminal of the second input module 500 is connected to the second input terminal of the filter module 300 .

The second output terminal of the second input module 500 is connected to the third input terminal of the filtering module 300 .

When the second input module 500 receives a low level signal, the first output terminal of the second input module 500 outputs a high level signal, and the second output terminal of the second input module 500 outputs a low level signal Signal.

When the second input module 500 receives a high level signal, the first output terminal of the second input module 500 outputs a low level signal, and the second output terminal of the second input module 500 outputs a high level signal Signal.

Optionally, the second input module 500 includes:

The fifth inverter C5 and the sixth inverter C6.

The input terminal of the fifth inverter C5 is the input terminal of the second input module 500 , and the output terminal of the fifth inverter C5 is the first output terminal of the second input module 500 .

The input terminal of the sixth inverter C6 is connected to the output terminal of the fifth inverter C5 , and the output terminal of the sixth inverter C6 is the second output terminal of the second input module 500 .

In this embodiment of the present application, the second input module respectively inputs level signals to the first flip-flop and the second flip-flop, so that the phase difference of the level signals received by the first flip-flop and the second flip-flop is 180 degrees, thereby realizing Filter out high pulse burrs in the data to be filtered.

Fig. 5 is a schematic diagram of an inverter provided in the embodiment of the present application. As shown in the figure, in the embodiments corresponding to Fig. 2, Fig. 3 and Fig. 4, the inverter includes:

The fifth transistor G5 and the sixth transistor G6.

The gate of the fifth transistor G5 and the gate of the sixth transistor G6 are the input terminals of the inverter, and the drain of the fifth transistor G5 and the drain of the sixth transistor G6 are the inverters. output terminal of the phaser.

The source of the fifth transistor G5 is connected to the power supply, and the drain of the fifth transistor G5 is connected to the drain of the sixth transistor G6.

The source of the sixth transistor G6 is grounded.

In practical applications, the fifth transistor may be a PMOS (positive channel Metal Oxide Semiconductor, P-channel MOS transistor), and the sixth transistor may be an NMOS (N Metal Oxide Semiconductor, N-channel MOS transistor).

In the embodiment of the present application, the phase of the input signal can be reversed by 180 degrees through the inverter composed of the fifth transistor and the sixth transistor.

Those skilled in the art can clearly understand that for the convenience and brevity of description, only the division of the above-mentioned functional units and modules is used for illustration. In practical applications, the above-mentioned functions can be assigned to different functional units, Completion of modules means that the internal structure of the device is divided into different functional units or modules to complete all or part of the functions described above. Each functional unit and module in the embodiment may be integrated into one processing unit, or each unit may exist separately physically, or two or more units may be integrated into one unit, and the above-mentioned integrated units may adopt hardware It can also be implemented in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the protection scope of the present application. For the specific working process of the units and modules in the above system, reference may be made to the corresponding process in the foregoing method embodiments, and details will not be repeated here.

In the above-mentioned embodiments, the descriptions of each embodiment have their own emphases, and for parts that are not detailed or recorded in a certain embodiment, refer to the relevant descriptions of other embodiments.

In the embodiments provided in the present invention, it should be understood that the disclosed device may be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the modules or units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be Incorporation may either be integrated into another system, or some features may be omitted, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

The above-described embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still carry out the foregoing embodiments Modifications to the technical solutions recorded in the examples, or equivalent replacement of some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should be included in within the protection scope of the present invention.

Claims (10)

1. A latch circuit, comprising:

The device comprises a gating control module, a data latch module and a filtering module;

The output end of the gating control module is connected with the input end of the data latch module; the output end of the data latch module is connected with the data input end to be filtered of the filtering module and the output end of the gating control module;

the gating control module receives input data and inputs the input data into the data latch module, when the gating control module is in an off state, the latch circuit is in a latch mode, the data latch module latches the input data and inputs the latched input data into the filtering module as data to be filtered, and the filtering module filters the data to be filtered to obtain output data.

2. the latch circuit of claim 1, wherein said strobe control module comprises:

A first transistor, a second transistor, a third transistor, and a fourth transistor;

the grid electrode of the first transistor is connected with the grid electrode of the fourth transistor and then serves as a first input end of the gating control module, the source electrode of the first transistor is connected with a power supply, and the drain electrode of the first transistor is connected with the source electrode of the second transistor;

the grid electrode of the second transistor is a second input end of the gating control module, and the drain electrode of the second transistor is connected with the drain electrode of the third transistor;

the grid electrode of the third transistor is a third input end of the gating control module, and the source electrode of the third transistor is connected with the drain electrode of the fourth transistor;

The source electrode of the fourth transistor is grounded;

When the second input end of the gating control module receives a low level and the third input end of the gating control module receives a high level, the gating control module is in a gating state, the latch circuit is in a gating mode, and the gating control module inputs received input data into the data latch module;

when the second input end of the gating control module receives a high level and the third input end of the gating control module receives a low level, the gating control module is in an off state, the latch circuit is in a latch mode, and the gating control module stops inputting received input data into the data latch module.

3. The latch circuit according to claim 1, wherein the data latch module comprises:

a first inverter and a second inverter;

The input end of the first phase inverter is the input end of the data latch module and is connected with the output end of the gating control module, and the output end of the first phase inverter is connected with the input end of the second phase inverter;

the output end of the second phase inverter is the output end of the data latch module and is connected with the input end of the first phase inverter.

4. The latch circuit of claim 1, wherein the filter module comprises:

the circuit comprises a first trigger, a second trigger and a logic gate;

A data input end of the first trigger is connected with a data input end of the second trigger and then serves as a data input end of the filtering module to be filtered, a clock signal input end of the first trigger serves as a first clock signal input end of the filtering circuit, and a clock signal input end of the second trigger serves as a second clock signal input end of the filtering circuit;

the output end of the first trigger is connected with the first input end of the logic gate, and the output end of the second trigger is connected with the second input end of the logic gate;

And the output end of the logic gate is the output end of the filtering module.

5. The latch circuit according to claim 1, wherein the latch circuit further comprises:

a first input module;

the first output end of the first input module is connected with the first input end of the gating control module;

the second output end of the first input module is connected with the second input end of the gating control module;

When the first input module receives a low level signal, a first output end of the first input module outputs a high level signal, and a second output end of the first input module outputs a low level signal;

When the first input module receives a high level signal, a first output end of the first input module outputs a low level signal, and a second output end of the first input module outputs a high level signal.

6. The latch circuit of claim 5, wherein the first input block comprises:

a third inverter and a fourth inverter;

the input end of the third phase inverter is the input end of the first input module, and the output end of the third phase inverter is the first output end of the first input module;

The input end of the fourth phase inverter is connected with the output end of the third phase inverter, and the output end of the fourth phase inverter is the second output end of the first input module.

7. the latch circuit according to claim 1, wherein the latch circuit further comprises:

a second input module;

The first output end of the second input module is connected with the second input end of the filtering module;

a second output end of the second input module is connected with a third input end of the filtering module;

when the second input module receives a low level signal, a first output end of the second input module outputs a high level signal, and a second output end of the second input module outputs a low level signal;

When the second input module receives a high level signal, a first output end of the second input module outputs a low level signal, and a second output end of the second input module outputs a high level signal.

8. the latch circuit of claim 7, wherein the second input block comprises:

A fifth inverter and a sixth inverter;

The input end of the fifth inverter is the input end of the second input module, and the output end of the fifth inverter is the first output end of the second input module;

the input end of the sixth phase inverter is connected with the output end of the fifth phase inverter, and the output end of the sixth phase inverter is the second output end of the second input module.

9. the latch circuit according to claim 1, wherein the latch circuit further comprises:

a seventh inverter;

the input end of the seventh phase inverter is connected with the output end of the data latch module, and the output end of the seventh phase inverter is connected with the first input end of the filter module.

10. The latch circuit according to any one of claims 3, 6, 8, and 9, wherein the inverter includes:

A fifth transistor and a sixth transistor;

The grid electrode of the fifth transistor and the grid electrode of the sixth transistor are input ends of the inverter, and the drain electrode of the fifth transistor and the drain electrode of the sixth transistor are output ends of the inverter;

the source electrode of the fifth transistor is connected with a power supply, and the drain electrode of the fifth transistor is connected with the drain electrode of the sixth transistor;

The source of the sixth transistor is grounded.