CN103199845B - Bidirectional buffer based on open drain bus - Google Patents
Bidirectional buffer based on open drain bus Download PDFInfo
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- CN103199845B CN103199845B CN201210004962.5A CN201210004962A CN103199845B CN 103199845 B CN103199845 B CN 103199845B CN 201210004962 A CN201210004962 A CN 201210004962A CN 103199845 B CN103199845 B CN 103199845B
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Abstract
The invention discloses a kind of bidirectional buffer based on open drain bus, including：Reference voltage and reference current generation module；Source data comparator, the input signal of source and reference voltage are compared, and when the input signal of source is higher than reference voltage, comparator is output as high level, and when the input signal of source is less than reference voltage, comparator is output as low level；Source data operation amplifier, Closed loop operation, for assisting correctly to be transmitted from end data to source；Source data are selected and driver, for selecting source data, are transmitted to from end, and are driven reinforcement；Select from end data and drive circuit, for selecting from end data, be transmitted to source, and be driven reinforcement.The present invention can across voltage domain work, be avoided that the latch problem for bus data transfer occur again.
Description
Technical field
The present invention relates to CMOS IC design fields, more particularly to a kind of bidirectional buffering based on open drain bus
Device.
Background technology
In the agreement of open drain bus, generally all include a data bus and clock bus.Such as I2C buses
(Inter-Integrated Circuit Bus), System Management Bus (System Managements Bus).Every bus
Power supply is pulled upward to by a pull-up resistor all, every bus all has parasitic capacitance.The speed of data transfer is by resistance and electricity
The size of appearance.
In order to increase the transfer rate of data, it is necessary to reduce bus parasitic electric capacity.It is thus desirable to buffer is introduced, by bus
It is divided into multistage, so that per section of parasitic capacitance is significantly reduced.
When principal and subordinate's device of bus is operated in different voltage domains, bus must be introduced into buffer, enable bus data
Across voltage domain transmission.Again because open drain bus are two-way, the buffer for therefore introducing must be bidirectional buffer.But it is general double
To the latch problem that buffer can produce data.
Content of the invention
The technical problem to be solved in the present invention is to provide a kind of bidirectional buffer based on open drain bus, can realize bus
Across the voltage domain transmission of data, it is to avoid the latch of bus data transfer occur.
For solve above-mentioned technical problem, the present invention the bidirectional buffer based on open drain bus, including：
Reference voltage, using conventional band-gap reference circuit, respectively source data comparator and source data operation is put
Big device provides accurate reference voltage；
Reference current generation module, respectively source data comparator and source data operation amplifier are provided with reference to electricity
Stream；
Source data comparator, the data signal bus and reference voltage that source is input into are compared；When source is input into
Data signal bus be higher than reference voltage when, the source data comparator is output as high level (logic 1)；When source is input into
Data signal bus be less than reference voltage when, the source data comparator is output as low level (logical zero)；
Source data operation amplifier, Closed loop operation, its reverse input end input reference voltage, positive input number of buses
It is believed that number, for assisting the bus data from end correctly to be transmitted to source；
Reference voltage of the reference voltage of the source data comparator less than source data operation amplifier；
Source data are selected and driver, are connected with the outfan of source data comparator, for selecting source bus
Data, are transmitted to from end, and are driven reinforcement；
Select from end data and driver, for selecting, from end bus data, to be transmitted to source, and be driven plus
By force；
The bidirectional buffer realizes across voltage domain work, only source data signal bus is detected and is adjudicated, letter
Circuit design is changed；When from source to during from end transfer bus data, the data signal bus fed back to from end can not open source
End transmitter；When from end to source transfer bus data, source data comparator output signal is constant, it is ensured that from end transmitter
Close.
The bidirectional buffer is applied to open collector bus.The bidirectional buffer is applied to unidirectional open drain bus.Institute
The bidirectional buffer that states using signal is enabled, when open drain bus do not work, close by whole bidirectional buffer.
Due to open drain bus across voltage domain work sometimes, there is the latch of bus data transfer in general logic design method
(latch up) problem.Application demand of the present invention according to open drain bus, for the defect of general open drain bus bidirectional buffer,
Bidirectional buffer based on open drain bus is realized using analog- and digital- combination；By analyzing across the voltage domain spy of open drain bus
Property and latch problem Crack cause, using operational amplifier and comparator, latch is formed loop disconnection, so that bus can
Normal communication.The bidirectional buffer based on open drain bus of the present invention, can realize across voltage domain work, solve well total
Line number is avoided that the latch problem for bus data transfer occur again according to across voltage domain transmission.
Description of the drawings
The present invention is further detailed explanation with specific embodiment below in conjunction with the accompanying drawings：
Fig. 1 is existing open drain bus bidirectional buffer Organization Chart；
Fig. 2 is the one embodiment Organization Chart of bidirectional buffer based on open drain bus of the present invention；
Fig. 3 is the bidirectional buffer circuit theory diagrams based on open drain bus.
Specific embodiment
For across the voltage domain work of open drain bus, and general bidirectional bus buffer has that latch, the present invention are adopted
The design combined with analogy and digital circuit, realizes the bidirectional buffer based on open drain bus.
Shown in Figure 1, the existing bidirectional buffer based on open drain bus, including：Source circuit 100 and from terminal circuit
200.When data signal bus are from source to during from end transmission, the data signal bus first pass through the data of source circuit 100 and delay
Rush device 110 and reach node 1, then through the 2nd NMOS crystal from terminal circuit 200 being sent to from the phase inverter 220 of terminal circuit 200
The grid of pipe (from end transmitter) 230, reaches from end finally by the second nmos pass transistor 230.In the same manner, passed from from end to source
During defeated bus data, the bus data reaches node 2 through the data buffer 210 from terminal circuit 200, then through source electricity
The phase inverter 120 on road 100 is sent to the grid of first nmos pass transistor (source transmitter) 130 of source circuit 100, finally by
First nmos pass transistor 130 reaches source.
In order to adapt to across the voltage domain work of open drain bus, source and nmos pass transistor and data buffer from end must be expired
The pressure condition of the respective voltage domain of foot.
But, the bidirectional buffer shown in Fig. 1 introduces latch problem.Assume currently from source to from end transfer bus number
According to just in transmission logic 0, then node 1 is logical zero to source, through phase inverter 220 and the 2nd NMOS crystal from terminal circuit 200
Pipe 230, is logical zero from end；Logical zero from end makes node 2 through passing to node 2 from the data buffer 210 of terminal circuit 200
For logical zero, through the phase inverter 120 of source circuit 100, the grid for making the first nmos pass transistor 130 is high level, protects source
Hold logical zero.
When source external circuit discharges open drain bus, source should be changed into logic 1, but be because current source electricity
First nmos pass transistor 130 on road 100 is still opened, and therefore source actually also remains logical zero, it is impossible to the actual logic of transmission
1 signal；Here it is the problem of latch.
In order to solve the problems, such as latch, it is necessary to prevent the reverse transfer of data signal bus.I.e. when from source to from end transmission
During bus data, source can not be passed to from the bus data at end；When from from end to source transmission data when, the bus data of source
Can not be transferred to from end.As shown in Fig. 2 for this purpose, introduce core circuit 300, by the data buffer of source circuit 100 in Fig. 1
110 and phase inverter 120 save, form source circuit 400.By core circuit 300, the reverse biography of data signal bus is prevented
Defeated.
Vdd1 in Fig. 1, Fig. 2 is source power supply, and vdd2 is from end power supply.For convenience of description, by source circuit in Fig. 2
400 the first nmos pass transistor 130 and core circuit 300 merge, and generate the bidirectional buffer based on open drain bus shown in Fig. 3
Circuit.
In the bidirectional buffer circuit shown in Fig. 3, it is reverse that VIL_REF is enter into source data comparator (CMP) 350
The reference voltage of input.VOL_REF is enter into the reference electricity of source data operation amplifier (AMP) 310 reverse input end
Pressure.For the data signal bus reverse transfer for preventing data signal bus from existing when transmitting, VIL_REF is required here<VOL_
REF.IBNin and IBNout are the ginseng of source data comparator (CMP) 350 and source data operation amplifier (AMP) 310 respectively
Examine electric current.
In order to save power consumption, introduce and enable signal DDC_EN, when open drain bus do not work, whole bidirectional buffer circuit
Can close.
It is logic 1 when signal DDC_EN is enabled, from source to when transmission data is held, if be input to source data compared
The source end node voltage of 350 positive input of device (CMP) is higher than reference voltage VIL_REF, then be located at source data comparator
(CMP) the node n2 of 350 outfans is logic 1 (high level).1 signal input of logic of node n2 is to the source being made up of OR gate
Data select the input with driver 360, and source data are selected and another input of driver 360 is input into inside first
Enable signal enb.When enable signal DDC_EN is logic 1, signal enb is enabled inside first for logical zero, source bus data
Can pass through, select positioned at source data and the node SINK_TO_PAD of 360 outfan of driver is logic 1；When enable signal
When DDC_EN is logical zero, signal enb is enabled inside first for logic 1, source bus data can not pass through.It is located at from terminal circuit
200 phase inverter 220 as source data driver, increases the driving energy to subsequent conditioning circuit while signals reverse is realized
Power.
When node SINK_TO_PAD is logic 1, node SINK_FROM_PAD is logic 1.
The inverted device 320 of 1 signal of logic of node SINK_FROM_PAD is input to selecting from end data of being made up of NAND gate
Select and 330 1 input of driver, slave end data are selected and another input of driver 330 is input into enable letter inside second
Number en.When signal en is enabled inside second is logic 1, from end, bus data can pass through, and inside second enable signal en
For logical zero when, from end bus data can not pass through.
When node SINK_FROM_PAD is logic 1, positioned at the node n4 selected from end data with 330 outfan of driver
For logic 1, the 3rd nmos pass transistor 340 is opened, and is made positioned at the drain electrode of the 3rd nmos pass transistor 340 and source data operation amplifier
(AMP) the node n5 of 310 outfans is logical zero, and the first nmos pass transistor 130 closes.3rd nmos pass transistor 340 equivalent to from
End data driver, it is ensured that when node n4 is logic 1, it is logical zero that node n5 can be drawn.
If source end node voltage is less than reference voltage VIL_REF, node n2 is logical zero, and node SINK_TO_PAD is
Logical zero；Node SINK_FROM_PAD is logical zero, and node n4 is logical zero, and the 3rd nmos pass transistor 340 closes.Because source section
Point voltage is less than reference voltage VIL_REF, so source node voltage is less than reference voltage VOL_REF, so ensures that node n5 is
Logical zero, the first nmos pass transistor 130 are closed.
When source end node change in voltage, the first nmos pass transistor 130 is constantly in closed mode, blocked by from end to
The reverse data transmission of source.
It is logic 1 when signal DDC_EN is enabled, from during from end to source transmission data, if being logic from end segment point voltage
1, then node SINK_FROM_PAD is logic 1, and node n4 is logic 1, and the 3rd nmos pass transistor 340 opens, and node n5 is haled
Logical zero is arrived, source end node is output as logic 1.When source end node is logic 1, its voltage is higher than reference voltage VIL_REF, position
It is logic 1 in the node n2 of 350 outfan of source data comparator (CMP), node SINK_TO_PAD is logic 1, from the of end
The grid of bi-NMOS transistor 230 is logical zero, closes the second nmos pass transistor 230, does not affect the data sent from end.
When logical zero is sent from end, then node SINK_FROM_PAD is logical zero, and node n4 is logical zero, and the 3rd NMOS is brilliant
Body pipe 340 is closed.What source data operation amplifier 310 and the first nmos pass transistor 130 were constituted is negative-feedback circuit.If source
The voltage of end node is higher than reference voltage VOL_REF, then the voltage of node n5 is raised, 130 discharge capability of the first nmos pass transistor
Strengthen, source end node voltage reduces.As long as 130 size of the first nmos pass transistor is enough big, source end node voltage finally by clamped
Reference voltage VOL_REF.If source end node voltage is less than reference voltage VOL_REF, the voltage at node n5 can reduce, first
130 ducting capacity of nmos pass transistor weakens, and source end node voltage rises, and final source end node voltage is also equal to reference voltage VOL_
REF.In a word, when from end to source, transmission logical zero is low, source end node voltage is by clamped in reference voltage VOL_REF.As long as ginseng
Voltage VOL_REF is examined in the voltage range that open drain bus logical zero specifies, source just logically 0 is processed.Because reference voltage
VOL_REF is more than reference voltage VIL_REF, so node n2 is output as logic 1, the voltage at node SINK_TO_PAD is to patrol
Volume 1, it is logical zero to make the grid voltage from the second nmos pass transistor 230 of end through the phase inverter 220 from end, the second nmos pass transistor
230 close, and do not affect the data signal bus sent from end.
When from end node change in voltage, from end the second nmos pass transistor 230 be constantly in closed mode, blocked by
Source is to the reverse data transmission from end.
In figure 3, enable signal DDC_EN and enable signal enb inside first is produced through phase inverter 370, make inside first
Energy signal enb is produced through phase inverter 380 and enable inside second signal en.Phase inverter 370 and phase inverter 380 enhance respectively
Enable the driving that signal en is enabled inside signal enb and second inside one.
If across the voltage domain work of open drain bus, i.e. source power supply vdd1 be not equal to from end power supply vdd2, then source, from
The nmos pass transistor at end must is fulfilled for the pressure condition of respective voltage domain, it is ensured that bidirectional buffer completes transmitted in both directions.
The present invention is described in detail above by specific embodiment, but these have not been constituted to the present invention's
Limit.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and improvement, these
Should be regarded as protection scope of the present invention.
Claims (4)
1. a kind of bidirectional buffer based on open drain bus, it is characterised in that include：
Reference voltage, respectively source data comparator and source data operation amplifier provide reference voltage；
Reference current generation module, respectively source data comparator and source data operation amplifier provide reference current；
Source data comparator, the data signal bus and reference voltage that source is input into are compared；When source input total
When line data signal is higher than reference voltage, high level is output as；When the data signal bus of source input are less than reference voltage,
It is output as low level；
Source data operation amplifier, Closed loop operation, its reverse input end input reference voltage, positive input input bus number
It is believed that number, for assisting correctly to be transmitted from end bus data to source；
Reference voltage of the reference voltage of the source data comparator less than source data operation amplifier；
Source data are selected and driver, are connected with the outfan of the source data comparator, for selecting source bus
Data, are transmitted to from end, and are driven reinforcement；
Select from end data and driver, for selecting, from end bus data, to be transmitted to source, and be driven reinforcement；
The bidirectional buffer realizes across voltage domain work；Only source data signal bus are detected and are adjudicated；Work as source
To when transfer bus data are held, the data signal bus fed back to from end can not open the transmitter of source；When from end to source
During the transfer bus data of end, source data comparator output signal is constant, it is ensured that from end to source normal transmission bus data.
2. bidirectional buffer according to claim 1, it is characterised in that：It is total that the bidirectional buffer is applied to open collector
Line.
3. bidirectional buffer according to claim 1, it is characterised in that：It is total that the bidirectional buffer is applied to unidirectional open-drain
Line.
4. bidirectional buffer according to claim 1, it is characterised in that：Using enabling signal, the enable signal is through the
One phase inverter to be produced and enable signal inside first, and this enables signal inside first and produces through the second phase inverter and enable inside second
Signal；Enable signal input sources end datas to select and driver inside described first, enable inside described second signal input from
End data is selected and driver, source data comparator and source data operation amplifier；When open drain bus do not work, entirely
Bidirectional buffer is closed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210004962.5A CN103199845B (en) | 2012-01-09 | 2012-01-09 | Bidirectional buffer based on open drain bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210004962.5A CN103199845B (en) | 2012-01-09 | 2012-01-09 | Bidirectional buffer based on open drain bus |
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| CN103199845A CN103199845A (en) | 2013-07-10 |
| CN103199845B true CN103199845B (en) | 2017-03-15 |
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| CN201210004962.5A Active CN103199845B (en) | 2012-01-09 | 2012-01-09 | Bidirectional buffer based on open drain bus |
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Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN104639144B (en) * | 2013-11-08 | 2018-02-13 | 上海华虹集成电路有限责任公司 | Bidirectional analog buffer circuits |
| CN107367697B (en) * | 2017-08-24 | 2020-09-01 | 武汉大学 | Double-detector lithium battery surface temperature detection device and method |
| CN113131920B (en) * | 2021-04-09 | 2023-05-09 | 成都芯源系统有限公司 | Fast low bias voltage bi-directional buffer |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5801549A (en) * | 1996-12-13 | 1998-09-01 | International Business Machines Corporation | Simultaneous transmission bidirectional repeater and initialization mechanism |
| US6037803A (en) * | 1997-12-12 | 2000-03-14 | Micron Electronics, Inc. | Integrated circuit having two modes of I/O pad termination |
| CN1497413A (en) * | 2002-09-25 | 2004-05-19 | 三星电子株式会社 | Simultaneous two-way input/output circuit |
-
2012
- 2012-01-09 CN CN201210004962.5A patent/CN103199845B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5801549A (en) * | 1996-12-13 | 1998-09-01 | International Business Machines Corporation | Simultaneous transmission bidirectional repeater and initialization mechanism |
| US6037803A (en) * | 1997-12-12 | 2000-03-14 | Micron Electronics, Inc. | Integrated circuit having two modes of I/O pad termination |
| CN1497413A (en) * | 2002-09-25 | 2004-05-19 | 三星电子株式会社 | Simultaneous two-way input/output circuit |
Non-Patent Citations (1)
| Title |
|---|
| 基于FPGA的I2C总线控制器的设计;蒋俊华;《中国优秀硕士学位论文全文数据库 工程科技Ⅱ辑》;20071215(第6期);C042-121 * |
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