CN110502465B - Communication method of first-line bus - Google Patents
Communication method of first-line bus Download PDFInfo
- Publication number
- CN110502465B CN110502465B CN201910762913.XA CN201910762913A CN110502465B CN 110502465 B CN110502465 B CN 110502465B CN 201910762913 A CN201910762913 A CN 201910762913A CN 110502465 B CN110502465 B CN 110502465B
- Authority
- CN
- China
- Prior art keywords
- bus
- communication
- signal
- line bus
- rising edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000006854 communication Effects 0.000 title claims abstract description 72
- 238000004891 communication Methods 0.000 title claims abstract description 70
- 238000000034 method Methods 0.000 title claims abstract description 45
- 230000000630 rising effect Effects 0.000 claims abstract description 52
- 230000008569 process Effects 0.000 claims description 6
- 230000003071 parasitic effect Effects 0.000 abstract description 12
- 230000007423 decrease Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000008859 change Effects 0.000 description 2
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Dc Digital Transmission (AREA)
- Small-Scale Networks (AREA)
Abstract
In order to solve the problem that the parasitic capacitance and leakage current of a first-line bus have influence on the rising edge time of a digital level and influence on the bus communication process afterwards, the invention provides a communication method of the first-line bus, which ensures the communication quality of the first-line bus. A method of communication of a line bus comprising a microprocessor for controlling communication of a line bus, and bus devices compliant with a line bus protocol, the method of communication of a line bus comprising the steps of: the first step is to measure the actual rising edge time t2 required by the bus device in a line bus to generate a rising edge signal; setting a signal reading period T of the microprocessor, wherein the signal reading period T is not smaller than the actual rising edge time T2; and thirdly, carrying out one-line bus data communication, and reading the level signal generated by the bus device in a signal reading period T by the microprocessor.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a communication method of a first-line bus.
Background
A line bus is a low power data bus between a microprocessor and a line bus device. The first-line bus mainly comprises three parts, namely a bus master, and the bus master controls the bus communication to be carried out through a software program; the connecting wire is called a 'line' because it only needs one data line and one reference ground line; and devices compliant with a line bus protocol. Because of the communication mode based on the first-line bus technology, the field wiring is simple and the transmission is reliable, and therefore, the method is widely applied to the large-scale sensing data acquisition in the field at present. The technology overcomes the defects of complex field working conditions, difficult wiring, difficult wireless signal transmission and instability, but the technology also has problems.
The bus master in the first-line bus, i.e. the microprocessor, completes the time sequence control of the bus communication by means of an 'open-drain output'. Taking as an example the sensor DS18B20 communicating using a one-wire bus, which is most common in the market today. According to the prior manufacturer technical data, DS18B20 is powered at 3-5V, the output mode of the sensor is "open drain output", and a 4.7K pull-up resistor is adopted to provide high level. However, when a plurality of DS18B20 are simultaneously on one bus or the bus length exceeds 20 meters or the sensors exceed 20, a delay of a line bus "rising edge time" is caused due to "parasitic capacitance" and "leakage current", and a data reading error occurs. Currently, reliable readings of only up to 10 sensors are guaranteed in most cases. This phenomenon is a common problem for communication based on the "one-wire bus technology".
In order to better study the problem, the phenomena of parasitic capacitance and leakage current of the bus and the bus device can be equivalent, and the equivalent circuit diagram of the phenomena of parasitic capacitance and leakage current of the bus and the bus device can be referred to as figure 1 of the accompanying drawings. As the bus length and number of bus devices increases, the total "parasitic capacitance" increases gradually, and the "leakage resistance" decreases gradually, thus directly causing the bus "rising edge time" to delay.
After the bus "rising edge time" has occurred, the actual process of which is shown in FIG. 2, the bus reads the timing diagram. In the figure, VCC is a power supply voltage, and VH is a high-level voltage. When the number of bus devices is small or the bus length is short, the rising edge time is t1; when the number of bus devices increases or the bus length is longer, the "rising edge time" is t2. However, in technical data, the standard time for reading by the sensor is t, and the rising edge time delay generated by the bus causes the high level time generated by the sensor to exceed the standard time, so that the data read according to the standard time is always low level, and the data reading is in error.
For this phenomenon, the current common method is to reduce the resistance value of the pull-up resistor, so that the bus has enough pull-up capability, and the excessive delay of the digital level rising edge time caused by the parasitic capacitance and leakage current of the long-distance communication bus and a plurality of bus devices is avoided, but the method has two problems:
firstly, the problem of limited capacity of a first-line bus is not completely solved, and when the number of bus components is increased and the bus length is increased, the limit exists for reducing the pull-up resistance, and the difficulty still exists for longer buses and carrying more bus devices;
secondly, excessively reducing the pull-up resistance causes an increase in bus current and further causes an increase in bus power consumption, which is particularly unfavorable for low-power consumption using a battery as a power supply device.
Disclosure of Invention
In order to solve the problem that the parasitic capacitance and leakage current of a first-line bus have influence on the rising edge time of a digital level and influence on the bus communication process afterwards, the invention provides a communication method of the first-line bus, which ensures the communication quality of the first-line bus.
The technical scheme of the communication method of the first-line bus is as follows:
a method of communication of a line bus comprising a microprocessor for controlling communication of a line bus, and bus devices compliant with a line bus protocol, the method of communication of a line bus comprising the steps of:
the first step is to measure the actual rising edge time t2 required by the bus device in a line bus to generate a rising edge signal;
setting a signal reading period T of the microprocessor, wherein the signal reading period T is not smaller than the actual rising edge time T2;
and thirdly, carrying out one-line bus data communication, and reading the level signal generated by the bus device in a signal reading period T by the microprocessor.
The communication method of the first-line bus eliminates the influence of parasitic capacitance and leakage current on the communication quality of the first-line bus, and ensures that the signal reading period T is not less than the actual rising edge time T2 by adjusting the signal reading period T of the microprocessor, thereby ensuring the accurate reading of the first-line bus information.
The bus system optimized according to the method is found through actual measurement: a mounting of more than 100 bus devices and a bus communication distance of more than 100 meters can be achieved.
Further, in the communication method of the first line bus, specifically, in the first step, the method for determining the actual rising edge time t2 required for generating a rising edge signal by the bus device in the first line bus is as follows:
firstly, the microprocessor forcedly controls the communication signal to be in a low level state through 'open drain output';
then, the microprocessor ends the low level state of the communication signal and naturally generates a rising edge signal through the pull-up resistor;
finally, the microprocessor counts the process of generating the rising edge signal, and obtains the actual rising edge time t2.
Further, in the communication method of a line bus, specifically, in the first step, the time of the communication signal in the low level state is longer than the level signal reset time of the bus device.
Further, in the communication method of the first line bus, in the second step, the method for setting the signal reading period T of the microprocessor is as follows:
firstly, comparing the actual rising edge time t2 with the standard reading time t of the bus device to obtain a communication signal delay time Deltat, wherein the communication signal delay time Deltat=the actual rising edge time t 2-the standard reading time t;
then, the signal reading period T is adjusted, the signal reading period t=the standard reading time t+the communication signal delay time Δt.
The standard read time t is described in the specification of the bus device and is the signal generation period of the bus device. In general, the signal reading period T of the microprocessor is set to a standard reading time T.
By adopting the method for setting the signal reading period T, the communication rate of the first-line bus can be accelerated and the communication efficiency of the first-line bus can be improved while the accurate reading of the first-line bus information is ensured.
Further, in the communication method of the first line bus, in a first step, when the first line bus is powered up, an actual rising edge time t2 required for generating a rising edge signal by a bus device in the first line bus is measured. The parasitic capacitance and leakage current in a line bus can change along with the increase and decrease of the wires and the increase and decrease of the bus devices in the long-distance layout process. Therefore, when the line bus is powered up, the actual rising edge time t2 is measured, and the corresponding actual rising edge time t2 can be provided for different line bus systems so as to adapt to different line bus conditions.
Drawings
FIG. 1 is an equivalent circuit diagram of the bus and bus device "parasitic capacitance" and "leakage current" phenomena;
FIG. 2 is a bus read timing diagram;
fig. 3 is a flow chart of a communication method of a first-line bus according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and the specific examples. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Examples:
referring to fig. 3, the present embodiment provides a communication method of a line bus. The line bus includes a microprocessor for controlling communication of the line bus, and bus devices compliant with a line bus protocol, the communication method of the line bus comprising the steps of:
the first step is to measure the actual rising edge time t2 required by the bus device in a line bus to generate a rising edge signal;
setting a signal reading period T of the microprocessor, wherein the signal reading period T is not smaller than the actual rising edge time T2;
and thirdly, carrying out one-line bus data communication, and reading the level signal generated by the bus device in a signal reading period T by the microprocessor.
According to the communication method of the first-line bus, the influence of parasitic capacitance and leakage current on the communication quality of the first-line bus is eliminated, and the signal reading period T of the microprocessor is adjusted to be not smaller than the actual rising edge time T2, so that the accurate reading of the first-line bus information is ensured.
The bus system optimized according to the method is found through actual measurement: a mounting of more than 100 bus devices and a bus communication distance of more than 100 meters can be achieved.
In a preferred embodiment, in the communication method of the first line bus, specifically, in the first step, the method for determining the actual rising edge time t2 required for generating a rising edge signal by the bus device in the first line bus is as follows:
firstly, the microprocessor forcedly controls the communication signal to be in a low level state through 'open drain output';
then, the microprocessor ends the low level state of the communication signal and naturally generates a rising edge signal through the pull-up resistor;
finally, the microprocessor counts the process of generating the rising edge signal, and obtains the actual rising edge time t2.
In a preferred embodiment, in the communication method of a line bus, specifically, in the first step, the time that the communication signal is in the low level state is longer than the level signal reset time of the bus device.
In a preferred embodiment, in the communication method of the first line bus, in the second step, the method for setting the signal reading period T of the microprocessor is as follows:
firstly, comparing the actual rising edge time t2 with the standard reading time t of the bus device to obtain a communication signal delay time Deltat, wherein the communication signal delay time Deltat=the actual rising edge time t 2-the standard reading time t;
then, the signal reading period T is adjusted, the signal reading period t=the standard reading time t+the communication signal delay time Δt.
The standard read time t is described in the specification of the bus device and is the signal generation period of the bus device. In general, the signal reading period T of the microprocessor is set to a standard reading time T.
By adopting the method for setting the signal reading period T, the communication rate of the first-line bus can be accelerated and the communication efficiency of the first-line bus can be improved while the accurate reading of the first-line bus information is ensured.
Further, in the communication method of the first line bus, in a first step, when the first line bus is powered up, an actual rising edge time t2 required for generating a rising edge signal by a bus device in the first line bus is measured. The parasitic capacitance and leakage current in a line bus can change along with the increase and decrease of the wires and the increase and decrease of the bus devices in the long-distance layout process. Therefore, when the line bus is powered up, the actual rising edge time t2 is measured, and the corresponding actual rising edge time t2 can be provided for different line bus systems so as to adapt to different line bus conditions.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.
Claims (4)
1. A method of communication of a line bus comprising a microprocessor for controlling communication of the line bus, and bus devices compliant with a line bus protocol, the method of communication of the line bus comprising the steps of:
first, when a line bus is powered up, determining the actual rising edge time t2 required by a bus device in the line bus to generate a rising edge signal;
setting a signal reading period T of the microprocessor, wherein the signal reading period T is not smaller than the actual rising edge time T2;
and thirdly, carrying out one-line bus data communication, and reading the level signal generated by the bus device in a signal reading period T by the microprocessor.
2. A method of communication of a line bus as claimed in claim 1, characterized in that in a first step the actual rising edge time t2 required for the bus devices in the line bus to generate a rising edge signal is determined by:
firstly, the microprocessor forcedly controls the communication signal to be in a low level state through 'open drain output';
then, the microprocessor ends the low level state of the communication signal and naturally generates a rising edge signal through the pull-up resistor;
finally, the microprocessor counts the process of generating the rising edge signal, and obtains the actual rising edge time t2.
3. A communication method of a line bus as claimed in claim 2, characterized in that in the first step the communication signal is in a low state for a time longer than the reset time of the level signal according to the bus device.
4. The communication method of a line bus as set forth in claim 1, wherein in the second step, the signal reading period T of the microprocessor is set by:
firstly, comparing the actual rising edge time t2 with the standard reading time t of the bus device to obtain a communication signal delay time Deltat, wherein the communication signal delay time Deltat=the actual rising edge time t 2-the standard reading time t;
then, the signal reading period T is adjusted, the signal reading period t=the standard reading time t+the communication signal delay time Δt.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910762913.XA CN110502465B (en) | 2019-08-19 | 2019-08-19 | Communication method of first-line bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910762913.XA CN110502465B (en) | 2019-08-19 | 2019-08-19 | Communication method of first-line bus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110502465A CN110502465A (en) | 2019-11-26 |
| CN110502465B true CN110502465B (en) | 2023-06-27 |
Family
ID=68588286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910762913.XA Active CN110502465B (en) | 2019-08-19 | 2019-08-19 | Communication method of first-line bus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110502465B (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105262490B (en) * | 2015-09-18 | 2018-10-12 | 重庆川仪自动化股份有限公司 | Based on Manchester Code/decode Adaptable System and its method |
| EP3319274B1 (en) * | 2016-11-02 | 2019-04-17 | NXP USA, Inc. | Can module and method therefor |
| CN107391401B (en) * | 2017-07-03 | 2019-06-21 | 北京亚华意诺斯新能源科技有限公司 | A kind of method for reading data and system |
-
2019
- 2019-08-19 CN CN201910762913.XA patent/CN110502465B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN110502465A (en) | 2019-11-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101133457B (en) | Temperature determination and communication for multiple devices of a memory module | |
| US12094553B2 (en) | Timing-drift calibration | |
| US9746383B2 (en) | Throttling memory in response to an internal temperature of a memory device | |
| US6456544B1 (en) | Selective forwarding of a strobe based on a predetermined delay following a memory read command | |
| US20060142959A1 (en) | Circuits, systems and methods for dynamic reference voltage calibration | |
| US12123789B2 (en) | Method and device for temperature detection and thermal management based on power measurement | |
| CN107025919A (en) | Memory interface circuit and control method thereof | |
| JPS6239926A (en) | Online type serial communication interface to current loop from computer | |
| CN105353245A (en) | DRAM DDR calibration circuit and method based on ZQ pin | |
| CN110502465B (en) | Communication method of first-line bus | |
| KR20070088845A (en) | Impedance calibration method of memory module and semiconductor devices included in memory module | |
| US20140028364A1 (en) | Critical path monitor hardware architecture for closed loop adaptive voltage scaling and method of operation thereof | |
| US20190207842A1 (en) | System including master device and slave device, and operation method of the system | |
| CN206057879U (en) | A kind of multichannel long range one-wire bus host driven circuit based on microcontroller | |
| CN203688086U (en) | Two-line remote temperature measuring circuit based on digital temperature sensor | |
| US20120013361A1 (en) | Synthetic Pulse Generator for Reducing Supply Noise | |
| CN106772405A (en) | A kind of TDC laser distance measurement methods based on FPGA | |
| US20140253250A1 (en) | Method and apparatus for self-calibrating driving capability and resistance of on-die termination | |
| CN101493698A (en) | Frequency signal generating method and circuit based on CAN bus | |
| CN206946470U (en) | Flash controller with signal calibration device | |
| TWI600017B (en) | Memory control circuit unit, memory storage device and reference voltage generation method | |
| WO2019171814A1 (en) | Vehicle-mounted system | |
| KR102821901B1 (en) | Dual Self-Training Calibration Method and System for VREF Generator for Memory Interface | |
| CN221465741U (en) | Ultrasonic radar acquisition circuit based on three-wire IO communication | |
| CN212435948U (en) | Automatic control heating system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |