KR102821901B1 - Dual Self-Training Calibration Method and System for VREF Generator for Memory Interface - Google Patents

Abstract

A dual self-training calibration method and system for a reference voltage generator for a memory interface are presented. The dual self-training calibration system for a reference voltage generator for a memory interface proposed in the present invention includes a finite state machine (FSM) that controls an upward calibration or downward calibration through a dual UP/DN self-calibration unit, a dual UP/DN self-calibration unit that receives an input signal from the FSM and performs an upward calibration or downward calibration to set an upper limit or a lower limit of a reference voltage, and a final reference voltage calculation unit that receives the upper limit or the lower limit of the reference voltage from the dual UP/DN self-calibration unit and calculates a final reference voltage value.

Description

{Dual Self-Training Calibration Method and System for VREF Generator for Memory Interface}

The present invention relates to a dual self-training calibration method and system for a VREF generator for a memory interface.

Most components used in integrated circuits typically exhibit different characteristics depending on temperature, which causes the circuit that generates the reference voltage to also change its characteristics, resulting in a slight difference in the actual output voltage from the target reference voltage.

Since such changes in the reference voltage can significantly deteriorate the stability of the memory system operation, a design that considers various possibilities is required to ensure stability of the reference voltage.

This change in output voltage is sensitive not only to temperature changes, but also to process and supply voltage, so a reference power source that can stably secure a constant voltage is required in these various situations.

A bandgap reference circuit (BGR) is widely used as a reference voltage generation circuit that is less affected by PVT variation.

Integrated circuits such as memory devices generate reference voltages using BGR, which is robust to PVT variations, while consuming relatively high current in normal mode when processing commands such as read or write.

However, if the BGR used in normal mode is used as it is in a standby state where no commands are processed, power consumption increases and it is not suitable for low-power operation.

Additionally, there is a problem of increasing the area of the overall integrated circuit due to the addition of additional circuitry when using a separate BGR for low-power mode.

In the continuous pursuit of improved accuracy and I/O data rate in high-performance computing (HPC) systems, many problems arise in high-speed memory interfaces. Among them, optimization of dual self-training correction of voltage reference (VREF) generator can play a pivotal role in high-performance memory interface systems. Accurate and stable VREF generation and correction can greatly improve the precise data transactions of memory interfaces.

[1] Michele Caselli, Evgenii Tiuriny, Stefano Stanzioney, and Andrea Boni, "A 6.5 nA Static Self-Calibrating Programmable Voltage Reference for Smart SoCs" IEEE Transactions on Circuits and Systems 2022. [2] I. Lee et al., “A Subthreshold Voltage Reference with Scalable Output Voltage for Low-Power IoT Systems,” IEEE JSCC 2017.

The technical problem to be achieved by the present invention is to propose a dual self-training calibration method and system for a VREF generator for a memory interface for reference voltage generation and self-calibration of a transceiver. The dual self-training calibration method for a VREF generator according to an embodiment of the present invention is to improve the precision and stability of the voltage reference of a transceiver in a high-speed memory interface.

In one aspect, the dual self-training calibration system for a reference voltage generator for a memory interface proposed in the present invention includes a finite state machine (FSM) that controls to perform upward calibration or downward calibration through a dual UP/DN self-calibration unit, a dual UP/DN self-calibration unit that receives an input signal from the FSM and performs upward calibration or downward calibration to set an upper limit or lower limit of a reference voltage, and a final reference voltage calculation unit that receives the upper limit or lower limit of the reference voltage from the dual UP/DN self-calibration unit and calculates a final reference voltage value.

The above dual UP/DN self-correction unit includes an UP count unit and a DOWN count unit, and when the FSM is triggered, upward correction is performed through the UP count unit under the control of the FSM, the input signal is started to sweep to find the lowest level of the input signal, and the lower limit of the reference voltage is set when the input signal starts to transition from LOW to HIGH.

The above dual UP/DN self-correction unit includes an UP count unit and a DOWN count unit, and performs downward correction through the DOWN count unit under the control of the FSM, starts sweeping the input signal to find the highest level of the input signal, and sets an upper limit of the reference voltage when the input signal starts to transition from HIGH to LOW.

The above final reference voltage calculation unit calculates the final reference voltage by averaging the upper or lower limits of the reference voltage set through the dual UP/DN self-correction unit, and outputs the average value of the upper and lower limits as the corrected final reference voltage to the receiver input for sampling the receiver input data.

In another aspect, the dual self-training calibration method for a reference voltage generator for a memory interface proposed in the present invention includes a step of controlling an upward calibration or downward calibration through a dual UP/DN self-calibration unit when a finite state machine (FSM) is triggered, a step of receiving an input signal from the FSM through the dual UP/DN self-calibration unit and performing an upward calibration or downward calibration to set an upper or lower limit of a reference voltage, and a step of receiving the upper or lower limit of the reference voltage from the dual UP/DN self-calibration unit through a final reference voltage calculation unit and calculating a final reference voltage value.

According to embodiments of the present invention, a dual self-training calibration method and system for a VREF generator for a memory interface can be used to generate a reference voltage and perform self-calibration of a transceiver. In a high-speed memory interface, the accuracy and stability of the voltage reference of a transceiver are very important for optimal performance. According to embodiments of the present invention, the accuracy can be improved through the dual self-training calibration method for a VREF generator, and the efficiency of improving the noise immunity of a memory interface by effectively recovering I/O reception data with an attenuation of about -8 dB through the calibration method according to embodiments of the present invention was confirmed.

FIG. 1 is a diagram showing the configuration of a transceiver system having a VREF self-training circuit according to one embodiment of the present invention.
FIG. 2 is a diagram showing the configuration of a dual UP/DN self-training correction system of a VREF generator according to one embodiment of the present invention.
FIG. 3 is a flowchart illustrating a dual UP/DN self-training correction method of a VREF generator according to one embodiment of the present invention.
FIG. 4 is a diagram showing a simulation result of dual UP/DN self-training correction according to one embodiment of the present invention.
FIG. 5 is a diagram showing the layout of a VREF generator circuit according to one embodiment of the present invention.

The present invention proposes an approach for reference voltage generation and dual self-training calibration of a transceiver by utilizing 28 nm CMOS technology. In a high-speed memory interface, the accuracy and stability of the voltage reference of the transceiver are very important for optimal performance. According to an embodiment of the present invention, the accuracy is improved through a dual self-training calibration method of a VREF generator. In addition, the calibration method according to the embodiment of the present invention was confirmed to be effective in improving the noise immunity of the memory interface by effectively recovering I/O reception data with an attenuation of about -8 dB. Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a diagram showing the configuration of a transceiver system having a VREF self-training circuit according to one embodiment of the present invention.

Referring to FIG. 1, in a complete transceiver system having a VREF self-training circuit (110), a typical memory interface receiver (120) is based on a single-ended signal and utilizes a VREF generator (130) for accurate data sampling.

FIG. 2 is a diagram showing the configuration of a dual UP/DN self-training correction system of a VREF generator according to one embodiment of the present invention.

A dual UP/DN self-training calibration system of a VREF generator according to an embodiment of the present invention includes a dual UP/DN self-calibration unit (210), a finite state machine (FSM) (220), and a final reference voltage calculation unit (230).

The FSM (220) according to an embodiment of the present invention controls to perform upward correction or downward correction through a dual UP/DN self-correction unit.

The dual UP/DN self-correction unit (210) according to an embodiment of the present invention receives an input signal from the FSM and performs upward or downward correction to set the upper or lower limit of the reference voltage.

A dual UP/DN self-correction unit (210) according to an embodiment of the present invention includes an UP count unit (211) and a DOWN count unit (212).

First, when the FSM (220) is triggered, upward correction is performed through the UP count unit (211) under the control of the FSM (220), the input signal is started to sweep to find the lowest level of the input signal, and the lower limit of the reference voltage is set when the input signal starts to transition from LOW to HIGH.

Thereafter, under the control of the FSM (220), downward correction is performed through the DOWN count unit (212), the input signal is started to be swept to find the highest level of the input signal, and the upper limit of the reference voltage is set when the input signal starts to transition from HIGH to LOW.

The final reference voltage calculation unit (230) according to an embodiment of the present invention receives the upper or lower limit of the reference voltage from the dual UP/DN self-correction unit and calculates the final reference voltage value.

The final reference voltage calculation unit (230) according to an embodiment of the present invention calculates the final reference voltage by averaging the upper or lower limits of the reference voltage set through the dual UP/DN self-correction unit (220), and outputs the average value of the upper and lower limits as the corrected final reference voltage as a receiver input for sampling receiver input data.

Referring to FIG. 2, the dual UP/DN self-training calibration process of the VREF generator according to the embodiment of the present invention dynamically adjusts the reference voltage (VREF) according to a predefined initial VREF signal (e.g., Vref_good). The proposed dual UP/DN self-calibration VREF generator integrates separate modules for upward and downward VREF calibration by enhancing the FSM (220) and the VREF averaging function for determining the VREF value. For example, the initial process starts with the FSM (220) in an idle state waiting for activation. When the idle FSM (220) is triggered, the FSM (220) proceeds to an upward calibration phase. In this phase, the system starts sweeping the input signal from 0 V to 1 V to find the lowest level of the input signal and records this signal as V1 to set the lower bound of VREF when the transition from LOW to HIGH starts.

Afterwards, the FSM (220) of the proposed VREF generator switches to the downward correction stage, where the system sweeps the VREF value from 1 V to 0 V to find the highest level of the input signal and records it as V2 to set the upper limit of VREF when the HIGH to LOW transition starts.

After both the upward and downward corrections are completed, the FSM (220) enters the optimal state, indicating the readiness of the two boundaries (upper and lower limits). The system then calculates the final VREF value by averaging the upper and lower limits obtained in the previous step. This average value is considered as the calibrated reference voltage and is output to the receiver input for accurately sampling the receiver input data.

The proposed dual calibration process can ensure precise control of the final and optimal VREF values, which are critical for accurate and stable data sampling of single-ended memory I/O transceivers. The modular structure of each UP count section and DOWN count section allows each calibration step to be clearly divided, which makes self-training easier and improves the reliability of the memory subsystem.

FIG. 3 is a flowchart illustrating a dual UP/DN self-training correction method of a VREF generator according to one embodiment of the present invention.

A dual UP/DN self-training calibration method of a VREF generator according to an embodiment of the present invention includes a step (310) of controlling an upward calibration or downward calibration through a dual UP/DN self-calibration unit when a finite state machine (FSM) is triggered, a step (320) of receiving an input signal from the FSM through the dual UP/DN self-calibration unit and performing an upward calibration or downward calibration to set an upper or lower limit of a reference voltage, and a step (330) of receiving an upper or lower limit of a reference voltage from the dual UP/DN self-calibration unit through a final reference voltage calculation unit and calculating a final reference voltage value.

In step (310), the dual UP/DN self-training correction method of the VREF generator controls upward correction or downward correction through the dual UP/DN self-correction unit when the FSM (Finite State Machine) is triggered.

In step (320), an input signal is received from the FSM through a dual UP/DN self-correction unit and upward correction or downward correction is performed to set the upper or lower limit of the reference voltage.

A dual UP/DN self-correction unit according to an embodiment of the present invention includes an UP count unit and a DOWN count unit.

First, when the FSM is triggered, upward correction is performed through the UP count section under the control of the FSM, the input signal is started to sweep to find the lowest level of the input signal, and the lower limit of the reference voltage is set when the input signal starts to transition from LOW to HIGH.

The dual UP/DN self-training calibration process of the VREF generator according to the embodiment of the present invention dynamically adjusts the reference voltage (VREF) according to a predefined initial VREF signal (e.g., Vref_good). The proposed VREF generator with dual UP/DN self-calibration scheme integrates separate modules for upward and downward VREF calibration by enhancing the VREF averaging function for FSM and VREF value determination. For example, the initial process starts with the FSM in idle state waiting for activation. Once the idle FSM is triggered, the FSM proceeds to the upward calibration phase. In this phase, the system starts sweeping the input signal from 0 V to 1 V to find the lowest level of the input signal and records this signal as V1 to set the lower bound of VREF when the transition from LOW to HIGH starts.

Thereafter, the downward correction is performed through the DOWN count section under the control of the FSM, the input signal is started to sweep to find the highest level of the input signal, and the upper limit of the reference voltage is set when the input signal starts to transition from HIGH to LOW. Here, the system sweeps the VREF value from 1 V to 0 V to find the highest level of the input signal and records it as V2 to set the upper limit of VREF when the transition from HIGH to LOW starts.

In step (330), the upper or lower limit of the reference voltage is input from the dual UP/DN self-correction unit through the final reference voltage calculation unit, and the final reference voltage value is calculated.

According to an embodiment of the present invention, the upper or lower limit of the reference voltage set through the dual UP/DN self-correction unit is averaged to calculate the final reference voltage, and the average value of the upper and lower limits is output as the corrected final reference voltage to the receiver input for sampling the receiver input data.

After both upward and downward corrections are completed, the FSM enters the optimal state, indicating the readiness of the two boundaries (upper and lower bounds). The system then averages the upper and lower bounds obtained in the previous steps to calculate the final VREF value. This average value is considered as the calibrated reference voltage and is output to the receiver input to accurately sample the receiver input data.

The proposed dual calibration process can ensure precise control of the final and optimal VREF values, which are critical for accurate and stable data sampling of single-ended memory I/O transceivers. The modular structure of each UP count section and DOWN count section allows each calibration step to be clearly divided, which makes self-training easier and improves the reliability of the memory subsystem.

FIG. 4 is a diagram showing a simulation result of dual UP/DN self-training correction according to one embodiment of the present invention.

Fig. 4 shows the simulated transient response of the proposed VREF generator's dual up- and down-reference voltage self-training correction. The simulation results show that the proposed VREF self-training correction scheme can continuously correct the reference voltage level and generate the optimal VREF value (i.e., Cal_done signal) through the dual count up and count down FSM scheme.

FIG. 5 is a diagram showing the layout of a VREF generator circuit according to one embodiment of the present invention.

FIG. 5(a) is a diagram showing the layout of a VREF generator circuit according to one embodiment of the present invention, and FIG. 5(b) is a diagram showing the layout of a VREF dual self-training and FSM according to one embodiment of the present invention.

Table 1 summarizes the performance of the proposed VREF generator and dual VREF self-training correction design.

<Table 1>

In conclusion, we propose an innovative voltage reference calibration method according to the embodiment of the present invention, which significantly improves the reliability of memory I/O interface. By using a sophisticated modular VREF generator and calibration scheme and integrating dual VREF FSMs (i.e., upward and downward calibration), the voltage reference voltage can be dynamically adjusted and self-calibrated with high precision. The simulation results verify the reliability and efficiency of the proposed VREF generator with dual self-calibration for high-performance computing systems.

Although the embodiments have been described above by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations may be made from the above teachings. For example, appropriate results may be achieved even if the described techniques are performed in a different order than the described method, and/or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different form than the described method, or are replaced or substituted by other components or equivalents.

Therefore, other implementations, other embodiments, and equivalents to the claims are also included in the scope of the claims described below.

Claims (8)

Finite State Machine (FSM) that controls upward or downward correction through dual UP/DN self-correction unit;
A dual UP/DN self-calibration unit that receives an input signal from the above FSM and performs upward or downward correction to set the upper or lower limit of the reference voltage; and
A final reference voltage calculation unit that calculates the final reference voltage value by receiving the upper or lower limit of the reference voltage from the above dual UP/DN self-correction unit.
Including,
The above dual UP/DN self-correction unit is,
Includes an UP count section and a DOWN count section,
When the above FSM is triggered, an upward correction is performed through the UP count section under the control of the FSM, the input signal is started to sweep to find the lowest level of the input signal, and the lower limit of the reference voltage is set when the input signal starts to transition from LOW to HIGH.
Under the control of the above FSM, downward correction is performed through the DOWN count section, the input signal is started to sweep to find the highest level of the input signal, and the upper limit of the reference voltage is set when the input signal starts to transition from HIGH to LOW.
After both upward correction and downward correction through the above dual UP/DN self-correction unit are completed, the FSM indicates the upper and lower limit ready states,
The modular structure of the UP count section and DOWN count section of the above dual UP/DN self-correction section divides each upward correction and downward correction step.
Dual self-training calibration system for reference voltage generators. delete delete In the first paragraph,
The final reference voltage calculation unit above is,
The final reference voltage is calculated by averaging the upper or lower limits of the reference voltage set through the above-mentioned dual UP/DN self-correction unit, and the average value of the upper and lower limits is output as the corrected final reference voltage to the receiver input for sampling the receiver input data.
Dual self-training calibration system for reference voltage generators. A step of controlling to perform upward correction or downward correction through a dual UP/DN self-correction unit when the FSM (Finite State Machine) is triggered;
A step of receiving an input signal from the FSM through a dual UP/DN self-correction unit and performing upward or downward correction to set the upper or lower limit of the reference voltage; and
A step for calculating the final reference voltage value by receiving the upper or lower limit of the reference voltage from the dual UP/DN self-correction unit through the final reference voltage calculation unit.
Including,
The step of receiving an input signal from the FSM through the above-mentioned dual UP/DN self-correction unit and performing upward or downward correction to set the upper or lower limit of the reference voltage is as follows.
Under the control of the above FSM, upward correction is performed through the UP count section of the dual UP/DN self-correction section, the input signal is started to sweep to find the lowest level of the input signal, and the lower limit of the reference voltage is set when the input signal starts to transition from LOW to HIGH.
Under the control of the above FSM, downward correction is performed through the DOWN count section of the dual UP/DN self-correction section, the input signal is started to sweep to find the highest level of the input signal, and the upper limit of the reference voltage is set when the input signal starts to transition from HIGH to LOW.
After both upward correction and downward correction through the above dual UP/DN self-correction unit are completed, the FSM indicates the upper and lower limit ready states,
The modular structure of the UP count section and DOWN count section of the above dual UP/DN self-correction section divides each upward correction and downward correction step.
A dual self-training calibration method for reference voltage generators. delete delete In paragraph 5,
The step of calculating the final reference voltage value by receiving the upper or lower limit of the reference voltage from the dual UP/DN self-correction unit through the final reference voltage calculation unit is as follows.
The final reference voltage is calculated by averaging the upper or lower limits of the reference voltage set through the above-mentioned dual UP/DN self-correction unit, and the average value of the upper and lower limits is output as the corrected final reference voltage to the receiver input for sampling the receiver input data.
A dual self-training calibration method for reference voltage generators.