CN110473489B - A pixel arrangement structure of a double gate panel - Google Patents

Abstract

The present invention relates to the field of display technology, in particular to a pixel arrangement structure of a double-gate panel. By changing the pixel arrangement driven by each data line, sub-pixels of the same type are connected to the same data line through a corresponding transistor. Realizing that the same data line drives the same type of pixel can achieve the purpose of reducing the power consumption of pure color. The pixel arrangement structure of the dual-gate panel designed in this scheme can change the existing switching once per row to once switching per frame, which greatly reduces the frequency of charging and discharging data lines by the driver IC, thereby reducing power consumption.

Description

A pixel arrangement structure of a double gate panel

technical field

The invention relates to the field of display technology, in particular to a pixel arrangement structure of a double-gate panel.

Background technique

With the continuous development of panel display technology, various display panels with different characteristics are used in ordinary life, especially with the promotion of smart phones, panel technology has also been greatly applied. Today's smartphones pursue higher screen-to-body ratios and higher resolutions. High screen-to-body ratios require display panels to have extremely narrow borders, and high resolutions mean more pixels and signal routing designs. For For the driver IC, it is also necessary to design more signal output channels, which will lead to an increase in the cost of the IC and an increase in the volume, which will affect the size of the lower frame. In view of this, the dual gate (Dual Gate) structure of the panel came into being. . Compared with the ordinary panel, the Dual Gate panel has twice the gate wiring and halved the data wiring to achieve high resolution and narrow the lower border. But the pixel arrangement of the current Dual Gate panel, when displaying a solid color picture, such as red, green, blue, the voltage on the Data line is not flipped once every frame, but flipped once every line, which will cause excessive power consumption of the display. question.

Contents of the invention

The technical problem to be solved by the present invention is to provide a pixel arrangement structure of a double gate panel.

In order to solve the problems of the technologies described above, the scheme adopted in the present invention is:

A pixel arrangement structure of a double-gate panel, including a plurality of main pixel areas, a plurality of data wiring lines and a plurality of gate wiring lines;

Each of the main pixel areas includes three sub-pixel areas arranged in sequence along the vertical direction, each of the sub-pixel areas is located between two adjacent data lines, and each sub-pixel area is provided with two a transistor and two sub-pixels of different types, the source of the transistor in each sub-pixel area is connected to a data line, and the gate of the transistor in each sub-pixel area is connected to a gate line. The drains of the transistors in each sub-pixel area are correspondingly connected to one sub-pixel, and the sub-pixels of the same type are connected to the same data line through a corresponding transistor.

The beneficial effects of the present invention are:

In this solution, by changing the pixel arrangement driven by each data line, the same type of sub-pixel is connected to the same data line through a corresponding transistor, so that the same data line can drive the same type of pixel, which can reduce the power consumption of pure color the goal of. The pixel arrangement structure of the dual-gate panel designed in this scheme can change the existing switching once per row to once switching per frame, which greatly reduces the frequency of charging and discharging data lines by the driver IC, thereby reducing power consumption.

Description of drawings

1 is a schematic structural diagram of a pixel arrangement structure of a double-gate panel according to the present invention;

Label description:

1. Data traces; 2. Gate traces; 3. Sub-pixels.

Detailed ways

In order to describe the technical content, achieved goals and effects of the present invention in detail, the following descriptions will be made in conjunction with the embodiments and accompanying drawings.

The most critical idea of the present invention is to connect sub-pixels of the same type to the same data line through a corresponding transistor, so that the same data line can drive the same type of pixel, and the purpose of reducing pure color power consumption can be achieved.

Please refer to Fig. 1, the technical scheme provided by the present invention:

A pixel arrangement structure of a double-gate panel, including a plurality of main pixel areas, a plurality of data wiring lines and a plurality of gate wiring lines;

Each of the main pixel areas includes three sub-pixel areas arranged in sequence along the vertical direction, each of the sub-pixel areas is located between two adjacent data lines, and each sub-pixel area is provided with two a transistor and two sub-pixels of different types, the source of the transistor in each sub-pixel area is connected to a data line, and the gate of the transistor in each sub-pixel area is connected to a gate line. The drains of the transistors in each sub-pixel area are correspondingly connected to one sub-pixel, and the sub-pixels of the same type are connected to the same data line through a corresponding transistor.

As can be seen from the foregoing description, the beneficial effects of the present invention are:

In this solution, by changing the pixel arrangement driven by each data line, the same type of sub-pixel is connected to the same data line through a corresponding transistor, so that the same data line can drive the same type of pixel, which can reduce the power consumption of pure color the goal of. The pixel arrangement structure of the dual-gate panel designed in this scheme can change the existing switching once per row to once switching per frame, which greatly reduces the frequency of charging and discharging data lines by the driver IC, thereby reducing power consumption.

Further, a plurality of said main pixel regions are arranged in an array.

It can be seen from the above description that the plurality of main pixel areas are arranged in an array, which can rationally utilize the limited display space of the panel, so that the display effect of the sub-pixels in each main pixel area is better.

Further, two adjacent data traces are parallel to each other, two adjacent gate traces are parallel to each other, and the data traces and the gate traces are perpendicular to each other.

Further, the sub-pixels in each sub-pixel area display different colors.

It can be known from the above description that the color and brightness of each sub-pixel area can be guaranteed to realize displaying red, green or blue.

Further, the three sub-pixel areas arranged in sequence along the vertical direction include the first sub-pixel area, the second sub-pixel area and the third sub-pixel area, and the color of the sub-pixels in the first-time pixel area is green and blue, the colors of the sub-pixels in the second sub-pixel area are red and green, and the colors of the sub-pixels in the third sub-pixel area are blue and red.

Further, the gates of the two transistors in the same sub-pixel area are respectively connected to different gate wires, and the sources of the two transistors in the same sub-pixel area are respectively connected to different data wires.

It can be seen from the above description that through the above routing design method, the same data routing can be connected to sub-pixels of the same color, which can solve the problem of frequent charging and discharging of data routing and greatly reduce the power consumption of pure colors.

Please refer to Fig. 1, embodiment one of the present invention is:

A pixel arrangement structure of a double-gate panel includes a plurality of main pixel regions, a plurality of data lines 1 and a plurality of gate lines 2;

Each of the main pixel areas includes three sub-pixel areas arranged in sequence along the vertical direction, and each of the sub-pixel areas is located between two adjacent data routing lines 1, and each sub-pixel area is provided with Two transistors and two sub-pixels of different types, the source of the transistor in each sub-pixel area is connected to a data wiring 1, and the gate of the transistor in each sub-pixel area is connected to a gate The drain of the transistor in each sub-pixel area is connected to a sub-pixel 3, and the sub-pixels 3 of the same type are connected to the same data line 1 through a corresponding transistor.

A plurality of the main pixel areas are arranged in an array.

Two adjacent data traces 1 are parallel to each other, two adjacent gate traces 2 are parallel to each other, and the data traces 1 and the gate traces 2 are perpendicular to each other.

The gates of the two transistors in the same sub-pixel area are respectively connected to different gate wires 2 , and the sources of the two transistors in the same sub-pixel area are respectively connected to different data wires 1 .

The sub-pixels of the sub-pixels 3 in each sub-pixel region display different colors.

The three sub-pixel areas arranged in sequence along the vertical direction include the first-time pixel area, the second sub-pixel area and the third sub-pixel area, and the colors of the sub-pixels 3 in the first-time pixel area are green and blue The colors of the sub-pixels 3 in the second sub-pixel area are red and green, and the colors of the sub-pixels 3 in the third sub-pixel area are blue and red.

The pixel arrangement structure of the traditional double-gate panel can only be switched once per row when the pixels are charged. For example, during the pixel charging process, if a green screen is displayed, the voltage written by the second data line (indicated by D2 in Figure 1) is Take -5V→0→-5V→0. . . For high-frequency switching, the next frame is +5V→0→+5V→0. . . In this way, the driver IC needs to frequently charge and discharge D2, consuming more power consumption.

The pixel arrangement structure of the dual-gate panel designed in this scheme can be switched once per frame. For example, in the process of pixel charging, if a green screen is displayed, the second data line (indicated by D2 in Figure 1) is always written into -5V The voltage is switched to +5V only in the next frame, that is, the voltages of the N frames of D2 are: -5V, -5V, -5V. . . -5V, the voltage of N+1 frame of D2 is switched to: +5V, +5V, +5V. . . +5V, thereby improving the problem of excessive power consumption of the existing double-gate panel.

To sum up, the present invention provides a pixel arrangement structure of a double-gate panel. In this solution, by changing the pixel arrangement driven by each data line, the sub-pixels of the same type are connected to the same data line through a corresponding transistor. line, so that the same data line can drive the same pixel, which can reduce the power consumption of pure color. The pixel arrangement structure of the dual-gate panel designed in this scheme can change the existing switching once per row to once switching per frame, which greatly reduces the frequency of charging and discharging data lines by the driver IC, thereby reducing power consumption.

The above description is only an embodiment of the present invention, and does not limit the patent scope of the present invention. All equivalent transformations made by using the description of the present invention and the contents of the accompanying drawings, or directly or indirectly used in related technical fields, are all included in the same principle. Within the scope of patent protection of the present invention.

Claims (6)

1. The pixel arrangement structure of the double-gate panel is characterized by comprising a plurality of main pixel areas, a plurality of data wires and a plurality of gate wires;

each main pixel area comprises three sub-pixel areas which are sequentially arranged along the vertical direction, each sub-pixel area is positioned between two adjacent data wires, two transistors and two different types of sub-pixels are arranged in each sub-pixel area, the source electrode of each transistor in each sub-pixel area is correspondingly connected with one data wire, the grid electrode of each transistor in each sub-pixel area is correspondingly connected with one grid wire, the drain electrode of each transistor in each sub-pixel area is correspondingly connected with one sub-pixel, and the same type of sub-pixels are connected with the same data wire through a corresponding transistor, so that the same data wire can drive the same pixel.

2. The pixel arrangement structure of a dual gate panel according to claim 1, wherein a plurality of the main pixel regions are arranged in an array.

3. The pixel arrangement structure of claim 1, wherein two adjacent data wires are parallel to each other, two adjacent gate wires are parallel to each other, and the data wires are perpendicular to the gate wires.

4. The pixel arrangement structure of a dual gate panel according to claim 1, wherein the sub-pixels of the sub-pixels in each sub-pixel region display different colors.

5. The pixel arrangement structure of a dual gate panel according to claim 4, wherein the three sub-pixel regions sequentially arranged in the vertical direction include a first sub-pixel region, a second sub-pixel region, and a third sub-pixel region, the sub-pixels in the first sub-pixel region being green and blue, the sub-pixels in the second sub-pixel region being red and green, and the sub-pixels in the third sub-pixel region being blue and red.

6. The pixel arrangement structure of claim 1, wherein gates of two transistors in the same sub-pixel region are respectively connected to different gate wirings, and sources of two transistors in the same sub-pixel region are respectively connected to different data wirings.

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