CN216118747U - Circuit structure for reducing Data Demux wiring load - Google Patents
Circuit structure for reducing Data Demux wiring load Download PDFInfo
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- CN216118747U CN216118747U CN202122715343.4U CN202122715343U CN216118747U CN 216118747 U CN216118747 U CN 216118747U CN 202122715343 U CN202122715343 U CN 202122715343U CN 216118747 U CN216118747 U CN 216118747U
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Abstract
The utility model discloses a circuit structure for reducing Data Demux wiring loads, which is provided with more than one multiplexing module, wherein each multiplexing module comprises four thin film transistors, the grid electrodes of the four thin film transistors are respectively and electrically connected with a first shunt control signal Demux1, a second shunt control signal Demux2, a third shunt control signal Demux3 and a fourth shunt control signal Demux4, and the drain electrodes are respectively and electrically connected with a Data line. According to the utility model, on the basis of the original two demux routing control pixel driving, 4 demux routing are added, the starting time of each demux routing is still 1/2 of the pulse period, and the data signal charging time of each routing is unchanged. According to the utility model, by increasing the demux wiring sharing load, the small thrust difference between the left end and the right end of the demux wiring and the middle of the demux wiring is ensured, and the pure color of the panel is uniformly displayed.
Description
Technical Field
The utility model relates to a touch screen circuit structure, in particular to a circuit structure for reducing Data Demux wiring loads.
Background
In recent years, the touch screen display market has now entered product diversification, from small-sized mobile phones to medium-sized NB, tablet, vehicle-mounted, and even to IT products. Touch technologies mainly include an Out cell and an In cell, and for mobile phones, tablet phones and NB products, the Out cell is gradually replaced by the In cell In consideration of cost, weight and thickness. Currently, embedded (In cell) products have a trend of increasing resolution from 720p to 1080p, which is the old convention, to 2K or even 4K, which results In increasing data routing, increasing routing space requirements of fanout area of data connection IC, that is, increasing the size of bottom border. At present, the mobile phone needs a selling point with a narrow frame, and the high ratio and the narrow frame design conflict with each other, and the prior art adopts a data demux design to reduce source routing by 1:3 or 1:2 so as to reduce the size of a lower border.
As shown in fig. 1, taking 1:2 as an example, the data trace is divided into two parts, and the data signal is distributed to the corresponding 2 sub-pixels by the demux device with time shift for data signal input. In practical application, the loading of the panel data with medium and large size is large, and the design of demux elements is required to be large. As shown in fig. 2, the gate end of the Demux element has cgd and cgs capacitive loads, when the Demux element W is larger, the capacitive load is larger, the Demux elements on the Demux trace are more, the whole load of the Demux trace is larger, even if the Demux trace is driven by two sides, the element thrust difference between the left end and the right end and the middle part is still larger, the display of the panel is not uniform, and the longitudinal middle area of the panel is slightly darker than the left area and the right area.
Disclosure of Invention
The utility model aims to provide a circuit structure for reducing Data Demux routing load.
The technical scheme adopted by the utility model is as follows:
a circuit structure for reducing Data Demux routing load comprises a drive IC and more than one multiplexing module, wherein the drive IC is connected with a first shunting control signal Demux1, a second shunting control signal Demux2, a third shunting control signal Demux3 and a fourth shunting control signal Demux 4; each multiplexing module comprises four thin film transistors, the grid electrodes of the four thin film transistors are respectively and electrically connected with a first shunt control signal Demux1, a second shunt control signal Demux2, a third shunt control signal Demux3 and a fourth shunt control signal Demux4, the drain electrodes of the four thin film transistors are respectively and electrically connected with a data line, all the data lines are mutually parallel and are sequentially arranged vertically, each data line is respectively and electrically connected with the sub-pixels of the corresponding row, in the same row of display pixels, the polarities of the sub-pixels of two adjacent rows of display pixels are different, and the polarities of the sub-pixels of two adjacent rows of display pixels with the same color are different; the source electrodes of two thin film transistors connected with the data lines with the same polarity in the same multiplexing module are electrically connected with the same data signal, the polarities of two adjacent data signals are opposite, and the data signal connected with the source electrode of the thin film transistor is the same as the polarity of the data line connected with the thin film transistor.
Further, the sub-pixels include a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B); a red sub-pixel (R), a green sub-pixel (G) and a blue sub-pixel (B) together form a display pixel.
Further, the sub-pixels are sequentially arranged in a row with a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B).
Further, the pulse periods of the first, second, third, and fourth shunting control signals Demux1, Demux2, Demux3, Demux4 are equal to 1/2 of the pulse period of the scan signal Gate.
Further, the multiplexing module includes the following three;
the first multiplexing modules each include:
a first thin film transistor T1, a gate of the first thin film transistor T1 being electrically connected to the first shunt control signal Demux1, a source being electrically connected to the first data signal S1, and a drain being electrically connected to the first data line R1;
a second thin film transistor T2, a gate of the second thin film transistor T2 being electrically connected to the second shunt control signal Demux2, a source being electrically connected to the second data signal S2, and a drain being electrically connected to the second data line G2;
a third thin film transistor T3, a gate of the third thin film transistor T3 being electrically connected to the third shunting control signal Demux3, a source being electrically connected to the first data signal S1, and a drain being electrically connected to the third data line B1;
a fourth thin film transistor T4, a gate of the fourth thin film transistor T4 being electrically connected to the fourth shunt control signal Demux4, a source being electrically connected to the second data signal S2, and a drain being electrically connected to the fourth data line R2;
the second multiplexing modules each include:
a fifth thin film transistor T5, a gate of the fifth thin film transistor T5 being electrically connected to the first shunt control signal Demux1, a source being electrically connected to the third data signal S3, and a drain being electrically connected to the fifth data line G3;
a sixth thin film transistor T6, a gate of the sixth thin film transistor T6 being electrically connected to the second shunt control signal Demux2, a source being electrically connected to the fourth data signal S4, and a drain being electrically connected to the sixth data line B4;
a seventh thin film transistor T7, a gate of the seventh thin film transistor T7 being electrically connected to the third shunting control signal Demux3, a source being electrically connected to the third data signal S3, and a drain being electrically connected to the seventh data line R3;
an eighth thin film transistor T8, wherein a gate of the eighth thin film transistor T8 is electrically connected to the fourth shunt control signal Demux4, a source thereof is electrically connected to the fourth data signal S4, and a drain thereof is electrically connected to the eighth data line G4;
the third multiplexing modules each include:
a ninth thin film transistor T9, wherein a gate of the ninth thin film transistor T9 is electrically connected to the first shunt control signal Demux1, a source thereof is electrically connected to the fifth data signal S5, and a drain thereof is electrically connected to the ninth data line B5;
a tenth tft T10, wherein a gate of the tenth tft T10 is electrically connected to the second shunt control signal Demux2, a source of the tenth tft T10 is electrically connected to the sixth data signal S6, and a drain of the tenth tft T10 is electrically connected to the tenth data line R6;
an eleventh thin film transistor T11, wherein a gate of the eleventh thin film transistor T11 is electrically connected to the third shunting control signal Demux3, a source thereof is electrically connected to the fifth data signal S5, and a drain thereof is electrically connected to the eleventh data line G5;
a twelfth thin film transistor T12, a gate of the twelfth thin film transistor T12 being electrically connected to the fourth shunt control signal Demux4, a source being electrically connected to the sixth data signal S6, and a drain being electrically connected to the twelfth data line B6;
further, the first data signal S1, the third data signal S3, and the fifth data signal S5 are all positive polarity, and the second data signal S2, the fourth data signal S4, and the sixth data signal S6 are all negative polarity.
Furthermore, the first to twelfth data lines are connected with the first to twelfth columns of sub-pixels in a one-to-one correspondence, and the polarities of the sub-pixels in the first to twelfth columns are alternately arranged according to the positive pole and the negative pole.
By adopting the technical scheme, on the basis that two demux wirings originally control pixel driving and the starting time of each demux wiring is 1/2 of a pulse period, 4 demux wirings are added.
The utility model changes the control of 4 demux lines, and simultaneously avoids the problem that the charging starting time of each line is a pulse period 1/4 when 4 demux lines are adopted in the prior art, which is not beneficial to improving the charging time of data signals. In other prior art, as the resolution of the display device is improved, the pulse period of the scan signal Gate is shortened, so that the pulse periods of the first, second, third, and fourth shunting control signals Demux1, Demux2, Demux3, and Demux4 are compressed, and the data switching time allocated to each column of sub-pixels is reduced, resulting in insufficient charging rate of the sub-pixels and data signals entering the sub-pixels not reaching the level voltage.
According to the utility model, the starting time of each demux line is still 1/2 of the pulse period, the data signal charging time of each line is unchanged, but the load on each line is reduced by increasing the demux line, so that the load on the demux line is improved. According to the utility model, by increasing the demux wiring sharing load, the small thrust difference between the left end and the right end of the demux wiring and the middle of the demux wiring is ensured, and the pure color of the panel is uniformly displayed.
Drawings
The utility model is described in further detail below with reference to the accompanying drawings and the detailed description;
FIG. 1 is a schematic diagram of a data demux routing scheme according to the prior art;
FIG. 2 is a schematic diagram of the capacitive loading of a known demux cell;
FIG. 3 is a diagram illustrating a data demux routing scheme according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.
As shown in fig. 3, the present invention discloses a circuit structure for reducing Data Demux routing load, which includes a driving IC and at least one multiplexing module, wherein the driving IC is connected with a first shunting control signal Demux1, a second shunting control signal Demux2, a third shunting control signal Demux3 and a fourth shunting control signal Demux 4; each multiplexing module comprises four thin film transistors, the grid electrodes of the four thin film transistors are respectively and electrically connected with a first shunt control signal Demux1, a second shunt control signal Demux2, a third shunt control signal Demux3 and a fourth shunt control signal Demux4, the drain electrodes of the four thin film transistors are respectively and electrically connected with a data line, all the data lines are mutually parallel and are sequentially arranged vertically, each data line is respectively and electrically connected with the sub-pixels of the corresponding row, in the same row of display pixels, the polarities of the sub-pixels of two adjacent rows of display pixels are different, and the polarities of the sub-pixels of two adjacent rows of display pixels with the same color are different; the source electrodes of two thin film transistors connected with the data lines with the same polarity in the same multiplexing module are electrically connected with the same data signal, the polarities of two adjacent data signals are opposite, and the data signal connected with the source electrode of the thin film transistor is the same as the polarity of the data line connected with the thin film transistor.
Further, the sub-pixels include a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B); a red sub-pixel (R), a green sub-pixel (G) and a blue sub-pixel (B) together form a display pixel.
Further, the sub-pixels are sequentially arranged in a row with a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B).
Further, the pulse periods of the first, second, third, and fourth shunting control signals Demux1, Demux2, Demux3, Demux4 are equal to 1/2 of the pulse period of the scan signal Gate.
Further, the multiplexing module includes the following three;
the first multiplexing modules each include:
a first thin film transistor T1, a gate of the first thin film transistor T1 being electrically connected to the first shunt control signal Demux1, a source being electrically connected to the first data signal S1, and a drain being electrically connected to the first data line R1;
a second thin film transistor T2, a gate of the second thin film transistor T2 being electrically connected to the second shunt control signal Demux2, a source being electrically connected to the second data signal S2, and a drain being electrically connected to the second data line G2;
a third thin film transistor T3, a gate of the third thin film transistor T3 being electrically connected to the third shunting control signal Demux3, a source being electrically connected to the first data signal S1, and a drain being electrically connected to the third data line B1;
a fourth thin film transistor T4, a gate of the fourth thin film transistor T4 being electrically connected to the fourth shunt control signal Demux4, a source being electrically connected to the second data signal S2, and a drain being electrically connected to the fourth data line R2;
the second multiplexing modules each include:
a fifth thin film transistor T5, a gate of the fifth thin film transistor T5 being electrically connected to the first shunt control signal Demux1, a source being electrically connected to the third data signal S3, and a drain being electrically connected to the fifth data line G3;
a sixth thin film transistor T6, a gate of the sixth thin film transistor T6 being electrically connected to the second shunt control signal Demux2, a source being electrically connected to the fourth data signal S4, and a drain being electrically connected to the sixth data line B4;
a seventh thin film transistor T7, a gate of the seventh thin film transistor T7 being electrically connected to the third shunting control signal Demux3, a source being electrically connected to the third data signal S3, and a drain being electrically connected to the seventh data line R3;
an eighth thin film transistor T8, wherein a gate of the eighth thin film transistor T8 is electrically connected to the fourth shunt control signal Demux4, a source thereof is electrically connected to the fourth data signal S4, and a drain thereof is electrically connected to the eighth data line G4;
the third multiplexing modules each include:
a ninth thin film transistor T9, wherein a gate of the ninth thin film transistor T9 is electrically connected to the first shunt control signal Demux1, a source thereof is electrically connected to the fifth data signal S5, and a drain thereof is electrically connected to the ninth data line B5;
a tenth tft T10, wherein a gate of the tenth tft T10 is electrically connected to the second shunt control signal Demux2, a source of the tenth tft T10 is electrically connected to the sixth data signal S6, and a drain of the tenth tft T10 is electrically connected to the tenth data line R6;
an eleventh thin film transistor T11, wherein a gate of the eleventh thin film transistor T11 is electrically connected to the third shunting control signal Demux3, a source thereof is electrically connected to the fifth data signal S5, and a drain thereof is electrically connected to the eleventh data line G5;
a twelfth thin film transistor T12, a gate of the twelfth thin film transistor T12 being electrically connected to the fourth shunt control signal Demux4, a source being electrically connected to the sixth data signal S6, and a drain being electrically connected to the twelfth data line B6;
further, the first data signal S1, the third data signal S3, and the fifth data signal S5 are all positive polarity, and the second data signal S2, the fourth data signal S4, and the sixth data signal S6 are all negative polarity.
Furthermore, the first to twelfth data lines are connected with the first to twelfth columns of sub-pixels in a one-to-one correspondence, and the polarities of the sub-pixels in the first to twelfth columns are alternately arranged according to the positive pole and the negative pole.
By adopting the technical scheme, on the basis that two demux wirings originally control pixel driving and the starting time of each demux wiring is 1/2 of a pulse period, 4 demux wirings are added.
The utility model changes the control of 4 demux lines, and simultaneously avoids the problem that the charging starting time of each line is a pulse period 1/4 when 4 demux lines are adopted in the prior art, which is not beneficial to improving the charging time of data signals. In other prior art, as the resolution of the display device is improved, the pulse period of the scan signal Gate is shortened, so that the pulse periods of the first, second, third, and fourth shunting control signals Demux1, Demux2, Demux3, and Demux4 are compressed, and the data switching time allocated to each column of sub-pixels is reduced, resulting in insufficient charging rate of the sub-pixels and data signals entering the sub-pixels not reaching the level voltage.
According to the utility model, the starting time of each demux line is still 1/2 of the pulse period, the data signal charging time of each line is unchanged, but the load on each line is reduced by increasing the demux line, so that the load on the demux line is improved. According to the utility model, by increasing the demux wiring sharing load, the small thrust difference between the left end and the right end of the demux wiring and the middle of the demux wiring is ensured, and the pure color of the panel is uniformly displayed.
It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. The embodiments and features of the embodiments in the present application may be combined with each other without conflict. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the detailed description of the embodiments of the present application is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Claims (7)
1. The utility model provides a reduce circuit structure that Data Demux walked line load which characterized in that: the circuit comprises a drive IC and more than one multiplexing module, wherein the drive IC is connected with a first shunt control signal Demux1, a second shunt control signal Demux2, a third shunt control signal Demux3 and a fourth shunt control signal Demux 4; each multiplexing module comprises four thin film transistors, the grid electrodes of the four thin film transistors are respectively and electrically connected with a first shunt control signal Demux1, a second shunt control signal Demux2, a third shunt control signal Demux3 and a fourth shunt control signal Demux4, the drain electrodes of the four thin film transistors are respectively and electrically connected with a data line, all the data lines are mutually parallel and are sequentially arranged vertically, and each data line is respectively and electrically connected with the sub-pixels in the corresponding row; in the same row of display pixels, the polarities of the sub-pixels of two adjacent columns of display pixels are different, and the polarities of the sub-pixels of two adjacent columns of the same color are different; the source electrodes of two thin film transistors connected with the data lines with the same polarity in the same multiplexing module are electrically connected with the same data signal, the polarities of two adjacent data signals are opposite, and the data signal connected with the source electrode of the thin film transistor is the same as the polarity of the data line connected with the thin film transistor.
2. The circuit structure for reducing Data Demux trace load according to claim 1, wherein: the number of the multiplexing modules is three, and the multiplexing modules are respectively the same;
the first multiplexing modules each include:
a first thin film transistor T1, a gate of the first thin film transistor T1 being electrically connected to the first shunt control signal Demux1, a source being electrically connected to the first data signal S1, and a drain being electrically connected to the first data line R1;
a second thin film transistor T2, a gate of the second thin film transistor T2 being electrically connected to the second shunt control signal Demux2, a source being electrically connected to the second data signal S2, and a drain being electrically connected to the second data line G2;
a third thin film transistor T3, a gate of the third thin film transistor T3 being electrically connected to the third shunting control signal Demux3, a source being electrically connected to the first data signal S1, and a drain being electrically connected to the third data line B1;
a fourth thin film transistor T4, a gate of the fourth thin film transistor T4 being electrically connected to the fourth shunt control signal Demux4, a source being electrically connected to the second data signal S2, and a drain being electrically connected to the fourth data line R2;
the second multiplexing modules each include:
a fifth thin film transistor T5, a gate of the fifth thin film transistor T5 being electrically connected to the first shunt control signal Demux1, a source being electrically connected to the third data signal S3, and a drain being electrically connected to the fifth data line G3;
a sixth thin film transistor T6, a gate of the sixth thin film transistor T6 being electrically connected to the second shunt control signal Demux2, a source being electrically connected to the fourth data signal S4, and a drain being electrically connected to the sixth data line B4;
a seventh thin film transistor T7, a gate of the seventh thin film transistor T7 being electrically connected to the third shunting control signal Demux3, a source being electrically connected to the third data signal S3, and a drain being electrically connected to the seventh data line R3;
an eighth thin film transistor T8, wherein a gate of the eighth thin film transistor T8 is electrically connected to the fourth shunt control signal Demux4, a source thereof is electrically connected to the fourth data signal S4, and a drain thereof is electrically connected to the eighth data line G4;
the third multiplexing modules each include:
a ninth thin film transistor T9, wherein a gate of the ninth thin film transistor T9 is electrically connected to the first shunt control signal Demux1, a source thereof is electrically connected to the fifth data signal S5, and a drain thereof is electrically connected to the ninth data line B5;
a tenth tft T10, wherein a gate of the tenth tft T10 is electrically connected to the second shunt control signal Demux2, a source of the tenth tft T10 is electrically connected to the sixth data signal S6, and a drain of the tenth tft T10 is electrically connected to the tenth data line R6;
an eleventh thin film transistor T11, wherein a gate of the eleventh thin film transistor T11 is electrically connected to the third shunting control signal Demux3, a source thereof is electrically connected to the fifth data signal S5, and a drain thereof is electrically connected to the eleventh data line G5;
a twelfth thin film transistor T12, a gate of the twelfth thin film transistor T12 is electrically connected to the fourth shunt control signal Demux4, a source is electrically connected to the sixth data signal S6, and a drain is electrically connected to the twelfth data line B6.
3. The circuit structure for reducing Data Demux trace load according to claim 2, wherein: the first to twelfth data lines are connected with the first to twelfth columns of sub-pixels in a one-to-one correspondence mode, and the polarities of the sub-pixels in the first to twelfth columns are alternately arranged according to the positive pole and the negative pole.
4. The circuit structure for reducing Data Demux trace load according to claim 2, wherein: the first, third, and fifth data signals S1, S3, and S5 are all positive polarity, and the second, fourth, and sixth data signals S2, S4, and S6 are all negative polarity.
5. The circuit structure for reducing Data Demux trace load according to claim 1, wherein: the sub-pixels comprise a red sub-pixel (R), a green sub-pixel (G) and a blue sub-pixel (B); a red sub-pixel (R), a green sub-pixel (G) and a blue sub-pixel (B) together form a display pixel.
6. The circuit structure for reducing Data Demux trace load according to claim 5, wherein: the sub-pixels are arranged in order of a red sub-pixel (R), a green sub-pixel (G), and a blue sub-pixel (B) on one row.
7. The circuit structure for reducing Data Demux trace load according to claim 1, wherein: the pulse periods of the first, second, third, and fourth shunting control signals Demux1, Demux2, Demux3, Demux4 are equal to 1/2 of the pulse period of the scan signal Gate.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202122715343.4U CN216118747U (en) | 2021-11-08 | 2021-11-08 | Circuit structure for reducing Data Demux wiring load |
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| CN202122715343.4U CN216118747U (en) | 2021-11-08 | 2021-11-08 | Circuit structure for reducing Data Demux wiring load |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114822437A (en) * | 2022-04-18 | 2022-07-29 | Tcl华星光电技术有限公司 | Display panel and display device |
| WO2023178776A1 (en) * | 2022-03-24 | 2023-09-28 | 广州华星光电半导体显示技术有限公司 | Display panel and display device |
| WO2023184581A1 (en) * | 2022-03-30 | 2023-10-05 | 广州华星光电半导体显示技术有限公司 | Display panel and display apparatus |
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2021
- 2021-11-08 CN CN202122715343.4U patent/CN216118747U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2023178776A1 (en) * | 2022-03-24 | 2023-09-28 | 广州华星光电半导体显示技术有限公司 | Display panel and display device |
| US12223925B2 (en) | 2022-03-24 | 2025-02-11 | Guangzhou China Star Optoelectronics Semiconductor Display Technology Co., Ltd. | Display panel with a signal adjusting trace and display device |
| WO2023184581A1 (en) * | 2022-03-30 | 2023-10-05 | 广州华星光电半导体显示技术有限公司 | Display panel and display apparatus |
| CN114822437A (en) * | 2022-04-18 | 2022-07-29 | Tcl华星光电技术有限公司 | Display panel and display device |
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