[go: up one dir, main page]

CN110456451A - A kind of preparation method of area thick film silicon nitride - Google Patents

A kind of preparation method of area thick film silicon nitride Download PDF

Info

Publication number
CN110456451A
CN110456451A CN201910750245.9A CN201910750245A CN110456451A CN 110456451 A CN110456451 A CN 110456451A CN 201910750245 A CN201910750245 A CN 201910750245A CN 110456451 A CN110456451 A CN 110456451A
Authority
CN
China
Prior art keywords
layer
thickness
silicon nitride
waveguide device
preparation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910750245.9A
Other languages
Chinese (zh)
Other versions
CN110456451B (en
Inventor
李彬
李志华
张鹏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Institute of Microelectronics of CAS
Original Assignee
Institute of Microelectronics of CAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Institute of Microelectronics of CAS filed Critical Institute of Microelectronics of CAS
Priority to CN201910750245.9A priority Critical patent/CN110456451B/en
Publication of CN110456451A publication Critical patent/CN110456451A/en
Application granted granted Critical
Publication of CN110456451B publication Critical patent/CN110456451B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13Integrated optical circuits characterised by the manufacturing method
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13Integrated optical circuits characterised by the manufacturing method
    • G02B6/132Integrated optical circuits characterised by the manufacturing method by deposition of thin films
    • GPHYSICS
    • G02OPTICS
    • G02BOPTICAL ELEMENTS, SYSTEMS OR APPARATUS
    • G02B6/00Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings
    • G02B6/10Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type
    • G02B6/12Light guides; Structural details of arrangements comprising light guides and other optical elements, e.g. couplings of the optical waveguide type of the integrated circuit kind
    • G02B6/13Integrated optical circuits characterised by the manufacturing method
    • G02B6/136Integrated optical circuits characterised by the manufacturing method by etching

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Optical Integrated Circuits (AREA)

Abstract

本发明提供了一种区域厚膜氮化硅的制备方法,包括:在半导体衬底上依次形成下包层和牺牲层,牺牲层高度与预设波导器件区域厚度相同;以下包层上表面为终止层形成多个芯层区域槽;在多个芯层区域槽内和牺牲层上沉积芯层材料形成第一芯层,其厚度小于预设波导器件区域厚度;以牺牲层上表面为终止层,去除多余的第一芯层;重复上述步骤直到形成芯层的厚度达到预设波导器件区域厚度为止;以下包层上表面为终止层去除牺牲层形成多个芯层区域,并对其进行刻蚀,形成预设波导器件结构;在预设波导器件结构和下包层上形成上包层。该方案解决了因薄膜太厚而产生的高应力问题,利于实现芯片的高度集成,同时解决直接挖槽不利于制备高集成度波导器件的问题。

The invention provides a method for preparing regional thick-film silicon nitride, comprising: sequentially forming a lower cladding layer and a sacrificial layer on a semiconductor substrate, and the height of the sacrificial layer is the same as the thickness of the preset waveguide device region; the upper surface of the lower cladding layer is The termination layer forms a plurality of core layer area grooves; depositing core layer materials in the plurality of core layer area grooves and on the sacrificial layer to form the first core layer, the thickness of which is less than the thickness of the preset waveguide device area; the upper surface of the sacrificial layer is used as the termination layer , remove the redundant first core layer; repeat the above steps until the thickness of the formed core layer reaches the thickness of the preset waveguide device area; remove the sacrificial layer from the upper surface of the lower cladding layer as the termination layer to form a plurality of core layer areas, and engrave them Etching to form a preset waveguide device structure; forming an upper cladding layer on the preset waveguide device structure and the lower cladding layer. This solution solves the problem of high stress caused by too thick film, which is beneficial to realize the high integration of chips, and at the same time solves the problem that direct trenching is not conducive to the preparation of highly integrated waveguide devices.

Description

一种区域厚膜氮化硅的制备方法A kind of preparation method of area thick film silicon nitride

技术领域technical field

本发明涉及集成光学技术领域,具体涉及一种区域厚膜氮化硅的制备方法。The invention relates to the technical field of integrated optics, in particular to a preparation method of regional thick-film silicon nitride.

背景技术Background technique

目前,氮化硅薄膜生长制备方法主要有LPCVD(低压化学气相沉积)和PECVD(等离子体化学气相沉积)等。采用PECVD能够实现较厚的薄膜沉积,但薄膜中杂质较多,致密性差,以其制备的波导传输损耗高。而采用LPCVD沉积的氮化硅薄膜质量好,其波导损耗低,但存在高应力问题,尤其当薄膜厚度大于300纳米后,很难实现大面积生长,薄膜会出现大量裂纹,无法实现高性能器件的制备。现有生产工艺中,通常采用干法刻蚀工艺在二氧化硅包裹层中开槽,然后在槽中填充氮化硅的方式获得厚膜氮化硅光波导,但在制备高集成度的氮化硅器件及芯片时,需要很多不等宽、高密度的二氧化硅槽,这会引起CMP的不均匀性,增加设计与工艺难度,同时直接开槽会带来波导及其器件侧壁陡直度差、粗糙度高等问题。At present, the silicon nitride film growth and preparation methods mainly include LPCVD (low pressure chemical vapor deposition) and PECVD (plasma chemical vapor deposition). Thick film deposition can be achieved by using PECVD, but there are many impurities in the film and the compactness is poor, so the waveguide prepared by it has high transmission loss. However, the silicon nitride film deposited by LPCVD has good quality and low waveguide loss, but there is a problem of high stress, especially when the film thickness is greater than 300 nanometers, it is difficult to achieve large-area growth, and a large number of cracks will appear in the film, which cannot realize high-performance devices. preparation. In the existing production process, a dry etching process is usually used to open a groove in the silicon dioxide cladding layer, and then fill the groove with silicon nitride to obtain a thick-film silicon nitride optical waveguide, but in the preparation of highly integrated nitrogen When siliconizing devices and chips, a lot of unequal width and high-density silicon dioxide grooves are required, which will cause unevenness of CMP and increase the difficulty of design and process. Problems such as poor straightness and high roughness.

发明内容Contents of the invention

为了克服现有技术中氮化硅沉积厚膜出现高应力的技术问题,以及挖槽带来的诸多工艺难题,进而提供了一种区域厚膜氮化硅的制备方法,从而满足不同的设计需要。In order to overcome the technical problems of high stress in silicon nitride deposited thick films in the prior art, as well as many process difficulties caused by trenching, a method for preparing regional thick film silicon nitride is provided to meet different design needs .

本发明提供了一种区域厚膜氮化硅的制备方法,包括:The invention provides a method for preparing a regional thick-film silicon nitride, comprising:

S1、在半导体衬底上沿半导体衬底的厚度方向依次形成下包层和牺牲层,牺牲层的高度与预设波导器件区域的厚度相同;S1, sequentially forming a lower cladding layer and a sacrificial layer on the semiconductor substrate along the thickness direction of the semiconductor substrate, and the height of the sacrificial layer is the same as the thickness of the predetermined waveguide device region;

S2、以下包层的上表面为终止层,光刻与刻蚀牺牲层,在牺牲层内形成多个芯层区域槽;S2. The upper surface of the lower cladding layer is used as a termination layer, and the sacrificial layer is photolithographically etched to form a plurality of core region grooves in the sacrificial layer;

S3、在多个芯层区域槽内和牺牲层上沉积芯层材料,形成第一芯层,第一芯层的厚度小于预设波导器件区域的厚度;S3. Depositing core material in grooves in multiple core regions and on the sacrificial layer to form a first core layer, the thickness of the first core layer is smaller than the thickness of the preset waveguide device region;

S4、以牺牲层的上表面为终止层,采用表面平坦化工艺去除多余的第一芯层;S4, using the upper surface of the sacrificial layer as the termination layer, and removing the redundant first core layer by using a surface planarization process;

S5、重复S3、S4直到多个芯层区域槽内形成的芯层的厚度达到预设波导器件区域的厚度为止;S5, repeating S3 and S4 until the thickness of the core layers formed in the grooves of the multiple core layer regions reaches the thickness of the preset waveguide device region;

S6、以下包层的上表面为终止层,去除牺牲层,形成多个芯层区域;S6. The upper surface of the lower cladding layer is used as a termination layer, and the sacrificial layer is removed to form a plurality of core layer regions;

S7、对多个芯层区域分别进行刻蚀,在每个芯层区域内形成预设波导器件结构;S7. Etching a plurality of core layer regions respectively, forming a preset waveguide device structure in each core layer region;

S8、在预设波导器件结构和下包层上形成上包层。S8, forming an upper cladding layer on the predetermined waveguide device structure and the lower cladding layer.

进一步地,下包层的材料为折射率低于1.7且高于1的固态包层材料。Further, the material of the lower cladding layer is a solid cladding material with a refractive index lower than 1.7 and higher than 1.

进一步地,固态包层材料为二氧化硅。Further, the solid cladding material is silicon dioxide.

进一步地,下包层采用热氧化和/或化学气相沉积工艺制备。Further, the lower cladding layer is prepared by thermal oxidation and/or chemical vapor deposition.

进一步地,牺牲层由无定形硅或多晶硅沉积形成。Further, the sacrificial layer is formed by depositing amorphous silicon or polysilicon.

进一步地,预设波导器件区域的厚度为350纳米至1000纳米。Further, the preset thickness of the waveguide device region is 350 nm to 1000 nm.

进一步地,芯层材料为氮化硅或氮氧化硅中的任意一种。Further, the material of the core layer is any one of silicon nitride or silicon oxynitride.

进一步地,第一芯层的厚度为50纳米至300纳米。Further, the thickness of the first core layer is 50 nm to 300 nm.

进一步地,对多个芯层区域进行刻蚀时,采用干法刻蚀工艺。Further, when etching the multiple core layer regions, a dry etching process is used.

进一步地,步骤S8中,上包层采用化学气相沉积工艺沉积折射率低于1.7且高于1的固态包层材料。Further, in step S8, a solid cladding material with a refractive index lower than 1.7 and higher than 1 is deposited on the upper cladding layer using a chemical vapor deposition process.

本发明相对于现有技术,具有以下有益效果:Compared with the prior art, the present invention has the following beneficial effects:

本发明通过在牺牲层内形成多个芯层区域槽即形成多个可制备波导器件区域,然后逐层沉积芯层材料,达到预设波导器件区域的厚度,可以解决采用现有技术沉积方式因薄膜太厚而产生的高应力问题;此外,以牺牲层作为隔离区,对形成的多个芯层区域分别进行刻蚀,在每个芯层区域内形成预设的多种波导器件结构,利于实现芯片的高度集成;此外,本发明还通过沉积制备的牺牲层,牺牲层的厚度容易调节,通过控制牺牲层的厚度来确定最终需要的预设波导器件区域的厚度,从而实现对预设波导器件结构厚度的控制,满足不同的设计需要,更加的方便灵活;通过去除牺牲层,刻蚀芯层区域的方式形成最终波导器件结构,相比于现有技术中直接生长得到的氮化硅,可以在大晶圆上实现更厚的薄膜生长,同时解决直接挖槽不利于制备高集成度波导器件的问题。The present invention forms a plurality of waveguide device regions by forming a plurality of core region grooves in the sacrificial layer, and then deposits the core layer material layer by layer to reach the thickness of the preset waveguide device region, which can solve the problem of using the prior art deposition method. The problem of high stress caused by too thick film; in addition, using the sacrificial layer as the isolation area, the multiple core layer regions formed are respectively etched, and a variety of preset waveguide device structures are formed in each core layer region, which is beneficial to Realize the high integration of the chip; in addition, the present invention also prepares the sacrificial layer by depositing, the thickness of the sacrificial layer is easy to adjust, and the thickness of the preset waveguide device area that is finally required is determined by controlling the thickness of the sacrificial layer, thereby realizing the preset waveguide The control of the thickness of the device structure meets different design needs, and is more convenient and flexible; the final waveguide device structure is formed by removing the sacrificial layer and etching the core layer region. Compared with the silicon nitride grown directly in the prior art, It can realize thicker film growth on a large wafer, and at the same time solve the problem that direct trenching is not conducive to the preparation of highly integrated waveguide devices.

附图说明Description of drawings

图1是本发明实施例一种区域厚膜氮化硅的制备方法流程示意图;1 is a schematic flow chart of a method for preparing a regional thick-film silicon nitride according to an embodiment of the present invention;

图2(1)至图2(7)为本发明实施例提供的一种区域厚膜氮化硅的制备方法制程对应的剖面结构示意图。Fig. 2 (1) to Fig. 2 (7) are schematic cross-sectional structural diagrams corresponding to the manufacturing process of a method for preparing a regional thick-film silicon nitride provided by an embodiment of the present invention.

具体实施方式Detailed ways

为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本发明进行进一步详细说明。应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。In order to make the object, technical solution and advantages of the present invention more clear, the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present invention, not to limit the present invention.

本实施方式中一种区域厚膜氮化硅的制备方法,如图1所示,包括:A method for preparing a regional thick-film silicon nitride in this embodiment, as shown in FIG. 1 , includes:

S1、在半导体衬底上沿半导体衬底的厚度方向依次形成下包层和牺牲层,牺牲层的高度与预设波导器件区域的厚度相同;S1, sequentially forming a lower cladding layer and a sacrificial layer on the semiconductor substrate along the thickness direction of the semiconductor substrate, and the height of the sacrificial layer is the same as the thickness of the predetermined waveguide device region;

在上述方案基础上,进一步地,在本实施方式中半导体衬底为硅衬底,在其他实施方式中,半导体衬底还可以为石英衬底。On the basis of the above solutions, further, the semiconductor substrate in this implementation manner is a silicon substrate, and in other implementation manners, the semiconductor substrate may also be a quartz substrate.

在上述方案基础上,进一步地,下包层采用热氧化和/或化学气相沉积工艺沉积形成,在其他实施方式中,下包层还可以采用物理气相沉积工艺形成。下包层材料包括折射率低于1.7且高于1的固态包层材料,优选为二氧化硅。On the basis of the above solution, further, the lower cladding layer is formed by thermal oxidation and/or chemical vapor deposition process, and in other embodiments, the lower cladding layer can also be formed by physical vapor deposition process. The lower cladding material includes a solid cladding material with a refractive index lower than 1.7 and higher than 1, preferably silicon dioxide.

在上述方案基础上,进一步地,牺牲层由无定形硅或多晶硅沉积形成。On the basis of the above solutions, further, the sacrificial layer is formed by depositing amorphous silicon or polysilicon.

在上述方案基础上,进一步地,预设波导器件区域的厚度相同为350纳米至1000纳米,由于牺牲层的高度与预设波导器件区域的厚度相同,所以牺牲层的高度为350纳米至1000纳米。On the basis of the above scheme, further, the thickness of the preset waveguide device area is the same as 350 nanometers to 1000 nanometers, and since the height of the sacrificial layer is the same as the thickness of the preset waveguide device region, the height of the sacrificial layer is 350 nanometers to 1000 nanometers .

S2、以下包层的上表面为终止层,光刻与刻蚀牺牲层,在牺牲层内形成多个芯层区域槽;S2. The upper surface of the lower cladding layer is used as a termination layer, and the sacrificial layer is photolithographically etched to form a plurality of core region grooves in the sacrificial layer;

S3、在多个芯层区域槽内和牺牲层上沉积芯层材料,形成第一芯层,第一芯层的厚度小于预设波导器件区域的厚度;S3. Depositing core material in grooves in multiple core regions and on the sacrificial layer to form a first core layer, the thickness of the first core layer is smaller than the thickness of the preset waveguide device region;

在一些实施例中,通过各种沉积技术中的任意一种,包括低压化学气相沉积(LPCVD)、大气压化学气相沉积(APCVD)、等离子体增强化学气相沉积(PECVD)、物理气相沉积(PVD)、溅射和其他合适的沉积技术来形成第一芯层。In some embodiments, by any of a variety of deposition techniques, including low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) , sputtering and other suitable deposition techniques to form the first core layer.

在上述方案基础上,进一步地,芯层材料包括氮化硅。在其他实施方式中,芯层材料还可以是氮氧化硅。On the basis of the above solution, further, the material of the core layer includes silicon nitride. In other embodiments, the material of the core layer may also be silicon oxynitride.

在上述方案基础上进一步地,第一芯层的厚度为50纳米至300纳米。Further on the basis of the above solution, the thickness of the first core layer is 50 nm to 300 nm.

S4、以牺牲层的上表面为终止层,采用表面平坦化工艺去除多余的第一芯层;S4, using the upper surface of the sacrificial layer as the termination layer, and removing the redundant first core layer by using a surface planarization process;

在上述方案基础上,进一步地,表面平坦化工艺具体采用化学机械抛光(CMP)。On the basis of the above solution, further, the surface planarization process specifically adopts chemical mechanical polishing (CMP).

S5、重复S3、S4直到多个芯层区域槽内形成的芯层的厚度达到预设波导器件区域的厚度为止;S5, repeating S3 and S4 until the thickness of the core layers formed in the grooves of the multiple core layer regions reaches the thickness of the preset waveguide device region;

在多个芯层区域槽内和牺牲层上继续沉积芯层材料,形成第二芯层,以牺牲层的上表面为终止层,采用表面平坦化工艺去除多余的第二芯层,芯层区域槽内的第一芯层和第二芯层的总厚度小于或等于预设波导器件区域的厚度时,继续重复S3、S4直到芯层区域槽内形成的芯层的厚度达到预设波导器件区域的厚度为止;Continue to deposit core layer materials in the grooves of multiple core layer areas and on the sacrificial layer to form a second core layer. The upper surface of the sacrificial layer is used as the termination layer, and the redundant second core layer is removed by surface planarization process, and the core layer area When the total thickness of the first core layer and the second core layer in the groove is less than or equal to the thickness of the preset waveguide device region, continue to repeat S3 and S4 until the thickness of the core layer formed in the groove in the core region reaches the preset waveguide device region up to the thickness;

S6、以下包层的上表面为终止层,去除牺牲层,形成多个芯层区域;S6. The upper surface of the lower cladding layer is used as a termination layer, and the sacrificial layer is removed to form a plurality of core layer regions;

S7、对多个芯层区域分别进行刻蚀,在每个芯层区域内形成预设波导器件结构;S7. Etching a plurality of core layer regions respectively, forming a preset waveguide device structure in each core layer region;

在上述方案基础上,进一步地,对多个芯层区域进行刻蚀时,采用干法刻蚀工艺。On the basis of the above solution, further, when etching the multiple core layer regions, a dry etching process is adopted.

S8、在预设波导器件结构和下包层上形成上包层。S8, forming an upper cladding layer on the predetermined waveguide device structure and the lower cladding layer.

在上述方案基础上,进一步地,本步骤中的上包层采用化学气相沉积工艺沉积折射率低于1.7且高于1的固态包层材料形成。On the basis of the above solution, further, the upper cladding layer in this step is formed by depositing a solid cladding material with a refractive index lower than 1.7 and higher than 1 by a chemical vapor deposition process.

在上述实施例的基础上,上包层材料与下包层材料选择一致,可以选择为二氧化硅。在一些实施例中,也可采用其它折射率低于1.7且高于1的固态包层材料。On the basis of the above embodiments, the material of the upper cladding layer is selected in the same way as the material of the lower cladding layer, and may be silicon dioxide. In some embodiments, other solid cladding materials with refractive indices below 1.7 and above 1 may also be used.

下面通过实施例对该申请的技术方案进行详细说明。The technical solution of the application is described in detail below through examples.

S1、在半导体衬底上沿半导体衬底的厚度方向依次形成下包层和牺牲层,牺牲层的高度与预设波导器件区域的厚度相同;S1, sequentially forming a lower cladding layer and a sacrificial layer on the semiconductor substrate along the thickness direction of the semiconductor substrate, and the height of the sacrificial layer is the same as the thickness of the predetermined waveguide device region;

如图2(1)所示,本领域技术人员可以采用热氧化和/或化学气相沉积工艺沉积形成下包层201,其中下包层201的材料可以是折射率低于1.7且高于1的固态包层材料,本实施例中下包层201采用的材料优选为二氧化硅;牺牲层202采用沉积工艺,例如可以为低压化学气相沉积(LPCVD)、大气压化学气相沉积(APCVD)、等离子体增强化学气相沉积(PECVD)、物理气相沉积(PVD)、溅射和其它合适的沉积技术来形成。牺牲层202采用的材料优选为无定形硅;半导体衬底200的材料可以是硅衬底或石英衬底,本实施例中半导体衬底200采用的材料优选为硅衬底。As shown in FIG. 2 (1), those skilled in the art can deposit and form the lower cladding layer 201 by thermal oxidation and/or chemical vapor deposition process, wherein the material of the lower cladding layer 201 can be a material with a refractive index lower than 1.7 and higher than 1. Solid cladding material, the material used in the lower cladding layer 201 in this embodiment is preferably silicon dioxide; the sacrificial layer 202 adopts a deposition process, such as low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), plasma Enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), sputtering and other suitable deposition techniques to form. The material used for the sacrificial layer 202 is preferably amorphous silicon; the material used for the semiconductor substrate 200 may be a silicon substrate or a quartz substrate, and the material used for the semiconductor substrate 200 in this embodiment is preferably a silicon substrate.

其中,预设波导器件区域的厚度为350纳米至1000纳米。具体的,预设波导器件区域的厚度可以根据具体需要设置,优选为400纳米至900纳米,最优选为500纳米至700纳米。例如可以为350纳米、400纳米、500纳米、700纳米、900纳米或1000纳米中的任意一种,本实施例中预设波导器件区域的厚度优选为 400纳米,由于牺牲层202的高度与预设波导器件区域的厚度相同,所以牺牲层202的高度为400纳米。Wherein, the predetermined thickness of the waveguide device region is 350 nanometers to 1000 nanometers. Specifically, the thickness of the preset waveguide device region can be set according to specific needs, preferably 400 nm to 900 nm, and most preferably 500 nm to 700 nm. For example, it can be any one of 350 nanometers, 400 nanometers, 500 nanometers, 700 nanometers, 900 nanometers or 1000 nanometers. In this embodiment, the thickness of the preset waveguide device region is preferably 400 nanometers. The thickness of the waveguide device area is assumed to be the same, so the height of the sacrificial layer 202 is 400 nanometers.

S2、以下包层的上表面为终止层,光刻与刻蚀牺牲层,在牺牲层内形成多个芯层区域槽;S2. The upper surface of the lower cladding layer is used as a termination layer, and the sacrificial layer is photolithographically etched to form a plurality of core region grooves in the sacrificial layer;

如图2(2)所示,光刻与刻蚀牺牲层202具体如下:在牺牲层202上依次通过涂光刻胶、曝光、显影、刻蚀、干法去胶工艺,形成芯层区域槽203。形成芯层区域槽203的刻蚀方法具体可以为干法刻蚀。在牺牲层202内形成多个芯层区域槽203。As shown in Figure 2 (2), the details of photolithography and etching of the sacrificial layer 202 are as follows: on the sacrificial layer 202, the process of coating photoresist, exposure, development, etching, and dry stripping is performed sequentially to form grooves in the core layer region 203. The etching method for forming the groove 203 in the core layer region may specifically be dry etching. A plurality of core region grooves 203 are formed in the sacrificial layer 202 .

S3、在多个芯层区域槽内和牺牲层上沉积芯层材料,形成第一芯层,第一芯层的厚度小于预设波导器件区域的厚度;S3. Depositing core material in grooves in multiple core regions and on the sacrificial layer to form a first core layer, the thickness of the first core layer is smaller than the thickness of the preset waveguide device region;

如图2(3)所示,在多个芯层区域槽203内和牺牲层202上沉积芯层材料,芯层材料包括氮化硅或氮氧化硅,本实施例中优选使用氮化硅作为芯层材料,芯层材料一部分沉积在芯层区域槽203内,一部分沉积在牺牲层202上,采用低压化学气相沉积(LPCVD)工艺向芯层区域槽203内填充氮化硅,形成第一芯层204,其中形成的第一芯层204厚度可以为50纳米至300纳米,优选第一芯层204厚度为80至200纳米,最优选第一芯层204厚度为100至150纳米,本实施例中第一芯层204厚度为100纳米,小于预设波导器件区域的厚度400纳米。As shown in FIG. 2 (3), core material is deposited in multiple core area grooves 203 and on the sacrificial layer 202. The core material includes silicon nitride or silicon oxynitride. In this embodiment, silicon nitride is preferably used as Core layer material, a part of the core layer material is deposited in the core region groove 203, and a part is deposited on the sacrificial layer 202, and the low pressure chemical vapor deposition (LPCVD) process is used to fill the core layer region groove 203 with silicon nitride to form the first core Layer 204, wherein the first core layer 204 formed may have a thickness of 50 nm to 300 nm, preferably the first core layer 204 has a thickness of 80 to 200 nm, and most preferably the first core layer 204 has a thickness of 100 to 150 nm. In this embodiment The thickness of the first core layer 204 is 100 nanometers, which is 400 nanometers less than the thickness of the predetermined waveguide device region.

S4、以牺牲层的上表面为终止层,采用表面平坦化工艺去除多余的第一芯层;S4, using the upper surface of the sacrificial layer as the termination layer, and removing the redundant first core layer by using a surface planarization process;

如图2(4)所示,通过表面平坦化工艺磨平,去除牺牲层202上多余的氮化硅,如在芯层区域槽203内形成最终的第一芯层204。本实施例中,表面平坦化工艺具体为化学机械抛光方法(CMP)进行磨平处理。As shown in FIG. 2 ( 4 ), the excess silicon nitride on the sacrificial layer 202 is removed through surface planarization process, such as forming the final first core layer 204 in the core region groove 203 . In this embodiment, the surface planarization process is specifically a chemical mechanical polishing method (CMP) for grinding.

S5、重复S3、S4直到多个芯层区域槽内形成的芯层的厚度达到预设波导器件区域的厚度为止;S5, repeating S3 and S4 until the thickness of the core layers formed in the grooves of the multiple core layer regions reaches the thickness of the preset waveguide device region;

如图2(5)所示,在芯层区域槽203内多次采用低压化学气相沉积(LPCVD)工艺沉积氮化硅,并通过化学机械抛光(CMP)去除多余的氮化硅,直到最后形成的芯层205的厚度达到预设波导器件区域的厚度400纳米为止。As shown in Figure 2 (5), silicon nitride is deposited in the groove 203 in the core layer area by low-pressure chemical vapor deposition (LPCVD) for many times, and excess silicon nitride is removed by chemical mechanical polishing (CMP) until finally The thickness of the core layer 205 reaches 400 nanometers of the predetermined waveguide device region.

S6、以下包层的上表面为终止层,去除牺牲层,形成多个芯层区域;S6. The upper surface of the lower cladding layer is used as a termination layer, and the sacrificial layer is removed to form a plurality of core layer regions;

如图2(6)所示,采用湿法腐蚀去除多余的牺牲层202,形成多个芯层区域206。As shown in FIG. 2 ( 6 ), the excess sacrificial layer 202 is removed by wet etching to form a plurality of core layer regions 206 .

其中,湿法腐蚀的工艺步骤如下:根据牺牲层202中的无定形硅和下包层201中的二氧化硅的比例确定湿法腐蚀溶液。具体地,采用稀释的四甲基氢氧化铵(TMAH)溶液湿法腐蚀。选择的湿法腐蚀溶液对非晶硅的腐蚀速率大于对二氧化硅、氮化硅的腐蚀速率,从而实现在去除残留的牺牲层202的同时,不会去除掉或者仅去除很少量的芯层205。Wherein, the process steps of the wet etching are as follows: the wet etching solution is determined according to the ratio of the amorphous silicon in the sacrificial layer 202 to the silicon dioxide in the lower cladding layer 201 . Specifically, a dilute tetramethylammonium hydroxide (TMAH) solution is used for wet etching. The etching rate of the selected wet etching solution to amorphous silicon is greater than that of silicon dioxide and silicon nitride, so that while removing the remaining sacrificial layer 202, no or only a small amount of core Layer 205.

S7、对多个芯层区域分别进行刻蚀,在每个芯层区域内形成预设波导器件结构;S7. Etching a plurality of core layer regions respectively, forming a preset waveguide device structure in each core layer region;

如图2(6)和图2(7)所示,对多个芯层区域206进行干法刻蚀,形成多个预设波导器件结构207。As shown in FIG. 2 ( 6 ) and FIG. 2 ( 7 ), dry etching is performed on multiple core layer regions 206 to form multiple preset waveguide device structures 207 .

S8、在预设波导器件结构和下包层上形成上包层。S8, forming an upper cladding layer on the predetermined waveguide device structure and the lower cladding layer.

如图2(7)所示,最后在形成的预设波导器件结构207上沉积折射率低于1.7且高于1的固态包层材料形成上包层,在本实施例中具体采用二氧化硅,通过在预设波导器件结构207上沉积二氧化硅形成上包层,与下包层201共同形成包层结构208,上包层的沉积工艺条件与下包层201的沉积方法相同,在此不再赘述。As shown in Figure 2 (7), finally, a solid cladding material with a refractive index lower than 1.7 and higher than 1 is deposited on the formed preset waveguide device structure 207 to form an upper cladding layer. In this embodiment, silicon dioxide is specifically used , the upper cladding layer is formed by depositing silicon dioxide on the predetermined waveguide device structure 207, and together with the lower cladding layer 201 to form the cladding layer structure 208, the deposition process conditions of the upper cladding layer are the same as the deposition method of the lower cladding layer 201, here No longer.

以上为本申请实施例提供的一种区域厚膜氮化硅的制备方法,该方案提出了新颖的划区域方法,解决了因薄膜太厚而产生的高应力问题,利于实现芯片的高度集成,可以在大晶圆上实现更厚的薄膜生长,同时解决直接挖槽不利于制备高集成度波导器件的问题。The above is a preparation method of regional thick-film silicon nitride provided by the embodiment of the present application. This scheme proposes a novel region-dividing method, which solves the problem of high stress caused by too thick a film, and is beneficial to realize high integration of chips. It can realize thicker film growth on a large wafer, and at the same time solve the problem that direct trenching is not conducive to the preparation of highly integrated waveguide devices.

上面的实施例仅仅是对本发明的优选实施方式进行描述,并非对本发明的构思和范围进行限定。在不脱离本发明设计构思的前提下,本领域普通人员对本发明的技术方案做出的各种变型和改进,均应落入到本发明的保护范围,本发明请求保护的技术内容,已经全部记载在权利要求书中。The above embodiments are only descriptions of preferred implementations of the present invention, and are not intended to limit the concept and scope of the present invention. Under the premise of not departing from the design concept of the present invention, various modifications and improvements made by ordinary persons in the art to the technical solution of the present invention shall fall within the scope of protection of the present invention, and the technical content claimed in the present invention has been fully described in the claims.

Claims (10)

1. a kind of preparation method of region thick film silicon nitride characterized by comprising
S1, along the thickness direction of the semiconductor substrate under-clad layer and sacrificial layer are sequentially formed on a semiconductor substrate, it is described sacrificial The height of domestic animal layer is identical as the thickness in default waveguide device region;
S2, using the upper surface of the under-clad layer as stop layer, photoetching and etch the sacrificial layer, formed in the sacrificial layer more A core region slot;
S3, deposition of core layer material in multiple core region slots and on the sacrificial layer, the first sandwich layer of formation, described first The thickness of sandwich layer is less than the thickness in the default waveguide device region;
S4, using the upper surface of the sacrificial layer as stop layer, extra first sandwich layer is removed using surface planarisation technique;
S5, S3, S4 are repeated until the thickness of the sandwich layer formed in multiple core region slots reaches the default waveguide device Until the thickness in region;
S6, using the upper surface of the under-clad layer as stop layer, remove the sacrificial layer, form multiple core regions;
S7, multiple core regions are performed etching respectively, forms default waveguide device structure in each core region;
S8, top covering is formed in the default waveguide device structure and the under-clad layer.
2. the preparation method of thick film silicon nitride in region according to claim 1, which is characterized in that the material of the under-clad layer Solid blanket material for refractive index lower than 1.7 and higher than 1.
3. the preparation method of thick film silicon nitride in region according to claim 2, which is characterized in that the solid blanket material For silica.
4. the preparation method of thick film silicon nitride in region according to claim 1, which is characterized in that the under-clad layer is using warm Oxidation and/or chemical vapor deposition process preparation.
5. the preparation method of thick film silicon nitride in region according to claim 1, which is characterized in that the sacrificial layer is by without fixed Shape silicon or polysilicon deposition are formed.
6. the preparation method of thick film silicon nitride in region according to claim 1, which is characterized in that the default waveguide device Region with a thickness of 350 nanometers to 1000 nanometers.
7. the preparation method of thick film silicon nitride in region according to claim 1, which is characterized in that the core material is nitrogen Any one in SiClx or silicon oxynitride.
8. the preparation method of thick film silicon nitride in region according to claim 1, which is characterized in that the thickness of first sandwich layer Degree is 50 nanometers to 300 nanometers.
9. the preparation method of thick film silicon nitride in region according to claim 1, which is characterized in that multiple sandwich layer areas When domain performs etching, using dry etch process.
10. the preparation method of thick film silicon nitride in region according to claim 1, which is characterized in that in the step S8, institute State solid blanket material of the top covering using chemical vapor deposition process deposition refractive index lower than 1.7 and higher than 1.
CN201910750245.9A 2019-08-14 2019-08-14 A kind of preparation method of area thick film silicon nitride Active CN110456451B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910750245.9A CN110456451B (en) 2019-08-14 2019-08-14 A kind of preparation method of area thick film silicon nitride

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910750245.9A CN110456451B (en) 2019-08-14 2019-08-14 A kind of preparation method of area thick film silicon nitride

Publications (2)

Publication Number Publication Date
CN110456451A true CN110456451A (en) 2019-11-15
CN110456451B CN110456451B (en) 2020-09-04

Family

ID=68486527

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910750245.9A Active CN110456451B (en) 2019-08-14 2019-08-14 A kind of preparation method of area thick film silicon nitride

Country Status (1)

Country Link
CN (1) CN110456451B (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111522094A (en) * 2020-05-06 2020-08-11 贵阳学院 BOX-shaped silicon nitride waveguide and preparation method thereof
CN113471656A (en) * 2021-05-31 2021-10-01 中国科学院微电子研究所 Waveguide device and preparation method thereof
CN115084815A (en) * 2022-05-22 2022-09-20 上海图灵智算量子科技有限公司 Method for preparing T-shaped waveguide
CN119667859A (en) * 2025-02-18 2025-03-21 上海铭锟半导体有限公司 A method for making silicon nitride waveguide using side walls

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004097464A2 (en) * 2003-04-29 2004-11-11 Xponent Photonics Inc. Multiple-core planar optical waveguides and methods of fabrication and use thereof
CN101197264A (en) * 2007-12-25 2008-06-11 上海集成电路研发中心有限公司 Forming method of L-shaped side wall
CN101471242A (en) * 2007-12-28 2009-07-01 东京毅力科创株式会社 Pattern forming method and semiconductor manufacturing device
WO2012109159A1 (en) * 2011-02-12 2012-08-16 Tokyo Electron Limited Method of etching features in silicon nitride films
CN103839820A (en) * 2012-11-25 2014-06-04 中国科学院微电子研究所 Semiconductor device manufacturing method
CN103972080A (en) * 2014-05-20 2014-08-06 上海华力微电子有限公司 ONO structure and manufacturing method for ONO capacitor
CN104360442A (en) * 2014-11-18 2015-02-18 四川飞阳科技有限公司 Planar optical waveguide device and manfucturing method thereof
CN104865223A (en) * 2015-05-27 2015-08-26 东南大学 Refractive index sensing chip of silicon nitride waveguide Bragg grating and preparation method of refractive index sensing chip
CN104977655A (en) * 2015-06-18 2015-10-14 湖南晶图科技有限公司 Wafer processing method for improving performance of PLC optical waveguides
US20170254953A1 (en) * 2016-03-04 2017-09-07 Inphi Corporation Vertical integration of hybrid waveguide with controlled interlayer thickness
CN110045460A (en) * 2019-05-31 2019-07-23 中国科学院微电子研究所 A kind of manufacturing method of optical waveguide

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004097464A2 (en) * 2003-04-29 2004-11-11 Xponent Photonics Inc. Multiple-core planar optical waveguides and methods of fabrication and use thereof
CN101197264A (en) * 2007-12-25 2008-06-11 上海集成电路研发中心有限公司 Forming method of L-shaped side wall
CN101471242A (en) * 2007-12-28 2009-07-01 东京毅力科创株式会社 Pattern forming method and semiconductor manufacturing device
WO2012109159A1 (en) * 2011-02-12 2012-08-16 Tokyo Electron Limited Method of etching features in silicon nitride films
CN103839820A (en) * 2012-11-25 2014-06-04 中国科学院微电子研究所 Semiconductor device manufacturing method
CN103972080A (en) * 2014-05-20 2014-08-06 上海华力微电子有限公司 ONO structure and manufacturing method for ONO capacitor
CN104360442A (en) * 2014-11-18 2015-02-18 四川飞阳科技有限公司 Planar optical waveguide device and manfucturing method thereof
CN104865223A (en) * 2015-05-27 2015-08-26 东南大学 Refractive index sensing chip of silicon nitride waveguide Bragg grating and preparation method of refractive index sensing chip
CN104977655A (en) * 2015-06-18 2015-10-14 湖南晶图科技有限公司 Wafer processing method for improving performance of PLC optical waveguides
US20170254953A1 (en) * 2016-03-04 2017-09-07 Inphi Corporation Vertical integration of hybrid waveguide with controlled interlayer thickness
CN110045460A (en) * 2019-05-31 2019-07-23 中国科学院微电子研究所 A kind of manufacturing method of optical waveguide

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
FRENCH P J 等: ""New silicon micromachining techniques for microsystems"", 《SENSORS & ACTUATORS A PHYSICAL》 *
刘耀东等: "光子集成用的新型波导材料Si3N4", 《物理》 *
吴清鑫等: "PECVD法生长氮化硅工艺的研究", 《功能材料》 *
魏景辉: ""基于MEMS硅基底双频段阵列式微带天线研究"", 《中国优秀硕士学位论文全文数据库信息科技辑》 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111522094A (en) * 2020-05-06 2020-08-11 贵阳学院 BOX-shaped silicon nitride waveguide and preparation method thereof
CN113471656A (en) * 2021-05-31 2021-10-01 中国科学院微电子研究所 Waveguide device and preparation method thereof
CN115084815A (en) * 2022-05-22 2022-09-20 上海图灵智算量子科技有限公司 Method for preparing T-shaped waveguide
CN119667859A (en) * 2025-02-18 2025-03-21 上海铭锟半导体有限公司 A method for making silicon nitride waveguide using side walls

Also Published As

Publication number Publication date
CN110456451B (en) 2020-09-04

Similar Documents

Publication Publication Date Title
CN110045460B (en) A method of manufacturing an optical waveguide
CN110459464B (en) Preparation method of thick film silicon nitride by regional grooving
CN110456451B (en) A kind of preparation method of area thick film silicon nitride
CN110161606B (en) A kind of preparation method of coupling grating
CN110456450B (en) A kind of preparation method of thick film silicon nitride waveguide
CN110441860B (en) A method for making trenches for thick-film silicon nitride waveguides
US20030052082A1 (en) Method of forming optical waveguides in a semiconductor substrate
CN112285827A (en) Preparation method of multilayer silicon photonic device
CN110320600B (en) Optical waveguide and manufacturing method thereof
CN108321119B (en) Three-dimensional optoelectronic integrated filter based on CMOS post-processing and its preparation method
CN105223646B (en) Low-loss three-dimensional silica waveguide chi structure and preparation method thereof
CN112612148B (en) A kind of optical device and its manufacturing method
CN107039459A (en) SOI and body silicon mixing crystal circle structure and preparation method thereof
CN111522094B (en) BOX-shaped silicon nitride waveguide and preparation method thereof
US6786968B2 (en) Method for low temperature photonic crystal structures
CN116299854B (en) Preparation method of silicon nitride device based on stress dispersion and crack blocking patterns
CN114203874A (en) A patterned composite substrate, preparation method and LED epitaxial wafer
CN112680715B (en) Growth method of silicon nitride film and preparation method of thick film silicon nitride waveguide device
CN114488394B (en) Silicon nitride grating coupler and preparation method thereof, optical device
CN117233892A (en) Preparation method of optical waveguide and optical waveguide
CN115116845A (en) Method for manufacturing semiconductor device
JPS59182538A (en) Semiconductor device and manufacture thereof
JPH03268444A (en) Manufacturing method of semiconductor device
CN113471289B (en) Silicon-on-insulator substrate and preparation method and application thereof
KR100318461B1 (en) Semiconductor device isolation method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant