CN110429139A - Binary channels LTPS thin film transistor (TFT) - Google Patents

Abstract

A dual-channel LTPS thin film transistor, comprising a first SD electrode, a second SD electrode, a first semiconductor channel layer, and a second semiconductor channel layer; the first SD electrode conducts with the second SD electrode through the first semiconductor channel layer , the first SD electrode is also connected to the second SD electrode through the second semiconductor channel layer, the first SD electrode is not in contact with the second SD electrode, the first semiconductor channel layer is not in contact with the second semiconductor channel layer, and the thin film In at least one sectional plane of the transistor, the first SD electrode, the second SD electrode, the first semiconductor channel layer, and the second semiconductor channel layer surround the interlayer dielectric layer. The above technical solution not only ensures the safety of the thin film transistor by designing a double-channel semiconductor channel layer, but also more effectively improves the electron migration efficiency of the oxide thin film transistor and increases the on-state current of the semiconductor thin film transistor.

Description

Dual Channel LTPS Thin Film Transistor

technical field

The invention relates to the field of liquid crystal panel design, in particular to an LTPS thin film transistor architecture with dual current paths.

Background technique

TFT (Thin Film Transistor) is the abbreviation of thin film transistor. TFT display is the mainstream display device on various notebook computers and desktops. Each liquid crystal pixel on this type of display is driven by a thin film transistor integrated behind the pixel, so TFT display is also a type of Active-matrix liquid crystal display devices. It is one of the best LCD color displays. TFT display has the advantages of high responsiveness, high brightness, high contrast, etc., and its display effect is close to that of CRT display.

At the same time, TFT screens are also widely used in mid-to-high-end color screen mobile phones. There are three types: 65536 colors, 160,000 colors, and 16 million colors. The display effect is very good.

TFT means that each liquid crystal pixel on the liquid crystal display is driven by a thin film transistor integrated behind it. In this way, high-speed, high-brightness and high-contrast display screen information can be achieved. TFT-LCD (thin film transistor liquid crystal display) is a kind of most liquid crystal displays. LCD and OLED Demux designs are currently receiving more and more attention from display manufacturers, because they have the following advantages: 1. The number of IC output pins is reduced, and the cost of IC is reduced; 2. The number of IC output pins is reduced, which is conducive to reducing the height of fanout cables , which is beneficial to the panel design with a narrow border on the lower border.

Low temperature polysilicon technology LTPS (Low Temperature Poly-silicon) was originally developed by Japanese and North American technology companies in order to reduce the energy consumption of the Note-PC display and make the Note-PC appear thinner and lighter. Panels designed with demux are often concentrated On the basis of the LTPS process, the reason is that the carrier mobility of LTPS is relatively high, which meets the requirements of demux design for TFT. However, as the screen-to-body ratio requirements of mobile phones are getting higher and higher, the lower border of the panel is required to be smaller and smaller, which requires a further reduction in the height of the demux, and the reduction in the height of the demux requires a higher on-state current of the demux TFT device; in this way, it can be further reduced The size of the TFT, thereby reducing the width of the demux.

The invention proposes a device and structure suitable for demux TFT. The device adopting the structure can double the on-state current; furthermore, the size of the demux TFT can be reduced.

Contents of the invention

For this reason, there is a need to provide an LTPS-related transistor capable of improving electron mobility,

In order to achieve the above object, the inventor provides a dual-channel LTPS thin film transistor, including a first SD electrode, a second SD electrode, a first semiconductor channel layer, and a second semiconductor channel layer;

The first SD electrode conducts with the second SD electrode through the first semiconductor channel layer, and the first SD electrode also conducts with the second SD electrode through the second semiconductor channel layer, and the first SD electrode and the second SD electrode No contact, the first semiconductor channel layer is not in contact with the second semiconductor channel layer,

In at least one sectional plane of the thin film transistor, the first SD electrode, the second SD electrode, the first semiconductor channel layer, and the second semiconductor channel layer surround the interlayer dielectric layer therein.

Further, the sectional plane includes a base layer, a first gate layer, a first insulating layer, a first semiconductor channel layer, a first SD electrode, a second SD electrode, a second semiconductor channel layer, an interlayer dielectric layer, a second insulating layer, second gate layer.

Specifically, the semiconductor channel layer is a phosphorus-silicon semiconductor channel layer.

Different from the existing technology, the above technical solution not only ensures the safety of the thin film transistor by designing a double-channel semiconductor channel layer, but also more effectively improves the electron migration efficiency of the oxide thin film transistor, and improves the on-state of the semiconductor thin film transistor. current.

Description of drawings

Fig. 1 is a schematic diagram of each module of the lower frame of the panel described in the specific embodiment;

Fig. 2 is the traditional bottom gate LTPS TFT cross-sectional structure schematic diagram described in the specific embodiment;

Fig. 3 is a schematic diagram of the dual-channel LTPS structure and manufacturing process described in the specific embodiment;

Fig. 4 is a schematic diagram of the open state of the dual-channel LTPS structure described in the specific embodiment;

FIG. 5 is an application example of the dual-channel LTPS device described in the specific embodiment.

Detailed ways

In order to explain in detail the technical content, structural features, achieved goals and effects of the technical solution, the following will be described in detail in conjunction with specific embodiments and accompanying drawings.

Please look at Figure 1 here, which is a schematic diagram of the modules in the lower border of the panel in the prior art. The lower border mainly includes the following modules: FPC, IC, fanout and demux modules, where the specifications of FPC, IC and fanout depend on the resolution of the panel rate, process and selection. Demux height mainly depends on the on-state current of demux TFT. Figure 2 is a TFT schematic diagram and process of the traditional bottom gate LTPS structure. The disadvantage of this traditional solution is that the electron mobility is not high. Based on the above principle, it can be imagined that the height of the Demux cannot be effectively reduced.

This solution provides a dual-channel LTPS thin film transistor, as shown in Figure 3, in Figure 3 we can include the first SD electrode on the left, the second SD electrode on the right, the first semiconductor channel layer in the lower middle, a second semiconducting channel layer on the middle slice;

The first SD electrode is conducted or communicated with the second SD electrode through the first semiconductor channel layer, which means that there is a path for electron migration between the first SD electrode-the first semiconductor channel layer-the second SD electrode. The first SD electrode is also conducted or communicated with the second SD electrode through the second semiconductor channel layer, which means that there is a path for electron migration between the first SD electrode-the second semiconductor channel layer-the second SD electrode. The first SD electrode is not in contact with the second SD electrode, and the first semiconductor channel layer is not in contact with the second semiconductor channel layer. At the same time, in at least one section plane of the thin film transistor, the first SD electrode, the second SD electrode, the first semiconductor channel layer The channel layer and the second semiconductor channel layer enclose a portion of an interlayer dielectric layer ILD (Interlayer Dielectric), and the ILD can prevent a short circuit between the first and second semiconductor channels. Through the above solution, the present invention completes the design of a dual-channel LTPS thin film transistor, improves electron mobility, and uses this type of transistor in panel design to reduce the thickness of the frame.

In some other embodiments as shown in Figure 3, the section plane includes a base layer (glass layer in the figure, other materials such as ceramics can also be used), a GI layer (first insulating layer) and a first insulating layer located on the base layer. The gate layer gate, the first semiconductor channel layer arranged thereon (the P-Si layer in the figure can also be designed as a PN type semiconductor, etc. according to the situation), the first SD electrode, the second SD electrode, the first electrode and the second The contact portion of the second electrode and the second semiconductor channel layer extends downwards, and the downward extensions of the first electrode and the second electrode are connected with the first semiconductor channel layer through the P-gap layer. Between the first semiconductor channel layer and the second semiconductor medium layer is an interlayer dielectric layer ILD, and the ILD is also arranged between the SD electrode and the first insulating layer. The cross-sectional view is the second insulating layer GI, and the upper surface of the second insulating layer is also designed with a second gate layer gate.

In the embodiment shown in FIG. 3 , the mask process between these levels is also briefly described. It is divided into the following steps in order to prepare the buffer base layer. The first mask is the first gate layer, the second mask is the silicon-phosphorus semiconductor P-Si, the third mask is the P-hole layer P+, and the fourth mask is the P-hole layer P+. The mask is the silicon-phosphorus semiconductor P-Si as the second semiconductor channel layer, the fifth mask is the nitrogen hole layer N+, the sixth mask is the electrode layer, and the seventh mask is the second gate layer of the gate. When the gate on the second gate has a high potential, the upper channel is turned on, and at the same time, the lower gate of the first gate is required to be at a low potential at this time, the lower channel is turned on, and the upper and lower channels are turned on at the same time; the conduction current doubles. The above scheme defines the basic process of using this dual channel device, which requires a total of 10 steps and 7 masks.

Fig. 4 is a schematic and schematic diagram of the dual channel LTPS open state of the present invention. Since it is a dual channel, compared with the device structure in Fig. 1, the TFT open state current of the device adopting this dual channel structure will be doubled.

FIG. 5 shows a practical application example of the present invention, such as a schematic diagram of a circuit in which the device structure of the present invention can be applied to 1To3demux design. We can design the phases of demux_CK and demux_XCK to be opposite, so as to achieve the purpose of reasonably using the transistor with high on-state current of the solution of the present invention, and the Demux using this solution can have a thinner design, and finally reduce the frame thickness of the panel.

It should be noted that although the foregoing embodiments have been described herein, the scope of protection of the present invention is not limited thereby. Therefore, based on the innovative concept of the present invention, the changes and modifications made to the embodiments described herein, or the equivalent structure or equivalent process conversion made by using the description of the present invention and the contents of the accompanying drawings, directly or indirectly apply the above technical solutions In other related technical fields, all are included in the patent protection scope of the present invention.

Claims (3)

1. a kind of binary channels LTPS thin film transistor (TFT), which is characterized in that led including the first SD electrode, the 2nd SD electrode, the first half Body channel layer, the second semiconductor channel layer；

For the first SD electrode by the first semiconductor channel layer and the 2nd SD electrode conduction, the first SD electrode also passes through the Two semiconductor channel layers and the 2nd SD electrode conduction, the first SD electrode are not contacted with the 2nd SD electrode, the first semiconductor channel layer It is not contacted with the second semiconductor channel layer,

In at least one cutting plane of thin film transistor (TFT), the first SD electrode, the 2nd SD electrode, the first semiconductor channel layer, Two semiconductor channel layers surround interlayer dielectric layer wherein.

2. binary channels LTPS thin film transistor (TFT) according to claim 1, which is characterized in that the cutting plane include base, First grid layer, the first insulating layer, the first semiconductor channel layer, the first SD electrode, the 2nd SD electrode, the second channel semiconductor Layer, interlayer dielectric layer, second insulating layer, second grid layer.

3. binary channels LTPS thin film transistor (TFT) according to claim 1, which is characterized in that the semiconductor channel layer is Phosphorus-silicon semiconductor channel layer.