CN110427065B - Double-circuit line loss compensation circuit based on DCDC converter - Google Patents
Double-circuit line loss compensation circuit based on DCDC converter Download PDFInfo
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- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
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- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is DC
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
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Abstract
The invention relates to the technical field of DCDC converters, and particularly discloses a double-line loss compensation circuit based on a DCDC converter, which is applied to the DCDC converter and comprises a double-line loss compensation module, wherein the input end of the double-line loss compensation module is respectively connected with a sampling resistor Rs1 and a sampling resistor Rs2, the output end of the double-line loss compensation module is connected with a feedback pin VFB, the feedback pin VFB is connected with a feedback resistor R1 and a feedback resistor R2, the other end of the feedback resistor R1 is connected with an equivalent line loss resistor Rcable, the other end of the equivalent line loss resistor Rcable is connected with a sampling resistor Rs1 and a sampling resistor Rs2, and one ends of the sampling resistor Rs1, the sampling resistor Rs2 and the feedback resistor R2 are respectively grounded; the output voltage Vout of the DCDC converter passes through the equivalent line loss resistor Rcable to obtain load voltage Vload, the two-way line loss compensation module receives voltage drops on the sampling resistor Rs1 and the sampling resistor Rs2 and converts the voltage drops into current Ic to extract the current of the feedback resistor R1, and therefore the output voltage Vout is corrected.
Description
Technical Field
The invention relates to the technical field of DCDC converters, in particular to a double-line loss compensation circuit based on a DCDC converter.
Background
In the prior art, an invention patent with publication number CN 2018116169800 discloses a line loss compensation circuit and an implementation method, including a control IC, a resistor RU, a resistor RD and a sampling resistor RSENSE connected to a voltage input terminal VBUS, where the control IC is internally connected with a comparison logic circuit, two input terminals of the comparison logic circuit are connected to two ends of the sampling resistor RSENSE through a SNSN port and a SNSP port of the control IC, respectively, and are used to transmit a sampling voltage to a ground resistor RC connected to the comparison logic circuit, so as to obtain a sampling current I C, the comparison logic circuit is further connected with a current source ICMP, and is used to output a smaller one of a maximum line compensation current ILIM and a sampling current preset inside the control IC, and finally form a compensation voltage superimposed on the voltage input terminal VBUS on the resistor RU; although the invention can control the maximum voltage compensation value and the compensation range, and the voltage compensation is not limited by the requirement of the fixed resistance value of the external voltage division network, the invention can only provide compensation aiming at a single-path load and is not suitable for double-path line loss compensation.
Another patent with publication No. CN2014107659908 discloses a DCDC converter with line loss compensation, which includes a control circuit, a filter circuit, a feedback circuit, and a line loss compensation circuit; the input voltage generates chip end output voltage after passing through the control circuit and the filter circuit, and generates load end output voltage after passing through the line loss resistor to supply power to the load end; the output voltage of the chip end is fed back to the control circuit through the feedback resistor and the compensation resistor; the line loss compensation circuit obtains load current by detecting the voltage at the output end of an error amplifier in the control circuit, extracts compensation current proportional to the load current from a feedback port of the compensation resistor and compensates the line loss voltage drop of the output voltage at the load end; although the compensation voltage and the loss voltage can be completely consistent, the output voltage is not changed along with the load current and is kept constant, and the compensation value can be flexibly set by the external resistor, the compensation is only provided for a single-path load, if the compensation circuit is applied to double-path line loss compensation, all circuits need to be repeatedly increased, in addition, the compensation circuit reflects that the precision of the load current on the wide input voltage and the output load range is poor through detecting the EA output end, and particularly in the application occasion of double-path line loss compensation.
Disclosure of Invention
Aiming at the technical problems, the invention provides a double-line loss compensation circuit based on a DCDC converter, which is simple in structure, suitable for single-line and double-line load application occasions, free of an external resistor and high in compensation precision.
In order to solve the technical problems, the invention provides the following specific scheme:
the utility model provides a double-circuit line loss compensating circuit based on DCDC converter, is applied to the DCDC converter, includes double-circuit line loss compensation module, double-circuit line loss compensation module's input is connected with sampling resistance Rs1 and sampling resistance Rs2 respectively, and double-circuit line loss compensation module's output is connected with feedback pin VFB, feedback pin VFB is connected with feedback resistance R1 and feedback resistance R2, feedback resistance R1's the other end is connected with equivalent line loss resistance Rcable, sampling resistance Rs1 and sampling resistance Rs2 are connected to equivalent line loss resistance Rcable's the other end, sampling resistance Rs1, sampling resistance Rs2 and feedback resistance R2's one end ground connection respectively;
the output voltage Vout of the DCDC converter passes through an equivalent line loss resistor Rcable to obtain a load voltage Vload, and the two-way line loss compensation module receives voltage drops on a sampling resistor Rs1 and a sampling resistor Rs2, converts the voltage drops into a current Ic and extracts the current of a feedback resistor R1, so that the output voltage Vout is corrected.
Optionally, the two-way line loss compensation module includes a start circuit, a trimming circuit, a first current mirror, a low-pass filter, and an addition transconductance amplifier;
the starting circuit, the trimming circuit and the first current mirror are respectively connected with the addition transconductance amplifier, and the low-pass filter is connected with the first current mirror.
Optionally, the summing transconductance amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, and a resistor R3 to a resistor R12;
one end of the resistor R3 is connected with the source electrode of the first NMOS transistor MN1 after the resistors R3, R5, R7, R9 and R11 are sequentially connected in series, and one end of the resistor R11 is connected with the drain electrode of the first PMOS transistor MP 1; the drain electrode of the first NMOS transistor MN1 and the drain electrode of the second NMOS transistor MN2 are connected together and then are connected to the first current mirror;
one end of the resistor R4, the resistor R6, the resistor R8, the resistor R10 and the resistor R12 are sequentially connected in series, one end of the resistor R4 is connected with the source electrode of the second NMOS transistor MN2, and one end of the resistor R12 is connected with the drain electrode of the second PMOS transistor MP 2;
the grid electrode of the first NMOS transistor MN1 and the source electrode of the first PMOS transistor MP1 are respectively connected with a node VN, and the grid electrode of the second NMOS transistor MN2 and the source electrode of the second PMOS transistor MP2 are respectively connected with a node VP;
the gate of the first PMOS transistor MP1 is connected to the sampling resistor Rs1, and the gate of the second PMOS transistor MP2 is connected to the sampling resistor Rs 2.
Optionally, the trimming circuit includes fifth to twelfth NMOS transistors MN5 to MN12, resistors R3 to R12;
the drain and the source of the fifth NMOS transistor MN5 are respectively connected to two ends of a resistor R5; the drain and the source of the sixth NMOS transistor MN6 are respectively connected to two ends of a resistor R6; the grid electrode of the fifth NMOS transistor MN5 is connected with the grid electrode of a sixth NMOS transistor MN 6;
the drain electrode and the source electrode of the seventh NMOS transistor MN7 are respectively connected to two ends of a resistor R7; the drain and the source of the eighth NMOS transistor MN8 are respectively connected to two ends of a resistor R8; the grid electrode of the seventh NMOS transistor MN7 is connected with the grid electrode of the eighth NMOS transistor MN 8;
the drain and the source of the ninth NMOS transistor MN9 are respectively connected to two ends of a resistor R9; the drain and the source of the tenth NMOS transistor MN10 are respectively connected to two ends of a resistor R10; the grid electrode of the ninth NMOS transistor MN9 is connected with the grid electrode of a tenth NMOS transistor MN 10;
the drain and the source of the eleventh NMOS transistor MN11 are respectively connected to two ends of a resistor R11; the drain and the source of the twelfth NMOS transistor MN12 are respectively connected to two ends of a resistor R12; the gate of the eleventh NMOS transistor MN11 is connected to the gate of the twelfth NMOS transistor MN 12.
Optionally, the first current mirror includes third to sixth PMOS transistors MP3 to MP6, a third NMOS transistor MN3 and a fourth NMOS transistor MN 4;
the third PMOS transistor MP3 is connected to a fourth PMOS transistor MP4, the fourth PMOS transistor MP4 is connected to a fifth PMOS transistor MP5, the fifth PMOS transistor MP5 is connected to a sixth PMOS transistor MP6, the sixth PMOS transistor MP6 is connected to a third NMOS transistor MN3, the third NMOS transistor MN3 is connected to a low pass filter, and the fourth NMOS transistor MN4 is connected to the other end of the low pass filter.
Optionally, the start-up circuit includes a second current mirror, a current drain, and a delay circuit;
the second current mirror is connected with a current drain, and the current drain is connected with the delay circuit.
Optionally, the second current mirror includes seventh to tenth PMOS transistors MP7 to MP 10; the seventh PMOS transistor MP7 is connected to an eighth PMOS transistor MP8, the eighth PMOS transistor MP8 is connected to a ninth PMOS transistor MP9, and the ninth PMOS transistor MP9 is connected to a tenth PMOS transistor MP 10;
the current drain comprises a thirteenth NMOS transistor MN 13-a fifteenth NMOS transistor MN15, and the delay circuit comprises a resistor R2 and a capacitor C2.
Optionally, the low pass filter includes a resistor R1 and a capacitor C1.
Compared with the prior art, the invention has the beneficial effects that: the voltage-regulating circuit is applied to a DCDC converter chip with double-path output, the voltage drop of a sampling resistor connected in series on a load is detected, the voltage is converted into current on an extraction feedback resistor through a double-path line loss compensation module, so that the output voltage Vout is corrected, the structure is simple, the circuit is suitable for single-path and double-path load application occasions, an external resistor is not needed, and the compensation precision is high.
Drawings
Fig. 1 is a block diagram of a dual-line loss compensation circuit based on a DCDC converter according to an embodiment of the present invention.
Fig. 2 is a specific circuit diagram of a dual-path line loss compensation module according to an embodiment of the present invention.
Detailed Description
In order to explain the technical solution of the present invention in detail, the technical solution of the embodiment of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiment of the present invention. It is to be understood that the embodiments described are only a few embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the invention without any inventive step, are within the scope of protection of the invention.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
For example, a double-line loss compensation circuit based on a DCDC converter is applied to the DCDC converter and comprises a double-line loss compensation module, wherein the input end of the double-line loss compensation module is respectively connected with a sampling resistor Rs1 and a sampling resistor Rs2, the output end of the double-line loss compensation module is connected with a feedback pin VFB, the feedback pin VFB is connected with a feedback resistor R1 and a feedback resistor R2, the other end of the feedback resistor R1 is connected with an equivalent line loss resistor Rcable, the other end of the equivalent line loss resistor Rcable is connected with a sampling resistor Rs1 and a sampling resistor Rs2, and one ends of the sampling resistor Rs1, the sampling resistor Rs2 and the feedback resistor R2 are respectively grounded; the output voltage Vout of the DCDC converter passes through an equivalent line loss resistor Rcable to obtain a load voltage Vload, and the two-way line loss compensation module receives voltage drops on a sampling resistor Rs1 and a sampling resistor Rs2, converts the voltage drops into a current Ic and extracts the current of a feedback resistor R1, so that the output voltage Vout is corrected.
The embodiment is applied to a DCDC converter chip with double-path output, and the voltage drop of the sampling resistor connected in series to the load is detected, and the voltage is converted into the current on the extraction feedback resistor through the double-path line loss compensation module, so that the output voltage Vout is corrected.
In some embodiments, as shown in fig. 1, a two-way line loss compensation circuit based on a DCDC converter is applied to the DCDC converter, and includes a two-way line loss compensation module, an input end of the two-way line loss compensation module is connected to a sampling resistor Rs1 and a sampling resistor Rs2, an output end of the two-way line loss compensation module is connected to a feedback pin VFB, the feedback pin VFB is connected to a feedback resistor R1 and a feedback resistor R2, another end of the feedback resistor R1 is connected to an equivalent line loss resistor Rcable, another end of the equivalent line loss resistor Rcable is connected to a sampling resistor Rs1 and a sampling resistor Rs2, and one ends of the sampling resistor Rs1, the sampling resistor Rs2 and the feedback resistor R2 are grounded, respectively; the output voltage Vout of the DCDC converter passes through an equivalent line loss resistor Rcable to obtain a load voltage Vload, and the two-way line loss compensation module receives voltage drops on a sampling resistor Rs1 and a sampling resistor Rs2, converts the voltage drops into a current Ic and extracts the current of a feedback resistor R1, so that the output voltage Vout is corrected.
Specifically, after converting to the current Ic and drawing the current of the feedback resistor R1, the formula is: vout = (R1+ R2)/R2 × VFB + R1 × Ic, thereby increasing the output voltage Vout, realizing line loss compensation, and stabilizing the load voltage Vload.
In some embodiments, as shown in fig. 2, the two-way line loss compensation module includes a start-up circuit, a trimming circuit, a first current mirror, a low-pass filter, and a summing transconductance amplifier; the starting circuit, the trimming circuit and the first current mirror are respectively connected with the addition transconductance amplifier, and the low-pass filter is connected with the first current mirror.
Specifically, the starting circuit injects current into the nodes VN and VP of the summing transconductance amplifier to activate the summing transconductance amplifier; the trimming circuit is used for correcting the line loss compensation coefficient; a low-frequency pole is introduced into the low-pass filter, so that the bandwidth of a line loss compensation loop is reduced, and the oscillation of the loop is avoided; the summing transconductance amplifier samples the voltage drop of the resistors connected in series with the dual-path load, adds the voltage drop and converts the voltage into the current Ic on the compensation feedback resistor, and the output voltage Vout compensation quantity is R1 × Ic because the current Ic of the KCL is Vout = (R1+ R2)/R2 × VFB + R1 × Ic.
In some embodiments, the summing transconductance amplifier includes a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, and a resistor R3 to a resistor R12; one end of the resistor R3 is connected with the source electrode of the first NMOS transistor MN1 after the resistors R3, R5, R7, R9 and R11 are sequentially connected in series, and one end of the resistor R11 is connected with the drain electrode of the first PMOS transistor MP 1; the drain electrode of the first NMOS transistor MN1 and the drain electrode of the second NMOS transistor MN2 are connected together and then are connected to the first current mirror; one end of the resistor R4, the resistor R6, the resistor R8, the resistor R10 and the resistor R12 are sequentially connected in series, one end of the resistor R4 is connected with the source electrode of the second NMOS transistor MN2, and one end of the resistor R12 is connected with the drain electrode of the second PMOS transistor MP 2; the grid electrode of the first NMOS transistor MN1 and the source electrode of the first PMOS transistor MP1 are respectively connected with a node VN, and the grid electrode of the second NMOS transistor MN2 and the source electrode of the second PMOS transistor MP2 are respectively connected with a node VP; the gate of the first PMOS transistor MP1 is connected to the sampling resistor Rs1, and the gate of the second PMOS transistor MP2 is connected to the sampling resistor Rs 2.
The trimming circuit comprises fifth to twelfth NMOS transistors MN5 to MN12, and resistors R3 to R12; the drain and the source of the fifth NMOS transistor MN5 are respectively connected to two ends of a resistor R5; the drain and the source of the sixth NMOS transistor MN6 are respectively connected to two ends of a resistor R6; the grid electrode of the fifth NMOS transistor MN5 is connected with the grid electrode of a sixth NMOS transistor MN 6; the drain electrode and the source electrode of the seventh NMOS transistor MN7 are respectively connected to two ends of a resistor R7; the drain and the source of the eighth NMOS transistor MN8 are respectively connected to two ends of a resistor R8; the grid electrode of the seventh NMOS transistor MN7 is connected with the grid electrode of the eighth NMOS transistor MN 8; the drain and the source of the ninth NMOS transistor MN9 are respectively connected to two ends of a resistor R9; the drain and the source of the tenth NMOS transistor MN10 are respectively connected to two ends of a resistor R10; the grid electrode of the ninth NMOS transistor MN9 is connected with the grid electrode of a tenth NMOS transistor MN 10; the drain and the source of the eleventh NMOS transistor MN11 are respectively connected to two ends of a resistor R11; the drain and the source of the twelfth NMOS transistor MN12 are respectively connected to two ends of a resistor R12; the gate of the eleventh NMOS transistor MN11 is connected to the gate of the twelfth NMOS transistor MN 12.
The first current mirror comprises third to sixth PMOS tubes MP3 to MP6, a third NMOS tube MN3 and a fourth NMOS tube MN 4; the third PMOS transistor MP3 is connected to a fourth PMOS transistor MP4, the fourth PMOS transistor MP4 is connected to a fifth PMOS transistor MP5, the fifth PMOS transistor MP5 is connected to a sixth PMOS transistor MP6, the sixth PMOS transistor MP6 is connected to a third NMOS transistor MN3, the third NMOS transistor MN3 is connected to a low-pass filter, the gate of the fourth NMOS transistor MN4 is connected to the other end of the low-pass filter, and the drain of the fourth NMOS transistor MN4 is connected to the feedback pin VFB.
The starting circuit comprises a second current mirror, a current drain and a delay circuit; the second current mirror is connected with a current drain, and the current drain is connected with the delay circuit. The second current mirror comprises seventh to tenth PMOS transistors MP7 to MP 10; the seventh PMOS transistor MP7 is connected to an eighth PMOS transistor MP8, the eighth PMOS transistor MP8 is connected to a ninth PMOS transistor MP9, and the ninth PMOS transistor MP9 is connected to a tenth PMOS transistor MP 10; the current drain comprises a thirteenth NMOS transistor MN 13-a fifteenth NMOS transistor MN15, and the delay circuit comprises a resistor R2 and a capacitor C2. The low pass filter includes a resistor R1 and a capacitor C1.
The drain of the ninth PMOS transistor MP9 and the drain of the fourteenth NMOS transistor MN14 are respectively connected to the node VN, and the drain of the tenth PMOS transistor MP10 and the drain of the fifteenth NMOS transistor MN15 are respectively connected to the node VP; the drain electrode and the gate electrode of a thirteenth NMOS tube MN13 are connected with one end of a resistor R2, the gate electrodes of a fourteenth NMOS tube MN14 and a fifteenth NMOS tube MN15 are connected with the other end of a resistor R2, and the source electrodes of the thirteenth NMOS tube MN13, the fourteenth NMOS tube MN14 and the fifteenth NMOS tube MN15 are connected with a capacitor C2; the drain of the third PMOS transistor MP3 is connected to the node VN, and the drain of the fifth PMOS transistor MP5 is connected to the node VP.
In this example, when the system starts to power up, the summing transconductance amplifier nodes VN and VP are both 0V, the first NMOS transistor MN1 and the second NMOS transistor MN2 are both turned off, the currents flowing through the third PMOS transistor MP3 to the sixth PMOS transistor MP6 are both 0uA, the current mirror current formed by the third NMOS transistor MN3 and the fourth NMOS transistor MN4 is 0uA, the compensation current Ic is 0uA, the line loss compensation circuit is in a failed merging point state, the start-up circuit injects currents into the nodes VN and VP to turn on the first NMOS transistor MN1 and the second NMOS transistor MN2, and thus the merging point is eliminated. The summing transconductance amplifier samples the voltage drop of resistors on a series load, namely VCS1= Rs1 XIload 1, VCS2= Rs2 XIload 2, and ensures that the threshold voltage VTHP of a first PMOS tube MP1 and a second PMOS tube MP2 is equal to the threshold voltage VTHN of a first NMOS tube MN1 and a second NMOS tube by reasonably designing W/L, so that VP = VCS2+ VTHPVN = VCS1+ VTH similarly availableN(ii) a The upper end voltage of the resistor R4 is VP-VTHNThe voltage at the upper end of the resistor R3 is VN-VTHNIn this example, the default condition trimming circuits are D3-D0=0111, R3= R4=8R, R5= R6=2R, R7= R8= R, R9= R/2, and R9= R/4, so that the current flowing through the MP9 tube is VCS 9/(R9 + R9) + VCS 9/(R9 + R9) = (VCS 9 + VCS 9)/10R = (9 × Iload 9 + 9 × Iload 9)/10R, thereby obtaining the compensation current I, i.e., the compensation current ICIn addition, when the formula is combined and the node VFB is KCL is calculated by = M × (Rs1 × Iload1+ Rs2 × Iload2)/10R, Vout = (R1+ R2)/R2 × VFB + R1 × Ic, the load compensation amount R1 × Ic = R1 × M × (Rs1 × Iload1+ Rs2 × Iload2)/10R can be obtained. Of the above, VTHPThreshold voltage, VTH, of P-type tubesNThe effective series resistance is R3-R6, Iload is load current and Rs is load current sampling resistance when the threshold voltage of the N-type tube, M is the amplification factor of the current mirror, R is the square resistance value and D3-D0= 0111.
The specific implementation process is that the starting circuit provides injection current for the adding transconductance amplifier through the ninth PMOS tube MP9 and the tenth PMOS tube MP10 of the current mirror, so that the adding transconductance amplifier is free from the failure and merging state, and the VTH is improvedPAnd VTHNMatching precision, introducing current leakage of the same current after a certain delay, and ensuring that the starting circuit has net current inflow to the nodes VN and VPThe flow is 0 uA. The trimming circuit receives the D3-D0 control signals to change the number of effective series resistors and correct line loss compensation coefficients, the consistency of batch production is guaranteed, the default condition D3-D0=0111 is achieved, the effective series resistors are R5 and R6, the range and the precision of the correction coefficients can be improved by expanding the number of control signal bits. The low-pass filter is composed of R1 and C1, so that in order to avoid oscillation of a positive feedback loop introduced by line loss compensation, the bandwidth of the line loss compensation needs to be made very low, and the bandwidth of the line loss compensation is generally 1/10-1/100 of the control bandwidth of the system. The summing transconductance amplifier detects the resistance voltage drop on the series load and converts the resistance voltage drop into the compensation current Ic of the feedback pin VFB, thereby realizing line loss compensation. When the load current Iload1 flows through the sampling resistor Rs1, a sampling voltage VCS1= Iload1 × Rs1 is generated, and similarly, the sampling voltage VCS1= Iload2 × Rs2 of the load2 can be obtained, and the W/L is reasonably designed to ensure that the threshold voltage VTHP of the first PMOS transistor MP1 and the second PMOS transistor MP2 is equal to the threshold voltage VTHN of the first NMOS transistor MN1 and the second NMOS transistor MN2, so that VP = VCS2+ VTHPEqually obtainable, VN = VCS1+ VTHN(ii) a The upper end voltage of the resistor R4 is VP-VTHNThe voltage at the upper end of the resistor R3 is VN-VTHNIn the present example, the default condition trimming circuit is D3-D0=0111, R3= R4=8R, R5= R6=2R, R7= R8= R, R9= R/2, R9= R/4, so the current flowing through the fourth PMOS tube MP9 is VCS 9/(R9 + R9) + VCS 9/(R9 + R9) = (VCS 9 + VCS 9)/10R = (9 × Iload 9 + Rs 9 × Iload 9)/10R, and thus the compensation current I is obtainedCIn addition, when the formula is combined and the node VFB is KCL is calculated by = M × (Rs1 × Iload1+ Rs2 × Iload2)/10R, Vout = (R1+ R2)/R2 × VFB + R1 × Ic, the load compensation amount R1 × Ic = R1 × M × (Rs1 × Iload1+ Rs2 × Iload2)/10R can be obtained.
From the above, the line loss compensation coefficient is related to the sampling resistors Rs1 and Rs2, the first current mirror amplification factor M, the feedback resistor R1 and the trimming resistor, wherein the sampling resistor is related to system application, and in order to reduce loss, the sampling resistor is generally 10M Ω or 20M Ω; the first current mirror amplification factor M is finished in the circuit design stage and is a fixed constant; the feedback resistor R1 is related to system application, generally ranges from 50K omega to 200K omega, and in the fast charging application field, the feedback resistor takes the value of 100K omega; the parameter design of the trimming resistor is flexible, and the range and the precision of a compensation system can be adjusted.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not to be understood as limiting the scope of the present invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the spirit of the invention, which falls within the scope of the invention, and therefore the scope of the invention is to be determined by the appended claims.
Claims (7)
1. The utility model provides a double-circuit line loss compensating circuit based on DCDC converter, is applied to DCDC converter, its characterized in that, includes double-circuit line loss compensation module, double-circuit line loss compensation module's input is connected with sampling resistance Rs1 and sampling resistance Rs2 respectively, and double-circuit line loss compensation module's output is connected with feedback pin VFB, feedback pin VFB is connected with feedback resistance R1 and feedback resistance R2, the other end of feedback resistance R1 is connected with equivalent line loss resistance Rcable, sampling resistance Rs1 and sampling resistance Rs2 are connected to equivalent line loss resistance Rcable's the other end, sampling resistance Rs1, sampling resistance Rs2 and feedback resistance R2's one end ground connection respectively;
the output voltage Vout of the DCDC converter passes through an equivalent line loss resistor Rcable to obtain a load voltage Vload, and a two-way line loss compensation module receives voltage drops on a sampling resistor Rs1 and a sampling resistor Rs2, converts the voltage drops into a current Ic and extracts the current of a feedback resistor R1, so that the output voltage Vout is corrected;
the double-circuit line loss compensation module comprises a starting circuit, a trimming circuit, a first current mirror, a low-pass filter and an addition transconductance amplifier;
the starting circuit, the trimming circuit and the first current mirror are respectively connected with the addition transconductance amplifier, and the low-pass filter is connected with the first current mirror.
2. The dual-line loss compensation circuit based on the DCDC converter of claim 1, wherein the summing transconductance amplifier comprises a first PMOS transistor MP1, a second PMOS transistor MP2, a first NMOS transistor MN1, a second NMOS transistor MN2, and a resistor R3 to a resistor R12;
one end of the resistor R3 is connected with the source electrode of the first NMOS transistor MN1 after the resistors R3, R5, R7, R9 and R11 are sequentially connected in series, and one end of the resistor R11 is connected with the drain electrode of the first PMOS transistor MP 1; the drain electrode of the first NMOS transistor MN1 and the drain electrode of the second NMOS transistor MN2 are connected together and then are connected to the first current mirror;
one end of the resistor R4, the resistor R6, the resistor R8, the resistor R10 and the resistor R12 are sequentially connected in series, one end of the resistor R4 is connected with the source electrode of the second NMOS transistor MN2, and one end of the resistor R12 is connected with the drain electrode of the second PMOS transistor MP 2;
the grid electrode of the first NMOS transistor MN1 and the source electrode of the first PMOS transistor MP1 are respectively connected with a node VN, and the grid electrode of the second NMOS transistor MN2 and the source electrode of the second PMOS transistor MP2 are respectively connected with a node VP;
the gate of the first PMOS transistor MP1 is connected to the sampling resistor Rs1, and the gate of the second PMOS transistor MP2 is connected to the sampling resistor Rs 2.
3. The DCDC converter-based dual line loss compensation circuit of claim 2, wherein the trimming circuit comprises a fifth NMOS transistor MN5 to a twelfth NMOS transistor MN12, a resistor R3 to a resistor R12;
the drain and the source of the fifth NMOS transistor MN5 are respectively connected to two ends of a resistor R5; the drain and the source of the sixth NMOS transistor MN6 are respectively connected to two ends of a resistor R6; the grid electrode of the fifth NMOS transistor MN5 is connected with the grid electrode of a sixth NMOS transistor MN 6;
the drain electrode and the source electrode of the seventh NMOS transistor MN7 are respectively connected to two ends of a resistor R7; the drain and the source of the eighth NMOS transistor MN8 are respectively connected to two ends of a resistor R8; the grid electrode of the seventh NMOS transistor MN7 is connected with the grid electrode of the eighth NMOS transistor MN 8;
the drain and the source of the ninth NMOS transistor MN9 are respectively connected to two ends of a resistor R9; the drain and the source of the tenth NMOS transistor MN10 are respectively connected to two ends of a resistor R10; the grid electrode of the ninth NMOS transistor MN9 is connected with the grid electrode of a tenth NMOS transistor MN 10;
the drain and the source of the eleventh NMOS transistor MN11 are respectively connected to two ends of a resistor R11; the drain and the source of the twelfth NMOS transistor MN12 are respectively connected to two ends of a resistor R12; the gate of the eleventh NMOS transistor MN11 is connected to the gate of the twelfth NMOS transistor MN 12.
4. The DCDC converter-based dual line loss compensation circuit of claim 1, wherein the first current mirror comprises a third PMOS transistor MP3 to a sixth PMOS transistor MP6, a third NMOS transistor MN3 and a fourth NMOS transistor MN 4;
the third PMOS transistor MP3 is connected to a fourth PMOS transistor MP4, the fourth PMOS transistor MP4 is connected to a fifth PMOS transistor MP5, the fifth PMOS transistor MP5 is connected to a sixth PMOS transistor MP6, the sixth PMOS transistor MP6 is connected to a third NMOS transistor MN3, the third NMOS transistor MN3 is connected to a low pass filter, and the fourth NMOS transistor MN4 is connected to the other end of the low pass filter.
5. The DCDC converter-based two-way line loss compensation circuit of claim 1, wherein the start-up circuit comprises a second current mirror, a current drain, and a delay circuit;
the second current mirror is connected with a current drain, and the current drain is connected with the delay circuit.
6. The DCDC converter-based two-way line loss compensation circuit of claim 5, wherein the second current mirror comprises a seventh PMOS transistor MP7 through a tenth PMOS transistor MP 10; the seventh PMOS transistor MP7 is connected to an eighth PMOS transistor MP8, the eighth PMOS transistor MP8 is connected to a ninth PMOS transistor MP9, and the ninth PMOS transistor MP9 is connected to a tenth PMOS transistor MP 10;
the current drain comprises a thirteenth NMOS transistor MN 13-a fifteenth NMOS transistor MN15, and the delay circuit comprises a resistor R2 and a capacitor C2.
7. The DCDC converter-based two-wire loss compensation circuit of claim 1, wherein the low pass filter comprises a resistor R1 and a capacitor C1.
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