CN105573396B - A kind of low differential voltage linear voltage stabilizer circuit - Google Patents

Abstract

The application discloses a low-dropout linear voltage regulator circuit, which includes an error amplifier, an adjustment tube, a frequency compensation circuit and a feedback circuit. The frequency compensation circuit includes two compensation capacitors. The input end of the frequency compensation circuit is connected to the output end of the error amplifier. The output end of the frequency compensation circuit is connected to the output end of the low dropout linear regulator circuit. It can be seen that the frequency compensation of the low-dropout linear regulator circuit adopts dual-capacitor compensation, the output pole of the error amplifier is amplified by two compensation capacitors, and the output node becomes the dominant pole of the entire circuit and is at a higher frequency, so that the load changes The influence on the position of the output pole can be ignored, thereby improving the stability of the LDO circuit without an off-chip capacitor.

Description

A low dropout linear regulator circuit

technical field

The invention relates to the technical field of switching voltage converters, and more specifically relates to a low-dropout linear regulator circuit.

Background technique

A Low Dropout Regulator (LDO) is a linear voltage regulator whose basic function is to ensure a stable output voltage within a certain range of input voltage variation and load variation. As an important part of the power management chip, LDO has the advantages of wide input voltage range, no output voltage ripple and low noise, simple structure, low power consumption and low production cost, and is widely used in portable products, computers, home appliances, Various occasions such as automotive electronic products.

Traditional LDO circuits all belong to the structure with off-chip capacitors. The off-chip capacitors can not only reduce the voltage change caused by the transient change of the load current, but also use it and the equivalent series resistance to compensate the system loop where it is located. Maintain system stability. However, with the continuous improvement of the integration of electronic products, especially portable electronic devices that have strict requirements on area and power consumption, the application range of LDOs with off-chip capacitors is increasingly restricted. Therefore, the LDO with no off-chip capacitor structure has become a research hotspot of LDO.

The output capacitance of a traditional LDO circuit is on the order of microfarads, so the main pole is generally located at the output of the LDO circuit, while the output capacitance of the LDO circuit without off-chip capacitors is only on the order of picofarads, so its main pole is usually located at the output of the error amplifier. Therefore, the position of the output pole of the LDO circuit without an off-chip capacitor is determined by the load. Since the load varies in a large range, it has a great impact on the stability of the LDO circuit without an off-chip capacitor.

To sum up, how to provide a highly stable LDO circuit without off-chip capacitors is a technical problem to be solved urgently by those skilled in the art.

Contents of the invention

In view of this, the present invention provides a low-dropout linear regulator circuit to improve the stability of LDO circuits without external capacitors.

A low-dropout linear regulator circuit, comprising: an error amplifier, a regulator tube, a frequency compensation circuit and a feedback circuit, wherein the frequency compensation circuit includes two compensation capacitors;

The inverting input terminal of the error amplifier is connected to the reference voltage source, the output terminal of the error amplifier is connected to the control terminal of the adjustment transistor, and the output end of the adjustment transistor is connected to the error amplifier through the feedback circuit. positive phase input;

The input end of the adjustment tube is connected to the power supply, the common end of the adjustment tube and the feedback circuit is connected to the output end of the frequency compensation circuit as the output end of the low dropout linear voltage regulator circuit, and the frequency compensation circuit The input terminal of the error amplifier is connected to the output terminal of the error amplifier;

The error amplifier compares the feedback voltage output by the feedback circuit with the reference voltage to generate an error signal, and adjusts the adjusting tube by amplifying the error signal, and the frequency compensation circuit adjusts the frequency of the entire circuit. compensate.

Preferably, the error amplifier includes: a first switch tube, a second switch tube, a third switch tube, a fourth switch tube, a fifth switch tube, a sixth switch tube, a seventh switch tube, an eighth switch tube, a Nine switching tubes, tenth switching tubes and eleventh switching tubes;

The input terminal of the eleventh switching tube is connected to the power supply, the control terminal of the eleventh switching tube is connected to the first bias voltage, and the output terminals of the eleventh switching tube are respectively connected to the first switch the input end of the tube and the input end of the second switching tube;

The control terminal of the first switching tube is connected to the feedback circuit as the non-inverting input terminal of the error amplifier, and the control terminal of the second switching tube is connected to the reference voltage source as the inverting input terminal of the error amplifier;

The input end of the ninth switch tube and the input end of the tenth switch tube are both connected to the power supply, and the control terminal of the ninth switch tube is connected to the control end of the tenth switch tube;

The input terminal of the seventh switching tube is connected to the output terminal of the ninth switching tube, the output terminal of the seventh switching tube is connected to the control terminal of the ninth switching tube, and the control terminal of the seventh switching tube is connected to and the control terminal of the eighth switch tube, and the common terminal of the two control terminals is connected to the second bias voltage, and the input terminal of the eighth switch tube is connected to the output terminal of the tenth switch tube;

The input terminal of the fifth switching tube is connected to the output terminal of the seventh switching tube, the control terminal of the fifth switching tube is connected to the control terminal of the sixth switching tube, and the common terminal of the two control terminals is connected to the third bias Set the voltage, the input terminal of the sixth switch tube is connected to the output terminal of the eighth switch tube, wherein the common terminal of the sixth switch tube and the eighth switch tube is used as the output terminal of the error amplifier;

The input end of the third switching tube is connected to the output end of the fifth switching tube, and the input end of the third switching tube is connected to the output end of the first switching tube, and the output end of the third switching tube connected to the ground terminal, the control terminal of the third switch tube is connected to the control terminal of the fourth switch tube and the common terminal of the two control terminals is connected to the fourth bias voltage, and the input terminal of the fourth switch tube is connected to the first The output terminals of the six switching tubes, and the input terminal of the fourth switching tube is connected to the output terminal of the second switching tube, and the output terminal of the fourth switching tube is connected to the ground terminal.

preferred,

The first switch tube, the second switch tube, the seventh switch tube, the eighth switch tube, the ninth switch tube, the tenth switch tube, and the eleventh switch tube are PMOS tube;

The third switch transistor, the fourth switch transistor, the fifth switch transistor and the sixth switch transistor are NMOS transistors.

Preferably, the two compensation capacitors are respectively a first compensation capacitor and a second compensation capacitor;

The positive plate of the first compensation capacitor is connected to the common terminal of the sixth switching tube and the eighth switching tube, and the negative plate of the first compensation capacitor is connected to the common terminal of the adjusting tube and the feedback circuit;

The positive plate of the second compensation capacitor is connected to the common terminal of the sixth switch transistor and the fourth switch transistor, and the negative plate of the second compensation capacitor is connected to the negative plate of the first compensation capacitor.

Preferably, it also includes: a buffer;

The input end of the buffer is connected to the output end of the error amplifier, and the output end of the buffer is connected to the control end of the adjustment tube, and the buffer is used to improve the Adjust the slew rate of the control end of the tube.

Preferably, the buffer includes: a twelfth switch tube, a thirteenth switch tube, a fourteenth switch tube, a fifteenth switch tube, a sixteenth switch tube, and a seventeenth switch tube;

The input end of the twelfth switch tube and the input end of the thirteenth switch tube are both connected to the power supply, and the control end of the twelfth switch tube is connected to the error amplifier as the input end of the buffer. output terminal, the output terminal of the twelfth switching tube is connected to the output terminal of the thirteenth switching tube, and both are connected to the ground terminal, and the control terminal of the thirteenth switching tube is connected to the thirteenth switching tube the output terminal;

The input terminal of the fourteenth switch tube is connected to the power supply, the control terminal of the fourteenth switch tube is connected to the output terminal of the error amplifier,

The input end of the fifteenth switch tube is connected to the power supply, the control end of the fifteenth switch tube is connected to the output end of the thirteenth switch tube, and the output end of the fifteenth switch tube is connected to the the control end of the adjustment tube;

The input terminal of the sixteenth switch tube is connected to the output terminal of the fourteenth switch tube, the output terminal of the sixteenth switch tube is connected to the ground terminal, and the control terminal of the sixteenth switch tube is respectively connected to the The input terminal of the sixteenth switch tube is connected to the control terminal of the seventeenth switch tube;

The input end of the seventeenth switch transistor is connected to the output end of the fifteenth switch transistor, and the output end of the seventeenth switch transistor is connected to a ground terminal.

preferred,

The twelfth switch tube, the thirteenth switch tube, the fourteenth switch tube, and the fifteenth switch tube are PMOS tubes;

The sixteenth switch transistor and the seventeenth switch transistor are NMOS transistors.

Preferably, the feedback circuit includes: a first resistor and a second resistor;

One end of the first resistor is connected to the output end of the adjustment tube, the other end of the first resistor is connected to the ground terminal through the second resistor, and the common end of the first resistor and the second resistor is used as a feedback The output end of the resistor is connected to the non-inverting input end of the error amplifier.

Preferably, it also includes: a filter circuit;

The input terminal of the filter circuit is connected to the output terminal of the low dropout linear regulator circuit, and the output terminal of the filter circuit is connected to the ground terminal.

Preferably, the filter circuit includes: a filter resistor and a filter capacitor;

One end of the filter resistor is connected to the output end of the low dropout linear voltage regulator circuit, and the other end of the filter resistor is connected to the ground terminal;

The positive plate of the filter capacitor is connected to the output terminal of the low dropout linear voltage regulator circuit, and the negative plate of the filter capacitor is connected to the ground terminal.

It can be seen from the above technical solution that the present invention provides a low-dropout linear voltage regulator circuit, including an error amplifier, a regulator tube, a frequency compensation circuit and a feedback circuit, the frequency compensation circuit includes two compensation capacitors, and the frequency compensation circuit The input terminal is connected to the output terminal of the error amplifier, and the output terminal of the frequency compensation circuit is connected to the output terminal of the low-dropout linear regulator circuit. It can be seen that the frequency compensation of the low-dropout linear regulator circuit adopts dual-capacitor compensation, the output pole of the error amplifier is amplified by two compensation capacitors, and the output node becomes the dominant pole of the entire circuit and is at a higher frequency, so that the load changes The influence on the position of the output pole can be ignored, thereby improving the stability of the LDO circuit without an off-chip capacitor.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only It is an embodiment of the present invention, and those skilled in the art can also obtain other drawings according to the provided drawings without creative work.

Fig. 1 is the circuit diagram of a kind of low-dropout linear regulator circuit disclosed by the embodiment of the present invention;

FIG. 2 is a circuit diagram of another low-dropout linear regulator circuit disclosed in an embodiment of the present invention;

3 is a circuit diagram of another low-dropout linear regulator circuit disclosed in an embodiment of the present invention;

FIG. 4 is a circuit diagram of a small signal model of a low dropout linear voltage regulator circuit disclosed by an embodiment of the present invention.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The embodiment of the invention discloses a low-dropout linear regulator circuit to improve the stability of an LDO circuit without an external capacitor.

Referring to FIG. 1 , a circuit diagram of a low-dropout linear voltage regulator circuit provided by an embodiment of the present invention includes: an error amplifier EA, an adjustment transistor M _p , a frequency compensation circuit 11 and a feedback circuit 12, wherein the frequency compensation circuit 11 includes two a compensation capacitor;

in:

The inverting input terminal of the error amplifier EA is connected to the reference voltage source, the output terminal of the error amplifier EA is connected to the control terminal of the adjusting transistor _Mp , and the output terminal of the adjusting transistor _Mp is connected to the non-inverting input terminal of the error amplifier EA through the feedback circuit 12 ;

The input terminal of the adjustment tube M _p is connected to the power supply VDD, and the common terminal of the adjustment tube M _p and the feedback circuit 12 is used as the output terminal V _out of the low dropout linear regulator (Low Dropout Regulator, LDO) circuit and the output of the frequency compensation circuit 11 The input terminal of the frequency compensation circuit 11 is connected to the output terminal of the error amplifier EA.

Those skilled in the art can understand that the two compensation capacitors in the frequency compensation circuit 11 can amplify the output pole of the error amplifier EA.

The working principle of the low dropout linear regulator circuit is as follows:

After the power supply voltage is powered on, the reference voltage source generates a reference voltage V _ref of a system close to zero temperature and acts on the inverting input terminal of the error amplifier EA, and the error amplifier EA, the adjustment transistor M _p and the feedback circuit 12 constitute a stable Negative feedback loop, the error amplifier EA compares the feedback voltage output by the feedback circuit 12 with the reference voltage V _ref to generate an error signal, and adjusts the adjustment tube _Mp by amplifying the error signal, and the frequency compensation circuit 11 controls The whole circuit performs frequency compensation, so that the whole circuit has a stable output voltage.

In summary, it can be seen that the frequency compensation of the low-dropout linear regulator circuit provided by the present invention adopts dual-capacitor compensation, the output pole of the error amplifier EA is amplified by two compensation capacitors, and the output node becomes the main pole of the entire circuit, and is in a relatively high position. At high frequencies, the impact of load changes on the output pole position can be ignored, thereby improving the stability of LDO circuits without off-chip capacitors.

In order to further optimize the above embodiment, refer to FIG. 2 , which is a circuit diagram of a low-dropout linear regulator circuit disclosed in another embodiment of the present invention. On the basis of the embodiment shown in FIG. 1 , it also includes: a buffer 13;

The input terminal of the buffer 13 is connected to the output terminal of the error amplifier EA, and the output terminal of the buffer 13 is connected to the control terminal of the adjustment transistor _Mp . The buffer 13 is used to improve the performance of the adjustment transistor _Mp when the quiescent current is lower than a preset value. The slew rate of the control terminal.

In order to further optimize the above embodiment, it also includes: a filtering circuit 14;

The input terminal of the filter circuit 14 is connected to the output terminal V _out of the low dropout linear voltage regulator circuit, the output terminal of the filter circuit 14 is connected to the ground terminal, and the filter circuit 14 is used for filtering the output voltage of the low dropout linear voltage regulator circuit.

Wherein, the filter circuit 14 includes a filter resistor _RL and a filter capacitor _CL ;

One end of the filter resistor _RL is connected to the output terminal V _out of the LDO circuit, and the other end of the filter resistor _RL is connected to the ground terminal;

The positive plate of the filter capacitor _CL is connected to the output terminal V _out of the LDO circuit, and the negative plate of the filter capacitor _CL is connected to the ground terminal.

Since the function of the error amplifier EA is to compare the feedback voltage with the reference voltage V _ref to generate an error signal, the adjustment tube M _p is adjusted by amplifying the error signal, and finally the output voltage of the entire circuit is stabilized. Therefore, the error amplifier The performance of the EA directly affects various performance parameters of the entire circuit, such as load regulation and linear regulation. In order to achieve very low load and linear regulation, the error amplifier EA is usually required to have a high gain. Therefore, the error amplifier EA generally adopts a folded cascode amplifier or a two-stage operational amplifier structure. Because the two-stage operational amplifier will generate two poles, it is necessary to design a compensation circuit to generate a zero point to offset a pole point, which undoubtedly increases the difficulty of designing the compensation network of the entire circuit. At the same time, because the folded cascode amplifier has the advantages of a single-stage operational amplifier that can reduce the influence of poles and zeros on the loop, thereby reducing the difficulty of compensation, the folded cascode amplifier can also provide greater gain and higher Large loop bandwidth. Therefore, the present invention uses a folded cascode amplifier as the error amplifier EA.

Referring to FIG. 3 , the circuit diagram of the low dropout linear voltage regulator circuit provided by the embodiment of the present invention, the error amplifier EA includes: a first switching tube M ₁ , a second switching tube M ₂ , a third switching tube M ₃ , and a fourth switching tube M ₄ , fifth switching tube M ₅ , sixth switching tube M ₆ , seventh switching tube M ₇ , eighth switching tube M ₈ , ninth switching tube M ₉ , tenth switching tube M ₁₀ and eleventh switching tube M ₁₁ ;

in:

The input terminal of the eleventh switching tube M ₁₁ is connected to the power supply VDD, the control terminal of the eleventh switching tube M ₁₁ is connected to the first bias voltage V _b0 , and the output terminal of the eleventh switching tube M ₁₁ respectively connecting the input end of the _first switching tube M1 and the input end of the _second switching tube M2;

The control terminal of the _first switching tube M1 is used as the non-inverting input terminal of the error amplifier EA to connect to the feedback circuit 12 (the feedback voltage is V _fb ), and the control terminal of the _second switching tube M2 is used as the error amplifier The inverting input terminal of EA is connected to the reference voltage source (the reference voltage is V _REF );

The input terminal of the _ninth switching tube M9 and the input terminal of the _tenth switching tube M10 are both connected to the power supply VDD, and the control terminal of the _ninth switching tube M9 and the tenth switching tube M ₁₀ control terminal connection;

The input terminal of the _seventh switching tube M7 is connected to the output terminal of the _ninth switching tube M9, the output terminal of the _seventh switching tube M7 is connected to the control terminal of the _ninth switching tube M9, and the The control terminal of the _seventh switch tube M7 is connected to the control terminal of the _eighth switch tube M8 and the common terminal of the two control terminals is connected to the second bias voltage V _b1 , and the input terminal of the _eighth switch tube M8 is connected to The output end of the _tenth switching tube M10;

The input terminal of the _fifth switching tube M5 is connected to the output terminal of the _seventh switching tube M7, the control terminal of the _fifth switching tube M5 is connected to the control terminal of the _sixth switching tube M6, and the two The common terminal of the control terminal is connected to the third bias voltage V _b3 , and the input terminal of the _sixth switching transistor M6 is connected to the output terminal of the _eighth switching transistor M8, wherein the sixth switching transistor _M6 and the The common terminal of the _eighth switch tube M8 serves as the output terminal of the error amplifier EA;

The input terminal of the third switching tube M3 is connected to the output terminal of the _fifth switching tube M5, and the input terminal of the _third switching tube M3 is connected to the output terminal _of the _first switching tube M1, so The output terminal of the _third switching tube M3 is connected to the ground terminal GND, the control terminal of the _third switching tube M3 is connected to the control terminal of the _fourth switching tube M4, and the common terminal of the two control terminals is connected to the fourth bias voltage V _b2 , the input end of the _fourth switch M4 is connected to the output end of the _sixth switch M6, and the input end of the _fourth switch M4 is connected to the second switch _M2 The output terminal, the output terminal of the _fourth switching transistor M4 is connected to the ground terminal GND.

It should be noted that, in the error amplifier EA, the first switch M ₁ , the second switch M ₂ , the seventh switch M ₇ , the eighth switch M ₈ , the ninth switch The switch tube M ₉ , the tenth switch tube M ₁₀ and the eleventh switch tube M ₁₁ are PMOS tubes;

The third switching tube M ₃ , the fourth switching tube M ₄ , the fifth switching tube M ₅ and the sixth switching tube M ₆ are NMOS tubes.

It can be seen from the figure that the input pair tube of the error amplifier EA is a PMOS tube, so that the error amplifier EA can still work normally when the input voltage is low, VDD is the soft-start control voltage, and there are three biases in the sleeve structure The voltage provides the DC bias point for the op amp.

For the error amplifier EA, it is necessary to analyze its DC and AC characteristics.

(1) DC characteristics: including input voltage range, input common mode level, output voltage swing, quiescent current, etc. The input voltage range of the error amplifier EA designed by the present invention is 0～(VDD-|V _DS11 |-|V _GS1 |), and the error amplifier EA can work normally when the input voltage is as low as 0V, wherein V _DS11 is the tenth The drain-source voltage of the first switch _M11 , V _GS1 is the gate-source voltage of the _first switch M1.

The range of the output voltage of the error amplifier EA is (V _DS5 +V _DS3 )～(VDD-|V _GS9 |), wherein, V _DS5 is the drain-source voltage of the _fifth switching tube M5, and V _DS3 is the third switching tube M ₃ , V _GS9 is the gate-source voltage of the _ninth switching transistor M9. Therefore, the error amplifier EA provided by the present invention has a wider output voltage swing.

(2) AC characteristics: including open-loop gain, phase margin, unity gain bandwidth, power supply rejection ratio, etc.

Assume that the two compensation capacitors in the frequency compensation circuit 11 are respectively a first compensation capacitor C ₃ and a second compensation capacitor C ₄ ;

Referring to FIG. ₃ , the positive plate of the first compensation capacitor C3 is connected to the common terminal of the sixth switching transistor _M6 and the _eighth switching transistor M8, and the negative plate _of the first compensation capacitor C3 is connected to the adjustment transistor _Mp and the The common end of the feedback circuit 12;

The positive plate of the second compensation capacitor _C4 is connected to the common terminal of the sixth switch _M6 and the _fourth switch M4, and the negative plate of the second compensation capacitor _C4 is connected to the negative plate _of the first compensation capacitor C3 .

It should be noted that the output pole of the buffer 13 in the present invention adopts a push-pull stage structure, so that under an extremely low quiescent current, the slew rate of the control terminal of the pass transistor M _p can be greatly improved, thereby improving the transient response.

Referring to FIG. 3 , the buffer 13 includes: a twelfth switching tube M ₁₂ , a thirteenth switching tube M ₁₃ , a fourteenth switching tube M ₁₄ , a fifteenth switching tube M ₁₅ , a sixteenth switching tube M ₁₆ and a Seventeen switching tubes M ₁₇ ;

in:

The input end of the _twelfth switching tube M12 and the input end of the _thirteenth switching tube M13 are both connected to the power supply VDD, and the control terminal of the _twelfth switching tube M12 is used as the buffer 13 The input terminal is connected to the output terminal of the error amplifier EA (that is, the common terminal of the sixth switching tube _M6 and the _eighth switching tube M8), and the output terminal of the _twelfth switching tube M12 is connected to the tenth switching tube M12. The output terminals of the three switch tubes _M13 are connected, and all are connected to the ground terminal GND, and the control terminal of the _thirteenth switch tube M13 is connected to the output terminal of the _thirteenth switch tube M13;

The input terminal of the _fourteenth switching tube M14 is connected to the power supply VDD, the control terminal of the _fourteenth switching tube M14 is connected to the output terminal of the error amplifier EA,

The input terminal of the _fifteenth switching tube M15 is connected to the power supply VDD, the control terminal of the _fifteenth switching tube M15 is connected to the output terminal of the _thirteenth switching tube M13, and the fifteenth switching tube M15 is connected to the output terminal of the thirteenth switching tube M13. The output terminal of the switching tube _M15 is connected to the control terminal of the adjusting tube _Mp ;

The input terminal of the _sixteenth switch tube M16 is connected to the output terminal of the _fourteenth switch tube M14, the output terminal of the _sixteenth switch tube M16 is connected to the ground terminal GND, and the sixteenth switch tube M16 is connected to the ground terminal GND. The control terminal of M16 is respectively connected to the input terminal of the _sixteenth switch tube _M16 and the control terminal of the _seventeenth switch tube M17;

The input end of the _seventeenth switching transistor M17 is connected to the output end of the _fifteenth switching transistor M15, and the output end of the _seventeenth switching transistor M17 is connected to the ground terminal GND.

It should be noted that, in the buffer 13, the twelfth switch tube M ₁₂ , the thirteenth switch tube M ₁₃ , the fourteenth switch tube M ₁₄ and the fifteenth switch tube M ₁₅ are PMOS tube;

The _sixteenth switching transistor M16 and the _seventeenth switching transistor M17 are NMOS transistors.

It should be noted that the feedback circuit 12 includes: a first resistor R _f1 and a second resistor R _f2 (see FIG. 3 );

One end of the first resistor R _f1 is connected to the output end of the adjustment transistor _Mp , the other end of the first resistor R _f1 is connected to the ground terminal GND through the second resistor R _f2 , and the common end of the first resistor R _f1 and the second resistor R _f2 is used as The output end of the feedback circuit 12 is connected to the non-inverting input end of the error amplifier EA.

In order to further illustrate that the low-dropout linear voltage regulator circuit provided by the present invention can make the influence of the load change on the position of the output pole negligible, the present invention is also described from the perspective of the transfer function of the system.

Referring to FIG. 4 , it is a circuit diagram of a small-signal model of a low-dropout linear regulator circuit provided by an embodiment of the present invention. By analyzing and calculating the model, its transfer function can be obtained.

where _gm1 represents the input transconductance of the error amplifier, R1 represents the equivalent output impedance of the error amplifier, _C1 represents the equivalent output capacitance of the error amplifier, _gm2 represents the input _{transconductance} of the buffer, and _R2 represents the buffer’s Equivalent output impedance, C ₂ represents the equivalent output capacitance of the buffer, g _m3 represents the input transconductance of the adjustment tube, R _eq represents the equivalent impedance of the LDO overall circuit output V _out , C _L represents the LDO overall circuit output V The equivalent output capacitance of _out , g _m6 represents the input transconductance of the _sixth switching tube M6, V _IN represents the voltage of the error amplifier, g _m1 V _IN represents the equivalent current of the error amplifier, V _I represents the voltage of the buffer, g _m2 V _I represents the equivalent current of the buffer, V ₂ represents the voltage of the buffer, g _m3 V ₂ represents the equivalent current of the adjustment tube, C ₃ represents the first compensation capacitor, C ₄ represents the second compensation capacitor; (1)

The transfer function H(s) of the system is:

a ₁ , a ₂ , a ₃ and a ₄ in formula (1) are respectively:

a ₁ = g _m2 g _m3 R ₁ R ₂ R _eq (C ₃ +C ₄ ) (2);

a ₃ ≈ R ₁ R ₂ R _eq C ₂ C ₃ C _L (4);

According to formula (4), the poles P ₁ ~ P ₄ and zero points Z ₁ ~ Z ₃ are respectively:

There are four poles P ₁ -P ₄ and three zeros Z ₁ -Z ₃ in the LDO. Since the capacitance at the output of the error amplifier EA is amplified by g _m2 g _m3 R ₁ R ₂ R _eq (C ₃ +C ₄ ), the pole P ₁ at the output of the error amplifier EA becomes the dominant pole of the entire circuit. Since the input transconductance g _m6 of the _sixth switching tube M6 is very small, the pole P2 generated by the output terminal of the _sixth switching tube M6 is a high _- frequency pole, which has no great influence on the stability of the LDO.

The pole _P3 generated at the output of the buffer cancels each other out due to the pole _- zero Z2 pair with the zero, so that the influence on the stability of the LDO is negligible. _The value of the pole P4 at the LDO output is amplified by a factor of _{g m2} R2, so the pole P4 at the _LDO output is also at a higher frequency, and the zero _Z3 is also at a very high frequency, so all pole and zero pairs The effect on the stability of the LDO is negligible.

In summary, it can be seen that the frequency compensation of the low-dropout linear regulator circuit provided by the present invention adopts dual-capacitor compensation, the output pole of the error amplifier EA is amplified by two compensation capacitors, and the output node becomes the main pole of the entire circuit, and is in a relatively high position. At high frequencies, the impact of load changes on the output pole position can be ignored, thereby improving the stability of LDO circuits without off-chip capacitors.

At the same time, the output pole of the buffer 13 adopts a push-pull stage structure, so that under an extremely low quiescent current, the slew rate of the control terminal of the pass transistor M _p can be greatly improved, thereby improving the transient response.

Finally, the low-dropout linear voltage regulator circuit provided by the present invention has no external capacitors, thereby improving the integration level of the power management chip.

Finally, it should also be noted that in this text, relational terms such as first and second etc. are only used to distinguish one entity or operation from another, and do not necessarily require or imply that these entities or operations, any such actual relationship or order exists. Furthermore, the term "comprises", "comprises" or any other variation thereof is intended to cover a non-exclusive inclusion such that a process, method, article, or apparatus comprising a set of elements includes not only those elements, but also includes elements not expressly listed. other elements of or also include elements inherent in such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.

Each embodiment in this specification is described in a progressive manner, each embodiment focuses on the difference from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (8)

1. a kind of low differential voltage linear voltage stabilizer circuit, it is characterised in that including：Error amplifier, adjustment pipe, frequency compensated circuit And feedback circuit, wherein, the frequency compensated circuit includes two compensation capacitors；

The inverting input of the error amplifier is connected with reference voltage source, and the output end of the error amplifier is adjusted with described The control end connection of homogeneous tube, the positive that the output end of the adjustment pipe connects the error amplifier by the feedback circuit is defeated Enter end；

The input connection power supply of the adjustment pipe, the common port of the adjustment pipe and the feedback circuit is used as low voltage difference The output end of linear regulator circuit is connected with the output end of the frequency compensated circuit, the input of the frequency compensated circuit Connect the output end of the error amplifier；

The feedback voltage that the error amplifier exports the feedback circuit is compared generation error signal with reference voltage, The adjustment pipe is adjusted by being amplified to the error signal, and by the frequency compensated circuit to whole circuit Carry out frequency compensation；

Wherein, the error amplifier includes：First switch pipe, second switch pipe, the 3rd switching tube, the 4th switching tube, the 5th Switching tube, the 6th switching tube, the 7th switching tube, the 8th switching tube, the 9th switching tube, the tenth switching tube and the 11st switching tube；

The input of 11st switching tube connects the power supply, the control end connection first of the 11st switching tube Bias voltage, the output end of the 11st switching tube connects the input and the second switch of the first switch pipe respectively The input of pipe；

The control end of the first switch pipe connects the feedback circuit, described second as the normal phase input end of error amplifier The control end of switching tube connects the reference voltage source as the inverting input of the error amplifier；

The input of 9th switching tube and the input of the tenth switching tube are all connected with the power supply, the described 9th The control end of switching tube and the connection of the control end of the tenth switching tube；

The input of 7th switching tube connects the output end of the 9th switching tube, and the output end of the 7th switching tube connects The control end of the 9th switching tube is connect, the control end of the 7th switching tube connects the control end and two of the 8th switching tube The common port of individual control end connects the second bias voltage, and the input of the 8th switching tube connects the defeated of the tenth switching tube Go out end；

The input of 5th switching tube connects the output end of the 7th switching tube, and the control end of the 5th switching tube connects The common port of the control end and two control ends that connect the 6th switching tube connects the 3rd bias voltage, the 6th switching tube Input connects the output end of the 8th switching tube, wherein, the common port of the 6th switching tube and the 8th switching tube It is used as the output end of the error amplifier；

The input of 3rd switching tube connects the output end of the 5th switching tube, and the input of the 3rd switching tube The output end of the first switch pipe is connected, the output end of the 3rd switching tube connects earth terminal, the 3rd switching tube Control end connects the control end of the 4th switching tube and the common port of two control ends connects the 4th bias voltage, the described 4th The input of switching tube connects the output end of the 6th switching tube, and the input connection described second of the 4th switching tube The output end of switching tube, the output end connection earth terminal of the 4th switching tube；

Two compensation capacitors are respectively the first compensation capacitor and the second compensation capacitor；

The positive plate of first compensation capacitor connects the common port of the 6th switching tube and the 8th switching tube, described The negative plate connection adjustment pipe and the common port of the feedback circuit of first compensation capacitor；

The positive plate of second compensation capacitor connects the common port of the 6th switching tube and the 4th switching tube, described The negative plate of second compensation capacitor connects the negative plate of first compensation capacitor.

2. low differential voltage linear voltage stabilizer circuit according to claim 1, it is characterised in that

The first switch pipe, the second switch pipe, the 7th switching tube, the 8th switching tube, the 9th switch Pipe, the tenth switching tube and the 11st switching tube are PMOS；

3rd switching tube, the 4th switching tube, the 5th switching tube and the 6th switching tube are NMOS tube.

3. low differential voltage linear voltage stabilizer circuit according to claim 1, it is characterised in that also include：Buffer；

The input of the buffer connects the output end of the error amplifier, and the output end connection of the buffer is described to adjust The control end of homogeneous tube, the buffer is used to improve the pendulum of the control end of the adjustment pipe when quiescent current is less than preset value Rate.

4. low differential voltage linear voltage stabilizer circuit according to claim 3, it is characterised in that the buffer includes：Tenth Two switching tubes, the 13rd switching tube, the 14th switching tube, the 15th switching tube, sixteenmo close pipe and the 17th switching tube；

The input of 12nd switching tube and the input of the 13rd switching tube are all connected with the power supply, described The control end of 12nd switching tube connects the output end of the error amplifier as the input of buffer, and the described 12nd opens The output end for closing pipe is connected with the output end of the 13rd switching tube, and the control end of the 13rd switching tube connects described the The output end of 13 switching tubes；

The input of 14th switching tube connects the power supply, and the control end connection of the 14th switching tube is described The output end of error amplifier,

The input of 15th switching tube connects the power supply, and the control end connection of the 15th switching tube is described The output end of 13rd switching tube, the control end of the output end connection adjustment pipe of the 15th switching tube；

The sixteenmo closes the output end of input connection the 14th switching tube of pipe, and the sixteenmo closes the defeated of pipe Go out end connection earth terminal, the control end that the sixteenmo closes pipe closes the input of pipe, described the with the sixteenmo respectively The control end connection of 17 switching tubes；

The input of 17th switching tube connects the output end of the 15th switching tube, the 17th switching tube it is defeated Go out end connection earth terminal.

5. low differential voltage linear voltage stabilizer circuit according to claim 4, it is characterised in that

12nd switching tube, the 13rd switching tube, the 14th switching tube and the 15th switching tube are PMOS；

The sixteenmo closes pipe and the 17th switching tube is NMOS tube.

6. low differential voltage linear voltage stabilizer circuit according to claim 1, it is characterised in that the feedback circuit includes：The One resistance and second resistance；

The output end of one end connection adjustment pipe of the first resistor, the other end of the first resistor passes through described second The common port of resistance connection earth terminal, the first resistor and the second resistance connects described as the output end of feedback circuit The normal phase input end of error amplifier.

7. low differential voltage linear voltage stabilizer circuit according to claim 1, it is characterised in that also include：Filter circuit；

The input of the filter circuit is connected with the output end of the low differential voltage linear voltage stabilizer circuit, the filter circuit Output end connects earth terminal.

8. low differential voltage linear voltage stabilizer circuit according to claim 7, it is characterised in that the filter circuit includes：Filter Ripple resistance and filter capacitor；

One end of the filter resistance connects the output end of the low differential voltage linear voltage stabilizer circuit, the filter resistance it is another End connection earth terminal；

The positive plate of the filter capacitor connects the output end of the low differential voltage linear voltage stabilizer circuit, the filter capacitor it is negative Pole plate connects earth terminal.