CN110364568B - IGBT device and forming method thereof - Google Patents

Abstract

The invention provides an IGBT device and a forming method thereof. Since the field plate structure in the terminal area of the IGBT device is embedded into the substrate, the height of the field plate structure relative to the substrate surface is greatly reduced, which is beneficial to reducing the height difference between the terminal area and the active area. This can further improve the difficulty of preparation due to the large height difference in subsequent processes.

Description

IGBT device and method of forming the same

Technical field

The present invention relates to the field of semiconductor technology, and in particular to an IGBT device and a forming method thereof.

Background technique

Insulated Gate Bipolar Transistor (IGBT, Insulated Gate Bipolar Transistor) is a new type of high-power device that combines the gate voltage control characteristics of MOSFET and the low on-resistance characteristics of bipolar transistors, improving the device withstand voltage and on-resistance. The situation of mutual restraint has the advantages of high voltage, large current, high frequency, high power integration density, large input impedance, small on-resistance, and low switching loss. It has gained wide application space in many fields such as frequency conversion home appliances, industrial control, electric and hybrid vehicles, new energy, and smart grids.

In an IGBT device, a terminal ring is usually provided around the active area of the IGBT device to protect the active area and improve the lateral voltage withstand capability of the device to avoid breakdown of the IGBT device. Specifically, a field plate structure is usually formed in the terminal area. The field plate structure can effectively alleviate the increase in local electric field intensity through the capacitive coupling effect, thereby achieving uniform distribution of the electric field in a limited lateral distance and optimizing the IGBT device. pressure resistance.

However, currently common field plate structures are usually formed on the substrate surface, and due to the formation of the field plate structure, the height of the terminal region is higher than the height of the active region. That is, there is a large height difference between the terminal area and the active area, which will have an adverse impact on subsequent processes.

Contents of the invention

The object of the present invention is to provide an IGBT device to solve the problem of a large height difference between the terminal area and the active area of the existing IGBT device.

In order to solve the above technical problems, the present invention provides an IGBT device, including a substrate having an active area and a terminal area located on the periphery of the active area, and is formed in the active area. There are multiple cell structures, and at least one field plate structure is formed in the terminal area;

Wherein, at least one field plate trench is formed in the substrate of the terminal region, the field plate structure includes a first dielectric layer and a first conductive layer, and the first dielectric layer covers the field plate trench. Sidewalls and bottom, the first conductive layer is formed on the first dielectric layer and located in the field plate trench.

Optionally, a plurality of field-limited rings are also formed in the substrate of the terminal region, the field-limited rings include first doped regions of the first conductivity type, and the first doped regions are formed from the substrate. The surface of the bottom extends toward the interior of the substrate and extends to the sidewalls of the field plate trench.

Optionally, the field plate structure also includes:

A second dielectric layer covers the first conductive layer, and a first through hole is opened in the second dielectric layer at a position corresponding to the first conductive layer, and the first through hole penetrates the second conductive layer. medium layer;

A second conductive layer is formed on the second dielectric layer. The second conductive layer fills the first through hole to connect with the first conductive layer. The second through hole penetrates the second dielectric layer. layer.

Optionally, a plurality of field limiting rings are also formed in the substrate of the terminal region, the field limiting rings include a first doping region of a first conductivity type, the first doping region is formed from the The surface of the substrate extends toward the interior of the substrate; the second dielectric layer also covers the first doped region, and is at a position corresponding to the first doped region in the second dielectric layer A second through hole is opened; the second conductive layer fills the second through hole to connect with the field limiting ring.

Optionally, a plurality of gate trenches are formed in the substrate in the active area, and the cell structure includes:

A gate dielectric layer formed on the bottom and sidewalls of the gate trench; and,

A gate conductive layer is formed on the gate dielectric layer and fills the gate trench.

Optionally, the unit cell structure further includes a well region, the well region includes a second doped region of the first conductivity type, the second doped region extends from the surface of the substrate to the surface of the substrate. The inner extension extends to the sidewalls of the gate trench.

Another object of the present invention is to provide a method for forming an IGBT device, including:

Provide a substrate in which an active area for forming a cellular structure and a terminal area located at the periphery of the active area are defined;

forming at least one field plate trench in the substrate in the termination region;

forming a first dielectric layer on the substrate in the terminal region, the first dielectric layer covering the sidewalls and bottom of the field plate trench; and,

A first conductive layer is formed in the field plate trench, and the first conductive layer is located on the first dielectric layer.

Optionally, before forming the field plate trench, the method further includes: forming at least one first doped region of the first conductivity type in the substrate of the terminal region, and the first doped region is used to form a field. a limiting ring; and when forming the field plate trench, the sidewalls of the field plate trench extend to the first doped region.

Optionally, when the first doped region is formed in the terminal region, a second doped region of the first conductivity type is also formed in the active region at the same time, and the second doped region is used for The well region constituting the cellular structure.

Optionally, when the field plate trench is formed in the substrate of the terminal region, a gate trench is also formed in the substrate of the active region at the same time.

Optionally, the opening size of the field plate trench is larger than the opening size of the gate trench.

Optionally, when the first dielectric layer is formed on the substrate of the terminal region, a gate dielectric layer is also formed on the substrate of the active region at the same time, and the gate dielectric layer covers the gate trench. Side walls and bottom of the tank.

Optionally, when forming the first conductive layer in the field plate trench, a gate conductive layer is also formed in the field plate trench at the same time. The method of forming the first conductive layer and the gate conductive layer includes: :

forming a conductive material layer on the substrate, the conductive material layer covering the surface of the substrate and the bottom and sidewalls of the field plate trench, and completely filling the gate trench;

Perform an etching back process to remove the portion of the conductive material layer located on the substrate surface, so that the remaining conductive material layer located in the active area is only filled in the gate trench to form the gate The conductive layer and the remaining conductive material layer located in the terminal area cover the sidewalls of the field plate trench to form the first conductive layer.

Optionally, the formation method of the IGBT device also includes:

A second dielectric layer is formed on the substrate in the terminal area, the second dielectric layer covers the first conductive layer, and a position in the second dielectric layer corresponding to the first conductive layer is opened. a first through hole, the first through hole exposing the first conductive layer;

A second conductive layer is formed on the second dielectric layer, and the second conductive layer fills the first through hole to connect with the first conductive layer.

Optionally, at least one first doped region of the first conductivity type is formed in the substrate of the terminal region, and the first doped region is used to form a field-limited ring; the second dielectric layer covers the a first doped region, and a second through hole is opened in the second dielectric layer at a position corresponding to the first doped region, and the second through hole exposes the first doped region; The second conductive layer fills the second through hole to connect with the field limiting loop.

In the IGBT device provided by the present invention, since a field plate trench is formed in the substrate of the terminal area and the field plate structure is extended into the field plate trench, specifically the first conductive layer is disposed in the field plate trench. , which is equivalent to embedding the field plate structure into the substrate, thereby greatly reducing the height of the field plate structure relative to the substrate surface. In this way, the height difference between the terminal area and the active area can be effectively reduced, and the preparation difficulty of subsequent processes is reduced.

Furthermore, in the preparation method of the IGBT device provided by the present invention, the field plate trench in the terminal area and the gate trench in the active area can be formed at the same time, and the field plate can be realized without additional additional process flow. The formation of grooves is conducive to simplifying the process.

Description of the drawings

Figure 1a is a schematic structural diagram of the terminal area of an IGBT device;

Figure 1b is a schematic structural diagram of the active area of an IGBT device;

Figure 2a is a schematic diagram of the positional relationship between the active area and the terminal area of the IGBT device in an embodiment of the present invention;

Figure 2b is a schematic structural diagram of an IGBT device in an embodiment of the present invention;

Figure 3 is a schematic flow chart of a method for forming an IGBT device in an embodiment of the present invention;

4a to 4f are schematic structural diagrams of a method for forming an IGBT device in the preparation process according to an embodiment of the present invention.

Detailed ways

As mentioned in the background art, in existing IGBT devices, there is a large height difference between the active area and the terminal area, which will adversely affect subsequent processes. Therefore, how to reduce the height difference between the active area and the terminal area is particularly important.

Figure 1a is a schematic structural diagram of the terminal area of an IGBT device, and Figure 1b is a schematic structural diagram of the active area of an IGBT device. As shown in FIGS. 1a and 1b , an IGBT device includes a substrate 1 in which an active region 20 and a terminal region 10 are defined.

Referring first to FIG. 1 a , at least one field plate structure 10A is formed in the terminal area 10 . The field plate structure 10A includes, for example, a field plate dielectric layer 11 and a first field plate 12 sequentially formed on the surface of the substrate 1 . , interlayer dielectric layer 13 and second field plate 14 . That is, the field plate structure 10A has a multi-layer stacked structure sequentially stacked on the surface of the substrate 1 , and its height relative to the surface of the substrate 1 is approximately equal to the sum of the thicknesses of the multi-layered stacked structures.

Next, as shown in FIG. 1 b , a plurality of cellular structures 20A are formed in the active area 20 . The unit cell structure 20A may be a planar insulated gate bipolar transistor or a trench insulated gate bipolar transistor. When the cellular structure 20A is a trench-type insulated gate bipolar transistor, the gate 21 of the cellular structure 20A is formed in the gate trench of the substrate 1 , that is, the gate of the cellular structure 20A 21 is embedded into the substrate 1 , thereby making the cell structure 20A smaller in height relative to the surface of the substrate 1 .

It can be seen that the height of the field plate structure 10A in the terminal area 10 relative to the surface of the substrate 1 is much higher than the height of the cell structure 20A in the active area 20 relative to the surface of the substrate 1 , resulting in the difference between the terminal area 10 and the active area There is a large height difference between 20 and 20, which will have an adverse impact on subsequent processes, for example, making the photolithography process more difficult. Specifically, on the one hand, the height difference will lead to uneven coating in the photolithography process, forming process abnormalities such as "spatter shadows"; on the other hand, the thickness of the photoresist needs to be increased to ensure that the photoresist can Taking into account the coverage of devices of different heights, however, a larger thickness of photoresist will further affect the photolithography accuracy, for example, the accuracy difference of the critical dimensions (CD) defined by photolithography and the process control capabilities such as photolithography alignment deviation (Overlay) decline.

To this end, the present invention provides an IGBT device, including: a substrate having an active area and a terminal area located on the periphery of the active area, and a A plurality of cellular structures, with at least one field plate structure formed in the terminal region;

Wherein, at least one field plate trench is formed in the substrate of the terminal region, the field plate structure includes a first dielectric layer and a first conductive layer, and the first dielectric layer covers the field plate trench. Sidewalls and bottom, the first conductive layer is formed on the first dielectric layer and located in the field plate trench.

In the IGBT device provided by the present invention, since the field plate structure in the terminal area is embedded into the substrate, the height of the field plate structure relative to the substrate surface is greatly reduced, which is beneficial to reducing the distance between the terminal area and the active area. height difference.

The IGBT device and its formation method proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use imprecise proportions, and are only used to conveniently and clearly assist in explaining the embodiments of the present invention.

Figure 2a is a schematic diagram of the positional relationship between the active area and the terminal area of the IGBT device in one embodiment of the present invention. Figure 2b is a schematic structural diagram of the IGBT device in one embodiment of the present invention.

As shown in Figure 2a and Figure 2b, the IGBT device includes: a substrate 100. The substrate 100 has an active area 100B and a terminal area 100A located on the periphery of the active area 100B, as shown in Figure 2a. The terminal area 100A surrounds the periphery of the active area 100B. A plurality of cell structures 101B are formed in the active area 100B, and at least one field plate structure 101A is formed in the terminal area 100A. In addition, there is a gate region 100C in the substrate, and the gate region 100C is used to control the on or off of the cell structure.

Wherein, at least one field plate trench 120A is formed in the substrate 100 of the terminal area 100A, and the field plate trench 120A surrounds the periphery of the active area 100B along the boundary of the active area 100B. As shown in FIG. 2a , in this embodiment, there are a plurality of field plate trenches 120A, and the plurality of field plate trenches 120A are sequentially arranged in an annular structure in a direction away from the active area 100B.

The field plate structure 101A includes a first dielectric layer 130A and a first conductive layer 140A. The first dielectric layer 130A covers the sidewalls and bottom of the field plate trench 120A in the terminal area 100A. Of course, the first dielectric layer 130A can further extend to cover the surface of the substrate 100 to This enables the subsequent film layer formed on the surface of the substrate to be isolated from the substrate. And, a first conductive layer 140A is formed on the first dielectric layer 130A and located in the trench 120A.

It can be understood that the field plate structure 101A is embedded into the substrate 100. Therefore, compared to forming the field plate structure on the surface of the substrate, embedding the field plate structure 101A into the substrate greatly reduces the relative strength of the field plate structure 101A. to the height position of the substrate surface, so that the height position of the terminal area 100A can be reduced accordingly.

As shown in FIG. 2b , in this embodiment, the first conductive layer 140A in the field plate structure 101A is formed on the sidewalls of the field plate trench 120A. However, it should be appreciated that according to the specific performance of the formed field plate structure, the extension size of the first conductive layer 140 in the field plate trench 120A can be adjusted accordingly. For example, the first conductive layer 140A can be further extended to The bottom of field plate trench 120A.

As shown in FIG. 2a and FIG. 2b , multiple field-limited rings are also formed in the substrate 100 of the terminal region 100A. It can be understood that the field-limited rings surround the active region 100B along the boundary of the active region 100B. On the periphery of the active area 100B, a plurality of field-limited rings are arranged in a ring-shaped structure in a direction away from the active area 100B. With specific reference to FIG. 2 b , the field-limited ring includes a first doped region 110A of a first conductivity type. The first doped region 110A extends from the surface of the substrate 100 to the interior of the substrate. , and extends to the side wall of the field plate trench 120A.

Further, the first conductive layer 140A covers the sidewalls of the field plate trench 120A, so that the first dielectric layer 130A covers the field limit ring from the sidewalls of the field plate trench 120A (corresponding to covering the first doped region 110A). That is, in this embodiment, the first conductive layer 140A is formed on the sidewall of the field plate trench 120A, and the first doping region 110A extends to the sidewall of the field plate trench 120A, so it is parallel to the substrate surface. In the direction of , the first conductive layer 140A and the first doped region 110A partially overlap in space, so that the electric field can expand in the direction away from the active region 100B in the terminal region 100A to achieve the lateral direction of the IGBT device. partial pressure process.

In addition, the field plate structure 101A also includes:

The second dielectric layer 170A covers the first conductive layer 140A to isolate the first conductive layer 140A, and a first through hole is opened in the second dielectric layer 170A at a position corresponding to the first conductive layer 140A. hole, the first through hole penetrates the second dielectric layer 170A; in this embodiment, the second dielectric layer 170A also covers the surface of the substrate 100 to correspondingly cover the first doped region 110A, and the A second through hole is also provided in the second dielectric layer 170A at a position corresponding to the first doped region 110A, and the second through hole penetrates the second dielectric layer 170A;

The second conductive layer 180A is formed on the second dielectric layer 170A, and the second conductive layer 180A fills the first through hole to connect with the first conductive layer 213; and, the second conductive layer 180A is formed on the second dielectric layer 170A. The layer 180A further fills the second through hole to be electrically connected to the first doped region 110A. That is, the first conductive layer 140A and the first doped region 110A of the field limiting ring are both electrically connected to the second conductive layer 180A, so that when realizing the voltage dividing process of the IGBT device, the first conductive layer can 140A and the second conductive layer 180A are in the same potential state.

Referring next to Figure 2b, in this embodiment, a plurality of cellular structures 101B are arranged in an array in the active area 100B, for example, and the cellular structures 101B are trench-type insulated gate bipolar transistors. That is, the gate electrode of the cellular structure 101B is embedded in the substrate 100 . Specifically, a gate trench is formed in the substrate of the active area 100B, and the gate dielectric layer 130B of the gate of the unit cell structure 101B is formed on the sidewalls and bottom of the gate trench. A conductive layer 140B is formed on the gate dielectric layer 130B and fills the gate trench.

Further, the unit cell structure 101B further includes a well region, and the well region is composed of a second doped region 110B of the first conductivity type. The second doped region 110B diffuses and extends from the surface of the substrate to the interior of the substrate, and the second doped region 110B further extends to the sidewall of the gate trench, so that the gate The dielectric layer 130B and the gate conductive layer 140B at least partially spatially overlap the well region in a direction parallel to the substrate surface.

In addition, the unit cell structure 101B also includes an emitter region 150B and a source region 160B. The emitter region 150B and the source region 160B are both formed in the second doped region 110B of the well region, where The source region 160B is located on the side of the gate.

FIG. 3 is a schematic flowchart of a method for forming an IGBT device in an embodiment of the present invention. FIGS. 4a to 4f are schematic structural views of the method of forming an IGBT device in an embodiment of the present invention during its preparation process. The method for forming the IGBT device in this embodiment will be described in detail below with reference to the accompanying drawings.

In step S110, with specific reference to FIG. 4a, a substrate 100 is provided. The substrate 100 defines an active area 100B for forming a cellular structure and a terminal area located at the periphery of the active area 100B. 100A.

Specifically, the substrate 100 may be, for example, a substrate of a first conductivity type, wherein the substrate of the active region 100B is doped with an ion region of the first conductivity type, and the ion region of the first conductivity type It can be used to form the base region of the formed cellular structure. In this embodiment, the first conductivity type is N-type, that is, the base region of the subsequently formed cellular structure is N-type.

Further, at least one first doped region 110A is formed in the substrate of the terminal region 100A, and the first doped region 110A is used to form a field limiting ring; and, in the substrate of the active region 100B A plurality of second doped regions 110B are also formed, and the second doped regions 110B are used to constitute well regions of the formed unit cell structure.

In a preferred solution, the first doped region 110A in the terminal region 100A and the second doped region 110B in the active region 100B are formed in the same process step, as shown in FIG. 4a for details.

First, a first mask layer 210 is formed on the substrate 100, and the first mask layer 210 is simultaneously formed in the active area 100B and the terminal area 100A. Among them, a plurality of openings are opened in the first mask layer 210, some of the openings correspond to the second doping region that needs to be formed later to expose the substrate in the active region 100B, and the other part of the openings correspond to the second doping region that needs to be formed later. A doped region exposes the substrate of the terminal region 100A.

Next, an ion implantation process is used to form a second doped region 110B in the active region 100B and a first doped region 110A in the terminal region 100A. After the first doped region 110A and the second doped region 110B are formed, the first mask layer 210 can be removed.

In addition, in an optional solution, after performing the ion implantation process, a thermal annealing process is also performed to activate the implanted ions and drive the implanted ions to diffuse to form a uniformly distributed doping region.

In step S120, with specific reference to FIG. 4b, at least one field plate trench 120A is formed in the substrate 100 in the terminal region 100A. By forming the field plate trench 120A, the subsequently formed field plate structure can be embedded into the substrate 100 .

In this embodiment, the cell structure formed in the active region 100B is a trench-type insulated gate bipolar transistor, that is, the gate of the cell structure is formed in the gate trench of the substrate.

In a preferred solution, during the process of forming the field plate trench 120A in the terminal region 100A, the gate trench 120B is also formed in the active region 100B. Or it can also be understood that when the gate trench 120B is formed, the field plate trench 120A is simultaneously formed in the terminal region. That is, the field plate trench 120A can be formed simultaneously using the formation process of the gate trench 120B. It can be seen that, The original formation process will not be affected when forming the field plate trench 120A, and no additional process steps are required.

As shown in FIG. 4 b , the gate trench 120B and the field plate trench 120A are formed by, for example:

In the first step, a second mask layer 220 is formed on the substrate 100, and the second mask layer 220 is simultaneously formed in the active area 100B and the terminal area 100A; wherein, the second mask layer 220 There are multiple openings in the middle, some openings correspond to the gate trenches that need to be formed later and expose the substrate of the active area 100B, and the other openings correspond to the field plate trenches that need to be formed later and expose the substrate of the terminal area 100A. ;

Further, the opening in the second mask layer 220 corresponding to the active region 100B exposes part of the boundary of the second doped region 110B, and extends in a direction away from the second doped region 110B to expose A substrate that does not correspond to the second doped region; and, the opening in the second mask layer 220 corresponds to the terminal region 100A, which exposes part of the boundary of the first doped region 110A and moves away from the first doped region. The direction of the impurity region 110A is expanded to expose the substrate that does not correspond to the first doping region;

The second step is to use the second mask layer 220 as a mask to etch the substrate 100 to form a gate trench 120B in the active region 100B and a field plate trench in the terminal region 100A. 120A. Correspondingly, the sidewalls of the formed gate trench 120B extend to the second doped region 110B, so that the gate trench 120B and the second doped region 110B are parallel to the substrate surface. At least part of the spatial overlap in the direction, so that the gate electrode subsequently filled in the gate trench 120A and the well region composed of the second doped region 110B are also correspondingly in the direction parallel to the substrate surface. At least some of the space overlaps. And, the sidewalls of the formed field plate trench 120A extend to the first doped region 110A, so that the field plate trench 120A and the first doped region 110A are in a direction parallel to the substrate surface. At least part of the space overlaps.

After the gate trench 120B and the field plate trench 120A are formed, the second mask layer 220 can be removed.

In addition, the opening size of the field plate trench 120A may be further larger than the size of the gate trench 120B. That is, the field plate trench 120A has a larger opening size, so it can provide a larger formation space for the field plate structure that needs to be formed subsequently, so that when the size of the field plate structure needs to be adjusted, it can have a larger opening size. Adjust sensitivity.

In step S130, with specific reference to FIG. 4c, a first dielectric layer 130A is formed on the substrate 100 in the terminal region 100A, and the first dielectric layer 130A covers the bottom and sidewalls of the field plate trench 120A. . Of course, the first dielectric layer 130A can further cover the surface of the substrate 100 .

In a preferred solution, when the first dielectric layer 130A is formed in the terminal region 100A, a gate dielectric layer 130B is also formed in the active region 100B. The gate dielectric layer 130B covers the bottom and bottom of the gate trench 120B. The sidewalls may of course further extend to cover the surface of the substrate. The first dielectric layer 130A and the gate dielectric layer 130B may be made of, for example, silicon oxide.

In addition, the first dielectric layer 130A and the gate dielectric layer 130B may be formed through a thermal oxidation process. Specifically, the same thermal oxidation process can be used to simultaneously form the first dielectric layer 130A in the terminal region 100A and the gate dielectric layer 130B in the active region 100B.

In step S140, with specific reference to FIG. 4d, a first conductive layer 140A is formed in the field plate trench 120A, and the first conductive layer 140A is located on the first dielectric layer 130A. In this embodiment, the formed first conductive layer 140A is only located in the field plate trench 120A, so that the subsequently formed field plate structure is embedded into the substrate 100, thereby effectively reducing the relative size of the field plate structure relative to the substrate. The height of the bottom surface accordingly reduces the height of the entire terminal area.

In this embodiment, the first conductive layer 140A covers the sidewalls of the field plate trench 120A. Of course, in other embodiments, the size of the first conductive layer 140A can also be adjusted according to actual needs. For example, the first conductive layer 140A can be further covered with the bottom of the field plate trench 120A to increase the size of the first conductive layer 140A. size. Therefore, by providing the field plate trench 120A with a larger opening size, it is beneficial to control and adjust the size of the first conductive layer 140A and the like.

Further, this step also includes forming a gate conductive layer 140B in the active region 100B, the gate conductive layer 140B filling the gate trench, the gate dielectric layer 130B and the gate conductive layer 140B. Used to form the gate of the cellular structure. The first conductive layer 140A and the gate conductive layer 140B may be formed of the same material, for example, they may both include polysilicon.

In a preferred solution, the first conductive layer 140A and the gate conductive layer 140B can also be formed in the same process step. For example, the following steps may be included.

Step 1: Form a conductive material layer on the substrate 100. The conductive material layer covers the surface of the substrate 100 and the bottom and sidewalls of the field plate trench 120A, and completely fills the gate trench. It should be noted that in this embodiment, the opening size of the field plate trench 120A is larger than the opening size of the gate trench, so the conductive material layer can completely fill the gate trench and only cover the bottom and bottom of the field plate trench 120A. The sidewalls do not completely fill the field plate trench 120A.

Step 2: Perform an etching back process on the conductive material layer to remove the portion of the conductive material layer located on the substrate surface. That is, at this time, the remaining conductive material layer in the active region 100B is only filled in the gate trench to form the gate conductive layer 140B; while in the terminal region 100A, the conductive material layer located on the surface of the substrate 100 and the bottom of the field plate trench 120A The conductive material layer is removed, and the conductive material layer located on the sidewall of the field plate trench 120A is retained for forming the first conductive layer 140A.

In addition, with specific reference to FIG. 4e , after forming the gate conductive layer, an emitter region 150B of the first conductivity type and a source region 160B of the second conductivity type can be formed in the substrate of the active region 100B. , the emitter region 150B and the source region 160B are both formed in the well region (the second doped region 110B), and the source region 160B is located on the side of the gate.

In this embodiment, the second doping region 110B of the first conductivity type is N-type, the emitter region 150B of the first conductivity type is also N-type, and the source region 160B of the second conductivity type is P-type. The doping concentration of the emitter region 150B is greater than the doping concentration of the second doping region 110B.

Optionally, this step may also include removing a portion of the gate dielectric layer located on the substrate surface, and exposing a portion of the gate dielectric layer 130B located in the gate trench.

In step S150, with specific reference to FIG. 4f, a second dielectric layer 170A and a second conductive layer 180A are sequentially formed on the substrate of the terminal region 100A. That is, in this embodiment, the field plate structure 101A formed is a multi-level field plate structure.

The second dielectric layer 170A covers the first conductive layer 140A, and a first through hole is opened in the second dielectric layer 170A at a position corresponding to the first conductive layer 140A. And, the second conductive layer 180A fills the first through hole to connect with the first conductive layer 140A.

Continuing to refer to Figure 4f, in this embodiment, a plurality of first doped regions 110A of the first conductivity type are formed in the substrate of the terminal region 100A, and the first doped regions 110A are used to form field limits. ring. The second dielectric layer 170A correspondingly covers the first doped region 110A to isolate and protect the first doped region 110A. Furthermore, a second through hole is opened in the second dielectric layer 170A at a position corresponding to the first doped region 110A, and the second conductive layer 180A further fills the second through hole to interact with the field. Limited ring connection.

Each embodiment in this specification is described in a progressive manner. Each embodiment focuses on its differences from other embodiments. The same and similar parts between the various embodiments can be referred to each other.

The above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. Any changes or modifications made by those of ordinary skill in the field of the present invention based on the above disclosure shall fall within the scope of the claims.

Claims (13)

1. An IGBT device comprising a substrate having an active region in which a plurality of cell structures are formed and a termination region at a periphery of the active region in which at least one field plate structure is formed;

a plurality of field plate grooves are formed in the substrate of the terminal area, the field plate grooves surround the periphery of the active area along the boundary of the active area, and the field plate grooves are sequentially distributed in an annular structure in the direction away from the active area; the field plate structure comprises a first dielectric layer and a first conductive layer, wherein the first dielectric layer covers the side wall and the bottom of the field plate groove, and the first conductive layer is formed on the first dielectric layer and is positioned in the field plate groove; the first conductive layer covers the inclined side wall of the field plate groove;

and a plurality of field limiting rings are further formed in the substrate of the terminal region, the field limiting rings comprise first doped regions of a first conductivity type, the first doped regions are located in the substrate between adjacent field plate trenches and extend from the top surface of the substrate to the inside of the substrate, and the first doped regions are electrically connected with the first conductive layer.

2. The IGBT device of claim 1 wherein the field plate structure further comprises:

the second dielectric layer covers the first conductive layer, a first through hole is formed in the second dielectric layer at a position corresponding to the first conductive layer, and the first through hole penetrates through the second dielectric layer; the method comprises the steps of,

and the second conductive layer is formed on the second dielectric layer, fills the first through hole and is connected with the first conductive layer.

3. The IGBT device of claim 2 wherein the second dielectric layer also covers the first doped region, and wherein a second through hole is formed in the second dielectric layer at a position corresponding to the first doped region, the second through hole penetrating through the second dielectric layer; the second conductive layer fills the second through hole and is connected with the field limiting ring.

4. The IGBT device of claim 1 wherein a plurality of gate trenches are formed in the substrate of the active region, the cell structure comprising:

the gate dielectric layer is formed on the bottom and the side wall of the gate trench; the method comprises the steps of,

and the gate conducting layer is formed on the gate dielectric layer and filled in the gate groove.

5. The IGBT device of claim 4 wherein the cell structure further comprises a well region comprising a second doped region of the first conductivity type extending from the surface of the substrate toward the interior of the substrate and onto the sidewalls of the gate trench.

6. The method for forming the IGBT device is characterized by comprising the following steps of:

providing a substrate, wherein an active area for forming a cell structure and a terminal area positioned at the periphery of the active area are defined in the substrate;

forming at least one first doped region of a first conductivity type in a substrate of the termination region, the first doped region being for forming a field limiting ring;

forming a plurality of field plate grooves in a substrate of the terminal region, wherein the field plate grooves surround the periphery of the active region along the boundary of the active region, the plurality of field plate grooves are sequentially arranged in an annular structure in a direction away from the active region, and the field plate grooves are provided with inclined side walls;

forming a first dielectric layer on the substrate of the terminal region, wherein the first dielectric layer covers the side wall and the bottom of the field plate groove; the method comprises the steps of,

and forming a first conductive layer in the field plate groove, wherein the first conductive layer is positioned on the first dielectric layer and covers the inclined side wall of the field plate groove, and the first conductive layer is electrically connected with the first doped region.

7. The method of forming an IGBT device of claim 6 wherein, when the terminal region forms the first doped region, a second doped region of the first conductivity type is also formed in the active region at the same time, the second doped region being used to form a well region of the cell structure.

8. The method of forming an IGBT device of claim 6 wherein a gate trench is also formed in the substrate of the active region at the same time as the field plate trench is formed in the substrate of the termination region.

9. The method of forming an IGBT device of claim 8 wherein the field plate trench has an opening size greater than an opening size of the gate trench.

10. The method for forming an IGBT device of claim 8 wherein when forming the first dielectric layer on the substrate of the termination region, a gate dielectric layer is also formed on the substrate of the active region, the gate dielectric layer covering sidewalls and bottom of the gate trench.

11. The method of forming an IGBT device of claim 8 wherein, when forming a first conductive layer in the field plate trench, a gate conductive layer is also formed in the field plate trench at the same time, the method of forming the first conductive layer and the gate conductive layer comprising:

forming a conductive material layer on the substrate, wherein the conductive material layer covers the surface of the substrate, the bottom and the side walls of the field plate groove and fills the grid groove;

and performing an etching back process, removing the part of the conductive material layer, which is positioned on the surface of the substrate, so that the rest of the conductive material layer positioned in the active region is only filled in the gate trench to form the gate conductive layer, and covering the side wall of the field plate trench by the rest of the conductive material layer positioned in the terminal region to form the first conductive layer.

12. The method of forming an IGBT device of claim 6, further comprising:

forming a second dielectric layer on the substrate of the terminal region, wherein the second dielectric layer covers the first conductive layer, a first through hole is formed in the second dielectric layer, and the first through hole exposes the first conductive layer;

and forming a second conductive layer on the second dielectric layer, wherein the second conductive layer fills the first through hole and is connected with the first conductive layer.

13. The method of forming an IGBT device of claim 12 wherein at least one first doped region of a first conductivity type is formed in the substrate of the termination region, the first doped region being used to form a field stop ring; the second dielectric layer covers the first doped region, and a second through hole is further formed in the second dielectric layer, and the second through hole exposes the first doped region; the second conductive layer fills the second through hole and is connected with the field limiting ring.