CN117293170A - Self-aligned trench MOSFET and method of making same - Google Patents

Abstract

The application provides a self-aligned trench MOSFET and a method of manufacturing the same, the method comprising: providing a substrate, forming an epitaxial layer on the substrate, and forming a hard mask layer on the epitaxial layer; forming a plurality of trenches in the epitaxial layer; sequentially forming a gate dielectric layer and a gate layer in the groove, wherein the top of the gate layer is higher than the top surface of the epitaxial layer; after the hard mask layer is removed, body region implantation and source region implantation are sequentially carried out on the epitaxial layer; forming side walls on two sides of the part of the grid electrode layer higher than the epitaxial layer; after forming the contact hole through a self-alignment process, filling a metal plug in the contact hole. Due to the fact that the side walls on the two sides of the part, higher than the epitaxial layer, of the gate layer are capable of forming self-aligned groove contact holes, device failure caused by too close distance between the contact holes and the groove gate due to fluctuation of feature sizes or photoetching alignment precision of the contact holes is avoided under the manufacturing process of the small-pitch groove MOSFET, and device parameter fluctuation caused by the fact that the injection area at the bottom of the contact holes is close to the channel area of the MOSFET is also avoided.

Description

Self-aligned trench MOSFET and method of manufacturing same

Technical field

The present application relates to the field of power semiconductor devices and manufacturing processes, and specifically to a self-aligned trench MOSFET and its manufacturing method.

Background technique

In existing trench MOSFETs, trench contact holes are formed by a non-self-aligned process, and the distance between the trench contact holes and the trench gate is controlled by the precision of layout design and photolithography process. In the process of continuous pursuit of size reduction and on-resistance reduction, when the pitch is less than 0.6 microns, forming contact holes with good morphology poses a huge challenge to the photolithography and etching processes.

Contents of the invention

In view of the above shortcomings of the prior art, the purpose of this application is to provide a self-aligned trench MOSFET and a manufacturing method thereof to solve the problem of precision control of the distance between the trench contact hole and the trench gate in the prior art. Poor question.

In order to achieve the above objectives and other related objectives, this application provides a manufacturing method of a self-aligned trench MOSFET, including:

Step S1: Provide a substrate, form an epitaxial layer on the substrate, and form a hard mask layer on the epitaxial layer;

Step S2, forming multiple trenches in the epitaxial layer;

Step S3, sequentially forming a gate dielectric layer and a gate electrode layer in the trench, with the top of the gate electrode layer being higher than the top surface of the epitaxial layer;

Step S4: After removing the hard mask layer, perform body region implantation and source region implantation on the epitaxial layer in sequence;

Step S5, forming sidewalls on both sides of the portion of the gate layer that is higher than the epitaxial layer;

Step S6: After forming the self-aligned contact hole through the self-alignment process, fill the self-aligned contact hole with a metal plug.

Preferably, the vertical distance between the top of the gate layer and the top surface of the epitaxial layer is 500 angstroms to 3000 angstroms.

Preferably, the material of the hard mask layer is an oxide or a stacked structure composed of oxide-nitride-oxide.

Preferably, the step of forming the trench includes: coating photoresist on the surface of the hard mask layer and using a photolithography process to define the formation area of the trench; etching the hard mask layer using the photoresist as a mask; The photoresist is removed, and the epitaxial layer is etched to form trenches using the hard mask layer as a mask.

Preferably, in step S3, a gate dielectric layer is first formed on the inner surface of the trench in the epitaxial layer, and then the gate layer is filled in the trench where the gate dielectric layer is formed.

Preferably, a thermal oxidation process is used to form the gate dielectric layer.

Preferably, after the gate layer is formed using a deposition process, an etching back or a chemical mechanical polishing process or a combination of the two is performed to remove the gate layer located on the hard mask layer, and the top of the gate layer is higher than the epitaxial layer. top surface.

Preferably, before performing the body region implantation, a shielding oxide layer is formed through a deposition process to cover the epitaxial layer and the gate layer.

Preferably, before performing source region injection, a step of implementing low thermal budget body region advancement is also included.

Preferably, after the source region is implanted, an annealing step is further included to activate the doping material in the source region.

Preferably, the sidewall material is silicon nitride.

Preferably, a dielectric layer before metal deposition is first formed on the epitaxial layer through a deposition process, and then a self-aligned contact hole is formed through photolithography and etching processes.

Preferably, the material of the dielectric layer before metal deposition is oxide.

Preferably, the etching has a high selectivity to the dielectric layer and spacers before metal deposition.

Preferably, after forming the self-aligned contact hole and before filling the metal plug, the step further includes the steps of implanting the contact hole to form a doped region and performing annealing to activate the doped material in the doped region.

Embodiments of the present application also provide a self-aligned trench MOSFET manufactured according to the above manufacturing method. The top of the gate layer constituting the trench gate is higher than the epitaxial layer, and the gate layer is formed on both sides of the portion higher than the epitaxial layer. There are side walls.

Preferably, the height of the portion of the gate layer higher than the epitaxial layer is 500 angstroms to 3000 angstroms.

As mentioned above, the self-aligned trench MOSFET and its manufacturing method provided by this application have the following beneficial effects: due to the existence of sidewalls on both sides of the part of the gate layer higher than the epitaxial layer, a self-aligned trench can be formed For contact holes, in the manufacturing process of small-pitch trench MOSFET, it is necessary to avoid fluctuations in the characteristic size of the contact holes or the accuracy of photolithography overlays, which may cause device failure due to the close distance between the contact holes and the trench gates. It also avoids the close proximity of the injection area at the bottom of the contact holes. The channel region of a MOSFET causes fluctuations in device parameters.

Description of drawings

In order to more clearly explain the specific embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings in the following description The drawings illustrate some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 shows a schematic cross-sectional structure diagram of an existing trench MOSFET;

Figure 2 shows a flow chart of a manufacturing method of a self-aligned trench MOSFET provided for an embodiment of the present application;

3A to 3F are schematic cross-sectional structural diagrams of the device formed after each step is completed in the manufacturing method of the self-aligned trench MOSFET provided in the embodiment of the present application.

Detailed ways

The following describes the implementation of the present application through specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

The technical solutions in this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some of the embodiments of this application, but not all of them. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of this application.

In the description of this application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. The indicated orientation or positional relationship is only for the convenience of describing the present application and simplifying the description. It does not indicate or imply that the indicated device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. limit. Furthermore, the terms “first”, “second” and “third” are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of this application, it should be noted that, unless otherwise clearly stated and limited, the terms "installation", "connection" and "connection" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection. Connection, or integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediary; it can also be an internal connection between two components; it can be a wireless connection or a wired connection connect. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood on a case-by-case basis.

In addition, the technical features involved in different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

As shown in Figure 1, the top of the gate of the existing trench MOSFET is lower than the top of the source region in the epitaxial layer, and a contact hole for filling the contact plug is formed by a non-self-aligned process. The contact hole is connected to the trench gate. The distance between poles is controlled by the precision of layout design and photolithography process. As the feature size of devices continues to shrink, fluctuations in the feature size of contact holes or the accuracy of photolithography overlays lead to device failure caused by the distance between the contact hole and the trench gate being too close, and the injection area at the bottom of the contact hole is close to the channel area of the MOSFET. Device parameters fluctuate.

In order to solve the above problems, this application provides a self-aligned trench MOSFET and a manufacturing method thereof.

Please refer to FIG. 2 , which shows a flow chart of a manufacturing method of a self-aligned trench MOSFET provided by an embodiment of the present application.

As shown in Figure 2, the manufacturing method of the self-aligned trench MOSFET includes the following steps:

Step S1: Provide a substrate, form an epitaxial layer on the substrate, and form a hard mask layer on the epitaxial layer;

Step S2, forming multiple trenches in the epitaxial layer;

Step S3, sequentially forming a gate dielectric layer and a gate electrode layer in the trench, with the top of the gate electrode layer being higher than the top surface of the epitaxial layer;

Step S4: After removing the hard mask layer, perform body region implantation and source region implantation on the epitaxial layer in sequence;

Step S5, forming sidewalls on both sides of the portion of the gate layer that is higher than the epitaxial layer;

Step S6: After forming the self-aligned contact hole through the self-alignment process, fill the self-aligned contact hole with a metal plug.

In step S1, optionally, the substrate is a silicon substrate, a germanium substrate, a silicon-on-insulator substrate, etc.; or the material of the substrate may also include other materials, such as III-V compounds such as gallium arsenide. Those skilled in the art can select the constituent material of the substrate according to the type of device structure formed on the substrate, so the type of substrate should not limit the scope of protection of the present invention.

For example, as shown in FIG. 3A , an epitaxial growth process is used to form an epitaxial layer 300 on a substrate (not shown in the figure). The material of the epitaxial layer 300 and the substrate may be the same or different.

Exemplarily, the hard mask layer 301 is formed on the epitaxial layer 300 through a deposition process. In order to make the top of the subsequently formed trench gate higher than the top surface of the epitaxial layer 300, the thickness of the hard mask layer 301 is preferably 500 angstroms to 6000 angstroms. The thickness of the hard mask layer 301 is too small, which is not conducive to controlling the topography of the trench gate higher than the epitaxial layer 300; the thickness of the hard mask layer 301 is too large, causing the top of the trench gate to be higher than the epitaxial layer 300. Too much top affects device performance, and the cost of removing the hard mask layer 301 also increases significantly, which is not conducive to cost reduction and efficiency improvement of the manufacturing process.

For example, the material of the hard mask layer 301 is oxide or a stacked structure composed of oxide-nitride-oxide.

In step S2, as shown in FIG. 3B, a plurality of trenches 302 are formed in the epitaxial layer 300.

As an example, the steps of forming the trench 302 include: coating photoresist on the surface of the hard mask layer 301 and using a photolithography process to define the formation area of the trench 302; using the photoresist as a mask to mask the hard mask layer 301 Etching is performed, and the etching process removes the hard mask layer 301 located in the formation area and retains the hard mask layer 301 outside the formation area; removes the photoresist, and uses the hard mask layer 301 as a mask to mask the epitaxial layer. 300 is etched to form trench 302.

In step S3, as shown in FIG. 3C, a gate dielectric layer 303 is first formed on the inner surface of the trench 302 located in the epitaxial layer 300, and then the gate layer 305 is filled in the trench 302 where the gate dielectric layer 303 is formed.

As an example, the material of the gate dielectric layer 303 includes silicon oxide, and the material of the gate electrode layer 305 includes silicon oxide.

Exemplarily, a thermal oxidation process is used to form the gate dielectric layer 303; after a deposition process is used to form the gate electrode layer 305, an etching back or a chemical mechanical polishing process or a combination of the two is performed to remove the gate electrode layer located on the hard mask layer 301. 305, and make the top of the gate layer 305 higher than the top surface of the epitaxial layer 300.

For example, the vertical distance between the top of the gate layer 305 and the top surface of the epitaxial layer 300 is 500 angstroms to 3000 angstroms. The distance is too small, which is not conducive to subsequent control of the self-aligned process to form the morphology of the self-aligned contact hole. The distance is too large, which will affect device performance.

In step S4, as shown in FIG. 3D, after removing the hard mask layer 301, body region implantation and source region implantation are sequentially performed on the epitaxial layer 300, and the body region 306 and the source region 307 are respectively formed in the epitaxial layer 300.

As an example, the hard mask layer 301 is removed through a dry etching process that has high selectivity for the hard mask layer 301 compared to the gate layer 305 .

Before performing body region implantation, a shielding oxide layer 308 is formed through a deposition process to cover the epitaxial layer 300 and the gate layer 305 to scatter ions before entering the epitaxial layer 300 to reduce the channel effect.

Taking N-type trench MOSFET as an example, the body region 306 formed by body region implantation is P-type, and the doped materials include B, In, Al, Ga plasma; the source region 307 formed by source region implantation is N+ type, and the doped material Substances include P, As, Sb plasma.

Before implementing the source region implantation, it also includes the step of implementing low thermal budget body region advancement to increase the effective channel length to suppress channel leakage. At the same time, it avoids the upward expansion of high-concentration doped materials in the epitaxial layer 300 and the effective epitaxial length. changes to ensure that the breakdown voltage of the device meets the requirements.

After the source region is implanted, an annealing step is also included to activate the doping material in the source region 307 .

In step S5 , as shown in FIG. 3E , spacers 309 are formed on both sides of the portion of the gate layer 305 that is higher than the epitaxial layer 300 .

As an example, the spacers 309 are formed through deposition combined with an etching process. For example, the material of the spacer 309 is preferably silicon nitride, because the etching process in the self-aligned process to form the contact hole subsequently has a high selectivity ratio for oxide and silicon nitride.

In step S6, as shown in FIG. 3F, after forming the self-aligned contact hole through the self-alignment process, the metal plug 310 is filled in the self-aligned contact hole.

First, a pre-metal deposition dielectric (PMD) layer 311 is formed on the epitaxial layer 300 through a deposition process. Next, due to the presence of the spacers 309, self-aligned contact holes can be formed through photolithography and etching processes. This etching process has a high selectivity ratio for the PMD layer 311 and the spacers 309. Therefore, the material of the PMD layer 311 is preferably oxide, and the material of the spacers 309 is preferably silicon nitride. Those skilled in the art can know that the PMD layer 311 Other materials can also be selected for the sidewalls 309 and the PMD layer 311 and the sidewalls 309 , as long as the etching process requires a high selectivity ratio for the PMD layer 311 and the sidewalls 309 .

Next, contact hole implantation is performed to form the doped region 312, and annealing is performed to activate the doped material in the doped region 312. Taking N-type trench MOSFET as an example, the doping region 312 is P+ type, and the doping material includes B, In, Al, Ga plasma.

Then, a barrier metal layer (not shown in the figure) is formed on the inner wall of the self-aligned contact hole, and the metal plug 310 is filled in the self-aligned contact hole. For example, the material of the barrier metal layer includes titanium nitride, and the material of the metal plug 310 includes tungsten. The follow-up is conventional metal interconnection and thick processing.

Embodiments of the present application also provide a self-aligned trench MOSFET. As shown in Figure 3F, the top of the gate layer 305 constituting the trench gate is higher than the epitaxial layer 300, and the gate layer 305 is higher than the epitaxial layer 300. The height of the gate layer 305 is 500 angstroms to 3000 angstroms, and spacers 309 are formed on both sides of the portion of the gate layer 305 that is higher than the epitaxial layer 300 .

In summary, the self-aligned trench MOSFET and its manufacturing method provided in this application can form a self-aligned trench contact due to the existence of the sidewalls 309 on both sides of the portion of the gate layer 305 that is higher than the epitaxial layer 300 holes, in the manufacturing process of small-pitch trench MOSFETs, to avoid fluctuations in the characteristic size of the contact holes or the accuracy of photolithography overlays, which may cause device failure due to the close distance between the contact holes and the trench gates, and also to avoid the contact hole bottom injection area being close to the MOSFET The channel region causes fluctuations in device parameters. Therefore, the present application effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present application in a schematic manner, and the drawings only show the components related to the present invention and do not follow the actual implementation of the component numbers, shapes and components. Dimension drawing, in actual implementation, the type, quantity and proportion of each component can be arbitrarily changed, and the component layout type may also be more complex.

The above embodiments only illustrate the principles and effects of the present application, but are not used to limit the present application. Anyone familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed in the present invention shall still be covered by the claims of this application.

Claims (17)

1. A method of manufacturing a self-aligned trench MOSFET, characterized in that the method includes: Step S1, providing a substrate, forming an epitaxial layer on the substrate, and forming a hard mask layer on the epitaxial layer; Step S2, forming multiple trenches in the epitaxial layer; Step S3, sequentially forming a gate dielectric layer and a gate electrode layer in the trench, with the top of the gate layer being higher than the top surface of the epitaxial layer; Step S4: After removing the hard mask layer, perform body region implantation and source region implantation on the epitaxial layer in sequence; Step S5, forming spacers on both sides of the portion of the gate layer that is higher than the epitaxial layer; Step S6: After forming a self-aligned contact hole through a self-alignment process, fill the self-aligned contact hole with a metal plug. 2. The method of claim 1, wherein a vertical distance between the top of the gate layer and the top surface of the epitaxial layer is 500 angstroms to 3000 angstroms. 3. The method of claim 1, wherein the hard mask layer is made of an oxide or a stacked structure composed of oxide-nitride-oxide. 4. The method of claim 1, wherein the step of forming the trench includes: coating photoresist on the surface of the hard mask layer and using a photolithography process to define the formation of the trench. area; use the photoresist as a mask to etch the hard mask layer; remove the photoresist, and use the hard mask layer as a mask to etch the epitaxial layer to form the trench. 5. The method of claim 1, wherein in step S3, the gate dielectric layer is first formed on the inner surface of the trench located in the epitaxial layer, and then the gate dielectric layer is formed. The gate layer is filled in the trench of the gate dielectric layer. 6. The method according to claim 1 or 5, characterized in that the gate dielectric layer is formed using a thermal oxidation process. 7. The method according to claim 1 or 5, characterized in that after forming the gate layer using a deposition process, an etching back or a chemical mechanical polishing process or a combination of the two is performed to remove the hard mask layer. on the gate layer, and make the top of the gate layer higher than the top surface of the epitaxial layer. 8. The method of claim 1, wherein before performing the body region implantation, a shielding oxide layer is formed through a deposition process to cover the epitaxial layer and the gate layer. 9. The method according to claim 1, characterized in that before performing the source region implantation, it further includes the step of implementing a low thermal budget body region advancement. 10. The method according to claim 1, wherein after implanting the source region, it further includes an annealing step to activate the doping material in the source region. 11. The method of claim 1, wherein the sidewalls are made of silicon nitride. 12. The method of claim 1, wherein the step of forming the self-aligned contact hole includes: first forming a dielectric layer before metal deposition on the epitaxial layer through a deposition process, and then using light to Engraving and etching processes form the self-aligned contact holes. 13. The method of claim 12, wherein the material of the dielectric layer before metal deposition is an oxide. 14. The method of claim 12, wherein the etching has a high selectivity ratio for the dielectric layer before metal deposition and the spacers. 15. The method of claim 1, wherein after forming the self-aligned contact hole and before filling the metal plug, the method further includes performing contact hole implantation to form a doped region and performing annealing to activate the doping. The step of doping substances in the region. 16. A self-aligned trench MOSFET manufactured according to the method of any one of claims 1 to 15, characterized in that the top of the gate layer constituting the trench gate is higher than the epitaxial layer, and the gate Sidewalls are formed on both sides of the portion of the layer that is higher than the epitaxial layer. 17. The self-aligned trench MOSFET according to claim 16, wherein the height of the portion of the gate layer higher than the epitaxial layer is 500 angstroms to 3000 angstroms.