CN110311668B - Chip output pin forward overvoltage and reverse voltage protection circuit and method - Google Patents
Chip output pin forward overvoltage and reverse voltage protection circuit and method Download PDFInfo
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- CN110311668B CN110311668B CN201910605777.3A CN201910605777A CN110311668B CN 110311668 B CN110311668 B CN 110311668B CN 201910605777 A CN201910605777 A CN 201910605777A CN 110311668 B CN110311668 B CN 110311668B
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- H—ELECTRICITY
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09421—Diode field-effect transistor logic
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Abstract
The embodiment of the invention discloses a chip output pin overvoltage and reverse connection protection circuit and a method, when the voltage of a chip output pin is positioned between a power supply end VDD and a wire grounding end GND, a forward overvoltage protection circuit and a reverse voltage protection circuit do not work, a chip is in a normal working state, and if an electrostatic discharge phenomenon occurs on the output pin, a current is conducted to the wire grounding end GND by an ESD protection circuit, so that an internal circuit is protected; when the voltage of the output pin of the chip is pulled to be higher than the normal voltage range, the forward overvoltage protection circuit starts to work and is in a high-resistance state, so that the internal circuit of the chip is prevented from being damaged by overhigh voltage; when the voltage of the output pin of the chip is pulled low, the reverse voltage protection circuit starts to work and is placed in a high-impedance state, so that the internal circuit of the chip is protected. The invention realizes the protection of the internal circuit of the chip when the voltage of the output pin of the chip is overhigh or is reversely connected, only increases the current of a few microamperes when the chip normally works, and has low power consumption.
Description
Technical Field
The embodiment of the invention relates to the technical field of integrated circuits, in particular to a chip output pin forward overvoltage and reverse voltage protection circuit.
Background
At present, in high-reliability applications such as automobiles, medical treatment, aerospace and the like, an output pin of an integrated circuit is required to have forward overvoltage and reverse voltage protection. For example, in an automotive sensor chip application, the output of the sensor chip is connected to the ECU through a wire harness and pulled up to a power supply voltage through a resistor, and during actual use, due to environmental influences or human errors, power supply overvoltage and reverse connection of the chip output pin to ground occur. As well as the engine ignition process in automotive electronics, the 5V power supply provided by the system often rises momentarily to 12V or even higher. In order to protect the integrated circuit, the output pin of the integrated circuit chip is required to have the functions of overvoltage and reverse voltage protection.
In the prior art, the overvoltage protection circuit function of the output pin of the integrated circuit chip is realized by a pin external series resistor. The voltage resistance is determined by the resistance value of the series resistor, the larger the resistance value is, the higher the voltage resistance is, but the series resistor and the pull-up resistor at the ECU end form voltage division, so that the analog signal output by the chip is deviated; when the resistance value of the series resistor is small, the voltage-resisting effect is not obvious. Meanwhile, this method cannot perform reverse voltage protection on the output pin. With the improvement of the requirement on reliability, many applications require that an overvoltage and reverse voltage protection circuit is built in an output pin of an integrated circuit, and meanwhile, the protection circuit can not influence the ESD index of the output pin of the integrated circuit as an output end. With the increasing demand for low power consumption circuits, especially for applications such as sensors, it is also required that the overvoltage and reverse voltage protection circuit has low power consumption in normal operation in addition to providing protection. A technical scheme for protecting the output pins of the chip from forward overvoltage and reverse voltage is needed.
Disclosure of Invention
Therefore, the embodiment of the invention provides a chip output pin forward overvoltage and reverse voltage protection circuit, which realizes the protection of the internal circuit of a chip when the voltage of the chip output pin is overhigh or reversely connected and has low power consumption in normal work.
In order to achieve the above object, the embodiments of the present invention provide the following technical solutions: a chip output pin overvoltage and reverse connection protection circuit comprises a power supply end VDD, a signal input end Vsig, a signal output end Vout, an electric wire grounding end GND, a forward overvoltage protection circuit, a reverse voltage protection circuit and an ESD protection circuit;
the forward overvoltage protection circuit comprises a high-voltage NMOS tube M1, a high-voltage PMOS tube M2, a high-voltage PMOS tube M3, a Zener diode D1, a resistor R1 and a resistor R2; the ESD protection circuit comprises a high-voltage NMOS tube M4, a high-voltage NMOS tube M5 and a high-voltage PMOS tube M6; the reverse voltage protection circuit comprises a high-voltage NMOS tube M7, a Zener diode D2, a resistor R3 and a resistor R4;
the grid electrode of the high-voltage NMOS tube M1 is connected with the power supply end VDD, the source electrode of the high-voltage NMOS tube M1 is connected with the signal input end Vsig, and the drain electrode of the high-voltage NMOS tube M1 is connected with the drain electrode of the high-voltage NMOS tube M5; the grid electrode of the high-voltage PMOS tube M2 is connected with the drain electrode of the high-voltage PMOS tube M3, the source electrode of the high-voltage PMOS tube M2 is connected with the drain electrode of the high-voltage NMOS tube M5, and the drain electrode of the high-voltage PMOS tube M2 is connected with the signal input end Vsig; the grid electrode of the high-voltage PMOS tube M3 is connected with the cathode of the Zener diode D1, the source electrode of the high-voltage PMOS tube M3 is connected with the drain electrode of the high-voltage NMOS tube M5, and the drain electrode of the high-voltage PMOS tube M3 is connected with the anode of the resistor R2; the anode of the resistor R1 is connected with the drain of the high-voltage NMOS tube M5;
the grid electrode and the source electrode of the high-voltage NMOS tube M4 are respectively connected with the wire grounding end GND, the drain electrode of the high-voltage NMOS tube M4 is connected with the drain electrode of the high-voltage NMOS tube M5, and the source electrode of the high-voltage PMOS tube M6 is connected with the drain electrode of the high-voltage NMOS tube M5;
the grid electrode of the high-voltage NMOS tube M7 is connected with the anode of the Zener diode D2, the source electrode of the high-voltage NMOS tube M7 is connected with the source electrode of the high-voltage NMOS tube M5, and the drain electrode of the high-voltage NMOS tube M7 is connected with the grid electrode of the high-voltage NMOS tube M5; the positive electrode of the resistor R3 is connected with the grid electrode of the high-voltage NMOS tube M7; the anode of the resistor R4 is connected with the cathode of the Zener diode D2.
As a preferred scheme of the chip output pin overvoltage and reverse connection protection circuit, the anode of the resistor R1 is connected with the drain of the high-voltage NMOS tube M5, and the cathode of the resistor R1 is connected with the grid of the high-voltage PMOS tube M3.
As a preferred scheme of the chip output pin overvoltage and reverse connection protection circuit, the anode of the resistor R2 is connected with the drain of the high-voltage PMOS tube M3, and the cathode of the resistor R2 is connected with the ground end GND of the wire.
As a preferred scheme of the chip output pin overvoltage and reverse connection protection circuit, the gate of the high-voltage NMOS transistor M5 is connected to the drain of the high-voltage NMOS transistor M7, the source of the high-voltage NMOS transistor M5 is connected to the signal output terminal Vout, and the drain of the high-voltage NMOS transistor M5 is connected to the source of the high-voltage PMOS transistor M6.
As a preferred scheme of the chip output pin overvoltage and reverse connection protection circuit, the grid of the high-voltage PMOS transistor M6 is connected with the ground end GND of the electric wire, the source of the high-voltage PMOS transistor M6 is connected with the drain of the high-voltage NMOS transistor M5, and the drain of the high-voltage PMOS transistor M6 is connected with the source of the high-voltage NMOS transistor M5.
As the preferred scheme of the chip output pin overvoltage and reverse connection protection circuit, the anode of the Zener diode D2 is connected with the grid of the high-voltage NMOS tube M7, and the cathode of the Zener diode D2 is connected with the power supply end VDD.
As a preferred scheme of the chip output pin overvoltage and reverse connection protection circuit, the anode of the resistor R3 is connected with the grid electrode of the high-voltage NMOS tube M7, and the cathode of the resistor R3 is connected with the source electrode of the high-voltage NMOS tube M5.
As a preferred scheme of the chip output pin overvoltage and reverse connection protection circuit, the anode of the resistor R4 is connected with the cathode of the Zener diode D2, and the cathode of the resistor R4 is connected with the grid of the high-voltage NMOS tube M5.
The embodiment of the invention also provides a chip output pin overvoltage and reverse connection protection method, the protection method adopts the protection circuit, the protection circuit comprises a power supply end VDD, a signal input end Vsig, a signal output end Vout, a wire grounding end GND, a forward overvoltage protection circuit, a reverse voltage protection circuit and an ESD protection circuit, when the working voltage of the chip output pin is between the power supply end VDD and the wire grounding end GND voltage, the forward overvoltage protection circuit and the reverse voltage protection circuit do not work, and when the chip output pin has static electricity release, the chip output pin is transmitted to the wire grounding end GND through the ESD protection circuit; when the working voltage of the chip output pin is greater than the VDD voltage of a power supply end, the forward overvoltage protection circuit starts to work in a high-resistance state; when the working voltage of the chip output pin is lower than the GND voltage of the wire grounding end, the reverse voltage protection circuit starts to work in a high-impedance state.
When the voltage of an output pin of the chip is within a normal voltage range (between a power supply end VDD and a wire grounding end GND), the forward overvoltage protection circuit and the reverse voltage protection circuit do not work, the chip is in a normal working state, and if an electrostatic discharge phenomenon occurs on the output pin, the ESD protection circuit conducts current to the wire grounding end GND, so that an internal circuit is protected; when the voltage of the output pin of the chip is pulled to be higher than the normal voltage range (larger than a power supply end VDD), the forward overvoltage protection circuit starts to work and is in a high-impedance state, so that the internal circuit of the chip is prevented from being damaged by overhigh voltage; when the voltage of the chip output pin is pulled low (lower than the ground GND of the wire), the reverse voltage protection circuit starts to work and is placed in a high-impedance state, so that the internal circuit of the chip is protected. The invention realizes the protection of the internal circuit of the chip when the voltage of the output pin of the chip is overhigh or is reversely connected, and only a few microamperes of current is increased during normal work.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.
Fig. 1 is a schematic diagram of a chip output pin overvoltage and reverse connection protection circuit provided in an embodiment of the present invention.
Detailed Description
The present invention is described in terms of particular embodiments, other advantages and features of the invention will become apparent to those skilled in the art from the following disclosure, and it is to be understood that the described embodiments are merely exemplary of the invention and that it is not intended to limit the invention to the particular embodiments disclosed. All other embodiments, which can be obtained by a person skilled in the art without making any creative effort based on the embodiments in the present invention, belong to the protection scope of the present invention.
As known to those skilled in the art, a "high impedance state" is one state of a tri-state gate. The output of the logic gate has a high state and a low state, and also has a high impedance state in a third state, wherein the high impedance state is neither a high level nor a low level. When the high-impedance state is input into the next circuit, the low-impedance state has no influence on the next circuit, and the high level or the low level is possible if the high-impedance state is measured by a multimeter and is determined by the circuit connected behind the high-impedance state.
Referring to fig. 1, an overvoltage and reverse connection protection circuit for a chip output pin is provided, which includes a power terminal VDD, a signal input terminal Vsig, a signal output terminal Vout, a wire ground terminal GND, a forward overvoltage protection circuit, a reverse voltage protection circuit, and an ESD protection circuit. The forward overvoltage protection circuit comprises a high-voltage NMOS tube M1, a high-voltage PMOS tube M2, a high-voltage PMOS tube M3, a Zener diode D1, a resistor R1 and a resistor R2; the ESD protection circuit comprises a high-voltage NMOS tube M4, a high-voltage NMOS tube M5 and a high-voltage PMOS tube M6; the reverse voltage protection circuit comprises a high-voltage NMOS tube M7, a Zener diode D2, a resistor R3 and a resistor R4.
In the forward overvoltage protection circuit, the grid electrode of the high-voltage NMOS tube M1 is connected with the power supply end VDD, the source electrode of the high-voltage NMOS tube M1 is connected with the signal input end Vsig, and the drain electrode of the high-voltage NMOS tube M1 is connected with the drain electrode of the high-voltage NMOS tube M5; the grid electrode of the high-voltage PMOS tube M2 is connected with the drain electrode of the high-voltage PMOS tube M3, the source electrode of the high-voltage PMOS tube M2 is connected with the drain electrode of the high-voltage NMOS tube M5, and the drain electrode of the high-voltage PMOS tube M2 is connected with the signal input end Vsig; the grid electrode of the high-voltage PMOS tube M3 is connected with the cathode of the Zener diode D1, the source electrode of the high-voltage PMOS tube M3 is connected with the drain electrode of the high-voltage NMOS tube M5, and the drain electrode of the high-voltage PMOS tube M3 is connected with the anode of the resistor R2; the positive electrode of the resistor R1 is connected with the drain electrode of the high-voltage NMOS tube M5, and the negative electrode of the resistor R1 is connected with the grid electrode of the high-voltage PMOS tube M3. The positive pole of the resistor R2 is connected with the drain electrode of the high-voltage PMOS tube M3, and the negative pole of the resistor R2 is connected with the ground end GND of the wire.
In the ESD protection circuit, the grid electrode and the source electrode of the high-voltage NMOS tube M4 are respectively connected with the ground end GND of the wire, the drain electrode of the high-voltage NMOS tube M4 is connected with the drain electrode of the high-voltage NMOS tube M5, and the source electrode of the high-voltage PMOS tube M6 is connected with the drain electrode of the high-voltage NMOS tube M5. The grid electrode of the high-voltage NMOS tube M5 is connected with the drain electrode of the high-voltage NMOS tube M7, the source electrode of the high-voltage NMOS tube M5 is connected with the signal output end Vout, and the drain electrode of the high-voltage NMOS tube M5 is connected with the source electrode of the high-voltage PMOS tube M6. The grid electrode of the high-voltage PMOS tube M6 is connected with the ground end GND of the wire, the source electrode of the high-voltage PMOS tube M6 is connected with the drain electrode of the high-voltage NMOS tube M5, and the drain electrode of the high-voltage PMOS tube M6 is connected with the source electrode of the high-voltage NMOS tube M5.
In the reverse voltage protection circuit, the grid electrode of the high-voltage NMOS tube M7 is connected with the anode of the Zener diode D2, the source electrode of the high-voltage NMOS tube M7 is connected with the source electrode of the high-voltage NMOS tube M5, and the drain electrode of the high-voltage NMOS tube M7 is connected with the grid electrode of the high-voltage NMOS tube M5; the positive electrode of the resistor R3 is connected with the grid electrode of the high-voltage NMOS tube M7, and the negative electrode of the resistor R3 is connected with the source electrode of the high-voltage NMOS tube M5; the anode of the resistor R4 is connected with the cathode of the Zener diode D2, and the cathode of the resistor R4 is connected with the grid of the high-voltage NMOS tube M5. The anode of the zener diode D2 is connected with the grid of the high-voltage NMOS tube M7, and the cathode of the zener diode D2 is connected with the power supply end VDD.
Specifically, the positive overvoltage protection circuit is used for cutting off external high voltage and internal circuits of the chip when the output pin of the chip is pulled to be higher than the bearing value of the chip, so that the internal circuits of the chip are prevented from being damaged by the positive high voltage. When the voltage of the signal output end Vout of the chip output pin is within a normal range (between the power supply end VDD and the wire ground end GND), since the steady voltage of the zener diode D1 is greater than or equal to the voltage of the power supply end VDD of the normal operation of the chip, the zener diode D1 is turned off, the gate of the high-voltage PMOS transistor M3 is pulled up by the resistor R1 to approach the source voltage of the high-voltage PMOS transistor M3, the high-voltage PMOS transistor M3 is turned off, the gate of the high-voltage PMOS transistor M2 is pulled down by the resistor R2 to the ground wire ground end GND, while the gate level power supply end VDD of the high-voltage NMOS transistor M1 is greater than Vsig, the pass gate formed by the high-voltage PMOS transistor M2 and the high-voltage NMOS transistor M1 is turned on, while the gate of the zener diode D2 is turned off since the steady voltage of the diode D2 is greater than or equal to the power supply end VDD of the normal operation of the chip, the gate of the high-voltage NMOS transistor M7 is pulled down by the resistor R4 to the vicinity of the signal output end Vout, the high-voltage NMOS transistor M7 is in a turned off state, the gate of the high-voltage NMOS transistor M5 is pulled up by the zener diode R4 to the power supply end VDD, while the gate of the high-voltage NMOS transistor M6 is less than the gate of the normal operation pin, and the pass gate of the high-voltage PMOS transistor M6, and the pass gate of the output pin, the normal operation of the output pin Vout, the chip output pin, and the pass gate of the normal operation of the chip output pin, which can be turned on; when the voltage of the output pin Vout of the chip is pulled to be higher than the normal working voltage range of the chip, current flows from the Vout to the power supply end VDD through a forward parasitic diode from the source to the drain of the high-voltage NMOS tube M7 and the resistor R4, so that the high-voltage NMOS tube M5 and the high-voltage PMOS tube M6 are conducted, the drain voltage of the high-voltage NMOS tube M5 is close to the Vout, because the Vout is larger than the stable voltage of the Zener diode D1, the Zener diode D1 is conducted at the moment, current flows through the resistor R1, when the voltage at two ends of the resistor R1 is larger than the threshold voltage of the high-voltage PMOS tube M3, the high-voltage PMOS tube M3 is conducted, the positive electrode of the resistor R2 is pulled to be close to the Vout, and at the moment, the high-voltage PMOS tube M2 and the Vout are cut off, and because the level of the Vout is higher than the power supply end VDD, the high-voltage NMOS tube M1 is also in a cut-off state, and a transmission gate formed by the high-voltage NMOS tube M1 and the high-voltage PMOS tube M2 is in a high-resistance state, so that the internal circuit of the chip is prevented from being damaged by high voltage.
Specifically, the ESD protection circuit is used to protect the internal circuits of the chip when an electrostatic discharge phenomenon occurs. A parasitic forward diode exists from the drain electrode to the source electrode of the high-voltage PMOS tube M6, the substrate of the high-voltage NMOS tube M5 is connected with the source electrode of the high-voltage NMOS tube M5, a parasitic forward diode exists from the source electrode to the drain electrode of the high-voltage NMOS tube M5, static electricity does not need to wait for the conduction of the high-voltage NMOS tube M5 and the high-voltage PMOS tube M6, and the static electricity directly reaches the drain electrode of the high-voltage NMOS tube M4 through the 2 parasitic diodes; the high-voltage NMOS tube M4 is connected in a mode of grid grounding NMOS, the NMOS tube in the CMOS process is provided with a transverse parasitic n-p-n transistor, the parasitic transistor can absorb a large amount of current when being started, the transverse transistor of the high-voltage NMOS tube M4 cannot be conducted under the normal working condition, when the static electricity release phenomenon occurs, avalanche occurs in a drain electrode of the high-voltage NMOS tube M4 and a depletion region of a substrate, along with the generation of electron hole pairs, a part of generated holes are absorbed by a source electrode, and the rest of generated holes flow through the substrate, so that static electricity is released.
Specifically, the reverse voltage protection circuit is used for ensuring that the chip output pin is in a high-resistance state when being pulled lower than the wire grounding end GND, so that the internal circuit of the chip is ensured not to be damaged by reverse voltage. The working principle of the reverse voltage protection circuit is as follows: when the voltage of the chip output pin Vout is within a normal range (located between a power supply end VDD and a wire grounding end GND), because the stable voltage of the zener diode D2 is greater than or equal to the chip normal operating voltage power supply end VDD, the gate of the high-voltage NMOS transistor M7 is pulled down to near Vout by the resistor R3, the high-voltage NMOS transistor M7 is in a cut-off state, the gate of the high-voltage NMOS transistor M5 is pulled up to the power supply end VDD by the resistor R4, the high-voltage NMOS transistor M5 is in a conduction state, meanwhile, because the gate level (GND) of the high-voltage PMOS transistor M6 is lower than Vout, the transmission gate formed by the high-voltage NMOS transistor M5 and the high-voltage PMOS transistor M6 is turned on, and because the stable voltage of the zener diode D1 is greater than or equal to the chip normal operating voltage power supply end VDD, the gate of the high-voltage PMOS transistor M3 is pulled up to a voltage close to the source voltage of the high-voltage PMOS transistor M3 by the resistor R1, the high-voltage PMOS transistor M3 is cut-off, the gate GND of M2 is pulled down to ground, the transmission gate formed by the high-voltage PMOS transistor M2 and the high-voltage NMOS transistor M1 are also turned on, and the internal output pin Vout can be normally output to the chip Vout; when the voltage of the output pin Vout of the chip is pulled down to be lower than the ground GND, the voltage between the power supply end VDD and Vout is larger than the stable voltage of the Zener diode D2, the Zener diode D2 is conducted, at the moment, current flows through the resistor R3, the grid level of the high-voltage NMOS tube M7 is larger than the source level, the high-voltage NMOS tube M7 is in a conducting state, the grid of the high-voltage NMOS tube M5 is pulled down to Vout, the high-voltage NMOS tube M5 is in a stopping state, and meanwhile, as the grid voltage GND of the high-voltage PMOS tube M6 is larger than the Vout, the high-voltage PMOS tube M6 is also stopped, a transmission gate formed by the high-voltage NMOS tube M5 and the high-voltage PMOS tube M6 is in a high-resistance state, so that the internal circuit of the chip is not influenced by reverse voltage.
The embodiment of the invention also provides a chip output pin overvoltage and reverse connection protection method, which adopts the protection circuit, wherein the protection circuit comprises a power supply end VDD, a signal input end Vsig, a signal output end Vout, an electric wire grounding end GND, a forward overvoltage protection circuit, a reverse voltage protection circuit and an ESD protection circuit; when the working voltage of the chip output pin is greater than the voltage of a power supply end VDD, the forward overvoltage protection circuit starts to work and is in a high-impedance state; when the working voltage of the chip output pin is lower than the GND voltage of the wire grounding end, the reverse voltage protection circuit starts to work in a high-impedance state. When the voltage of an output pin of the chip is within a normal voltage range (between a power supply end VDD and a wire grounding end GND), the forward overvoltage protection circuit and the reverse voltage protection circuit do not work, the chip is in a normal working state, and if an electrostatic discharge phenomenon occurs on the output pin, the ESD protection circuit conducts current to the wire grounding end GND, so that an internal circuit is protected; when the voltage of the output pin of the chip is pulled to be higher than the normal voltage range (larger than a power supply end VDD), the forward overvoltage protection circuit starts to work and is in a high-impedance state, so that the internal circuit of the chip is prevented from being damaged by overhigh voltage; when the voltage of the chip output pin is pulled low (lower than the ground GND of the wire), the reverse voltage protection circuit starts to work and is placed in a high-impedance state, so that the internal circuit of the chip is protected. The invention realizes the protection of the internal circuit of the chip when the voltage of the output pin of the chip is overhigh or is reversely connected, and only a few microamperes of current is increased during normal work.
Although the invention has been described in detail above with reference to a general description and specific examples, it will be apparent to one skilled in the art that modifications or improvements may be made thereto based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.
Claims (5)
1. A chip output pin overvoltage and reverse connection protection circuit comprises a power supply end VDD, a signal input end Vsig, a signal output end Vout and a wire grounding end GND, and is characterized by further comprising a forward overvoltage protection circuit, a reverse voltage protection circuit and an ESD protection circuit;
the forward overvoltage protection circuit comprises a high-voltage NMOS tube M1, a high-voltage PMOS tube M2, a high-voltage PMOS tube M3, a Zener diode D1, a resistor R1 and a resistor R2; the ESD protection circuit comprises a high-voltage NMOS tube M4, a high-voltage NMOS tube M5 and a high-voltage PMOS tube M6; the reverse voltage protection circuit comprises a high-voltage NMOS tube M7, a Zener diode D2, a resistor R3 and a resistor R4;
the grid electrode of the high-voltage NMOS tube M1 is connected with the power supply end VDD, the source electrode of the high-voltage NMOS tube M1 is connected with the signal input end Vsig, and the drain electrode of the high-voltage NMOS tube M1 is connected with the drain electrode of the high-voltage NMOS tube M5; the grid electrode of the high-voltage PMOS tube M2 is connected with the drain electrode of the high-voltage PMOS tube M3, the source electrode of the high-voltage PMOS tube M2 is connected with the drain electrode of the high-voltage NMOS tube M5, and the drain electrode of the high-voltage PMOS tube M2 is connected with the signal input end Vsig; the grid electrode of the high-voltage PMOS tube M3 is connected with the cathode of the Zener diode D1, the source electrode of the high-voltage PMOS tube M3 is connected with the drain electrode of the high-voltage NMOS tube M5, and the drain electrode of the high-voltage PMOS tube M3 is connected with the anode of the resistor R2; the anode of the resistor R1 is connected with the drain of the high-voltage NMOS tube M5;
the grid electrode and the source electrode of the high-voltage NMOS tube M4 are respectively connected with the wire grounding end GND, the drain electrode of the high-voltage NMOS tube M4 is connected with the drain electrode of the high-voltage NMOS tube M5, and the source electrode of the high-voltage PMOS tube M6 is connected with the drain electrode of the high-voltage NMOS tube M5;
the grid electrode of the high-voltage NMOS tube M7 is connected with the anode of the Zener diode D2, the source electrode of the high-voltage NMOS tube M7 is connected with the source electrode of the high-voltage NMOS tube M5, and the drain electrode of the high-voltage NMOS tube M7 is connected with the grid electrode of the high-voltage NMOS tube M5; the positive electrode of the resistor R3 is connected with the grid electrode of the high-voltage NMOS tube M7; the anode of the resistor R4 is connected with the cathode of the Zener diode D2;
the anode of the Zener diode D1 is connected with the cathode of the resistor R2; the anode of the Zener diode D1 is also connected with the grounding end GND of the electric wire;
the positive electrode of the resistor R1 is connected with the drain electrode of the high-voltage NMOS tube M5, and the negative electrode of the resistor R1 is connected with the grid electrode of the high-voltage PMOS tube M3;
the positive electrode of the resistor R2 is connected with the drain electrode of the high-voltage PMOS tube M3, and the negative electrode of the resistor R2 is connected with the ground end GND of the wire;
the positive electrode of the resistor R3 is connected with the grid electrode of the high-voltage NMOS tube M7, and the negative electrode of the resistor R3 is connected with the source electrode of the high-voltage NMOS tube M5;
the anode of the resistor R4 is connected with the cathode of the Zener diode D2, and the cathode of the resistor R4 is connected with the grid of the high-voltage NMOS tube M5.
2. The over-voltage and reverse-connection protection circuit for the chip output pin according to claim 1, wherein a gate of the high-voltage NMOS transistor M5 is connected to a drain of the high-voltage NMOS transistor M7, a source of the high-voltage NMOS transistor M5 is connected to the signal output terminal Vout, and a drain of the high-voltage NMOS transistor M5 is connected to a source of the high-voltage PMOS transistor M6.
3. The chip output pin overvoltage and reverse connection protection circuit according to claim 1, wherein a gate of the high voltage PMOS transistor M6 is connected to a ground GND of the wire, a source of the high voltage PMOS transistor M6 is connected to a drain of the high voltage NMOS transistor M5, and a drain of the high voltage PMOS transistor M6 is connected to a source of the high voltage NMOS transistor M5.
4. The protection circuit for over-voltage and reverse connection of the chip output pin according to claim 1, wherein an anode of the zener diode D2 is connected to the gate of the high voltage NMOS transistor M7, and a cathode of the zener diode D2 is connected to the power supply terminal VDD.
5. A chip output pin overvoltage and reverse connection protection method, the protection method adopts the protection circuit of any claim 1 to 4, the protection circuit includes power end VDD, signal input end Vsig, signal output end Vout, wire ground GND, forward overvoltage protection circuit, reverse voltage protection circuit and ESD protection circuit, characterized in that when the working voltage of the chip output pin is between the voltage of the power end VDD and the wire ground GND, the forward overvoltage protection circuit and the reverse voltage protection circuit do not work, and when there is static discharge on the chip output pin, the working voltage is transmitted to the wire ground GND through the ESD protection circuit; when the working voltage of the chip output pin is greater than the VDD voltage of a power supply end, the forward overvoltage protection circuit starts to work in a high-resistance state; when the working voltage of the chip output pin is lower than the GND voltage of the wire grounding end, the reverse voltage protection circuit starts to work in a high-impedance state.
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| CN113359063B (en) * | 2021-06-09 | 2024-04-12 | 赛卓电子科技(上海)股份有限公司 | Open circuit detection circuit with reverse connection protection |
| CN114284990B (en) * | 2021-12-29 | 2025-02-18 | 琻捷电子科技(江苏)股份有限公司 | Overvoltage protection circuit and device |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101212134A (en) * | 2006-12-28 | 2008-07-02 | 华润矽威科技（上海）有限公司 | Over-voltage protection circuit for boosting-type switching power supply |
| CN101980363A (en) * | 2010-08-31 | 2011-02-23 | 电子科技大学 | A controllable self-clamping SensorFET composite lateral power device |
| CN102280871A (en) * | 2011-07-29 | 2011-12-14 | 惠州市德赛汽车电子有限公司 | Preposed overvoltage protection circuit |
| CN103713538A (en) * | 2014-01-06 | 2014-04-09 | 杭州柏年光电标饰有限公司 | LED guiding sign controller |
| CN104253410A (en) * | 2014-09-11 | 2014-12-31 | 北京大学 | Overvoltage breakdown preventing type input-stage ESD (Electronic Static Discharge) protection circuit |
| CN104283201A (en) * | 2014-09-11 | 2015-01-14 | 北京大学 | Input stage ESD protection circuit |
| CN204559094U (en) * | 2014-11-25 | 2015-08-12 | 广东金莱特电器股份有限公司 | A kind of DC interface circuit with overvoltage and polarity protection |
| CN105470926A (en) * | 2015-12-14 | 2016-04-06 | 无锡中感微电子股份有限公司 | Cascaded battery protection circuit and system |
| CN107181396A (en) * | 2017-05-05 | 2017-09-19 | 北京精密机电控制设备研究所 | A kind of paralleling MOS Guan Junliu and short-circuit protection circuit |
| CN206671932U (en) * | 2017-03-30 | 2017-11-24 | 鑫雁电子科技（上海）有限公司 | Wide input voltage range voltage adjustment chip provided with reverse-connection protection circuit |
| CN107707236A (en) * | 2017-11-02 | 2018-02-16 | 成都冠深科技有限公司 | Intelligence power supply overvoltage protection intelligent-induction for electric drawer slide rail closes circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101039027B (en) * | 2007-05-10 | 2010-05-26 | 北京中星微电子有限公司 | Improved electrostatic discharge protection circuit |
| US9231565B2 (en) * | 2013-05-14 | 2016-01-05 | Infineon Technologies Austria Ag | Circuit with a plurality of bipolar transistors and method for controlling such a circuit |
-
2019
- 2019-07-05 CN CN201910605777.3A patent/CN110311668B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101212134A (en) * | 2006-12-28 | 2008-07-02 | 华润矽威科技（上海）有限公司 | Over-voltage protection circuit for boosting-type switching power supply |
| CN101980363A (en) * | 2010-08-31 | 2011-02-23 | 电子科技大学 | A controllable self-clamping SensorFET composite lateral power device |
| CN102280871A (en) * | 2011-07-29 | 2011-12-14 | 惠州市德赛汽车电子有限公司 | Preposed overvoltage protection circuit |
| CN103713538A (en) * | 2014-01-06 | 2014-04-09 | 杭州柏年光电标饰有限公司 | LED guiding sign controller |
| CN104253410A (en) * | 2014-09-11 | 2014-12-31 | 北京大学 | Overvoltage breakdown preventing type input-stage ESD (Electronic Static Discharge) protection circuit |
| CN104283201A (en) * | 2014-09-11 | 2015-01-14 | 北京大学 | Input stage ESD protection circuit |
| CN204559094U (en) * | 2014-11-25 | 2015-08-12 | 广东金莱特电器股份有限公司 | A kind of DC interface circuit with overvoltage and polarity protection |
| CN105470926A (en) * | 2015-12-14 | 2016-04-06 | 无锡中感微电子股份有限公司 | Cascaded battery protection circuit and system |
| CN206671932U (en) * | 2017-03-30 | 2017-11-24 | 鑫雁电子科技（上海）有限公司 | Wide input voltage range voltage adjustment chip provided with reverse-connection protection circuit |
| CN107181396A (en) * | 2017-05-05 | 2017-09-19 | 北京精密机电控制设备研究所 | A kind of paralleling MOS Guan Junliu and short-circuit protection circuit |
| CN107707236A (en) * | 2017-11-02 | 2018-02-16 | 成都冠深科技有限公司 | Intelligence power supply overvoltage protection intelligent-induction for electric drawer slide rail closes circuit |
Non-Patent Citations (2)
| Title |
|---|
| Low leakage 3×VDD-tolerant ESD detection circuit without deep N-well in a standard 90-nm low-voltage CMOS process;YANG ZhaoNian等;《Science China(Technological Sciences)》;20130801(第08期);101-107 * |
| 基于M51995A的开关电源设计;高建强等;《科技视界》;20110925(第06期);221-228 * |
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