CN110311668A - A kind of chip output pin forward direction over-voltage and reverse voltage protection circuit and method - Google Patents
A kind of chip output pin forward direction over-voltage and reverse voltage protection circuit and method Download PDFInfo
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- CN110311668A CN110311668A CN201910605777.3A CN201910605777A CN110311668A CN 110311668 A CN110311668 A CN 110311668A CN 201910605777 A CN201910605777 A CN 201910605777A CN 110311668 A CN110311668 A CN 110311668A
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- 230000005611 electricity Effects 0.000 claims description 11
- 238000005265 energy consumption Methods 0.000 abstract description 2
- 230000005540 biological transmission Effects 0.000 description 6
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
- H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
- H03K19/09421—Diode field-effect transistor logic
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- Semiconductor Integrated Circuits (AREA)
Abstract
The embodiment of the invention discloses a kind of chip output pin over-voltage and reverse-connection protection circuit and methods; when chip output pin voltage is located between power end VDD and electric wire ground terminal GND; positive overvoltage crowbar and reverse voltage protection circuit do not work; chip is in normal operating conditions; if there is Electro-static Driven Comb phenomenon on output pin at this time; electric current will be directed at electric wire ground terminal GND by esd protection circuit, to protect internal circuit；When chip output pin voltage is raised when normal voltage range, positive overvoltage crowbar start-up operation is placed in high-impedance state, so that too high voltages be avoided to damage chip internal circuits；When chip output pin voltage is pulled low, reverse voltage protection circuit start-up operation is placed in high-impedance state, to protect chip internal circuits.Protection to chip internal circuits when the present invention realizes chip output pin overtension or reversal connection, when normal work, only increases several microamperes of electric current, low in energy consumption.
Description
Technical field
The present embodiments relate to technical field of integrated circuits, and in particular to a kind of chip output pin forward direction over-voltage and anti-
To voltage protection circuit.
Background technique
Currently, in the application of the high reliability such as automobile, medical treatment, space flight, it is desirable that the output pin of integrated circuit has just
To over-voltage and reverse-voltage protection.Such as in the application of automobile sensor chip, the output of sensor chip is connected by bunch
It is connected to ECU and supply voltage is pulled to by resistance, in actual use, due to environment influence or human error, power supply
Over-voltage and chip output pin happen occasionally with ground reversal connection.The for another example engine ignition process in automotive electronics, what system provided
Often moment, to be increased to 12V even higher for 5V power supply.In order to protect integrated circuit, it is desirable that IC chip output pin tool
There are electric voltage over press and reverse voltage protection functions.
In the prior art, IC chip output pin overvoltage crowbar function is by pin external series resistance Lai real
It is existing.The height of pressure resistance is determined that resistance value is bigger, and pressure resistance is higher by the resistance value of series resistance, but due on series resistance meeting and the end ECU
Pull-up resistor forms partial pressure, and chip output analog signal can be made to cause to deviate；Series resistance value hour, pressure resistance effect are again unknown
It is aobvious.Meanwhile this method can not carry out reverse-voltage protection to output pin.With the raising to reliability requirement, Hen Duoying
With requiring over-voltage and reverse voltage protection circuit built in integrated circuit efferent duct foot, while as output end, protecting circuit cannot
Influence the ESD index of integrated circuit efferent duct foot.With the increasing of the applications such as the demand to low consumption circuit, especially sensor
Add, also requires over-voltage and reverse voltage protection circuit other than providing protection, in normal operation, itself will also have
The characteristics of low-power consumption.Need a kind of chip output pin forward direction over-voltage and reverse-voltage protection technical solution.
Summary of the invention
For this purpose, the embodiment of the present invention provides a kind of chip output pin forward direction over-voltage and reverse voltage protection circuit, realize
Protection to chip internal circuits when chip output pin overtension or reversal connection, when normal work are low in energy consumption.
To achieve the goals above, the embodiment of the present invention provides the following technical solutions: a kind of chip output pin over-voltage and
Reverse-connection protection circuit, including power end VDD, signal input part Vsig, signal output end Vout and electric wire ground terminal GND, are also wrapped
Include positive overvoltage crowbar, reverse voltage protection circuit and esd protection circuit；
The forward direction overvoltage crowbar includes high pressure NMOS pipe M1, high voltage PMOS pipe M2, high voltage PMOS pipe M3, Zener two
Pole pipe D1, resistance R1 and resistance R2；The esd protection circuit includes high pressure NMOS pipe M4, high pressure NMOS pipe M5 and high voltage PMOS
Pipe M6；The reverse voltage protection circuit includes high pressure NMOS pipe M7, Zener diode D2, resistance R3 and resistance R4；
The grid of the high pressure NMOS pipe M1 is connected with the power end VDD, the source electrode and the letter of high pressure NMOS pipe M1
Number input terminal Vsig is connected, and the drain electrode of high pressure NMOS pipe M1 is connected with the drain electrode of the high pressure NMOS pipe M5；The high voltage PMOS
The grid of pipe M2 is connected with the drain electrode of high voltage PMOS pipe M3, the drain electrode phase of the source electrode and high pressure NMOS pipe M5 of high voltage PMOS pipe M2
Even, the drain electrode of high voltage PMOS pipe M2 is connected with the signal input part Vsig；The grid of the high voltage PMOS pipe M3 and described neat
Receive diode D1 cathode be connected, the source electrode of high voltage PMOS pipe M3 is connected with the drain electrode of high pressure NMOS pipe M5, high voltage PMOS pipe M3
Drain electrode be connected with the anode of resistance R2；The anode of the resistance R1 is connected with the drain electrode of high pressure NMOS pipe M5；
The grid and source electrode of the high pressure NMOS pipe M4 is connected with the electric wire ground terminal GND respectively, high pressure NMOS pipe M4
Drain electrode be connected with the drain electrode of high pressure NMOS pipe M5, the drain electrode of the source electrode of the high voltage PMOS pipe M6 and the high pressure NMOS pipe M5
It is connected；
The grid of the high pressure NMOS pipe M7 is connected with the anode of the Zener diode D2, the source electrode of high pressure NMOS pipe M7
It is connected with the source electrode of high pressure NMOS pipe M5, the drain electrode of high pressure NMOS pipe M7 is connected with the grid of high pressure NMOS pipe M5；The resistance
The anode of R3 is connected with the grid of high pressure NMOS pipe M7；The cathode phase of the anode and the Zener diode D2 of the resistance R4
Even.
As the over-voltage of chip output pin and the preferred embodiment of reverse-connection protection circuit, the anode and high pressure of the resistance R1
The drain electrode of NMOS tube M5 is connected, and the cathode of resistance R1 is connected with the grid of high voltage PMOS pipe M3.
As the over-voltage of chip output pin and the preferred embodiment of reverse-connection protection circuit, the anode and high pressure of the resistance R2
The drain electrode of PMOS tube M3 is connected, and the cathode of resistance R2 is connected with electric wire ground terminal GND.
As the over-voltage of chip output pin and the preferred embodiment of reverse-connection protection circuit, the grid of the high pressure NMOS pipe M5 with
The drain electrode of high pressure NMOS pipe M7 is connected, and the source electrode of high pressure NMOS pipe M5 is connected with signal output end Vout, high pressure NMOS pipe M5's
Drain electrode is connected with the source electrode of high voltage PMOS pipe M6.
As the over-voltage of chip output pin and the preferred embodiment of reverse-connection protection circuit, the high voltage PMOS pipe M6 grid and electricity
Line ground terminal GND is connected, and the source electrode of high voltage PMOS pipe M6 is connected with the drain electrode of high pressure NMOS pipe M5, the drain electrode of high voltage PMOS pipe M6
It is connected with the source electrode of high pressure NMOS pipe M5.
As the over-voltage of chip output pin and the preferred embodiment of reverse-connection protection circuit, the anode of the Zener diode D2 with
The grid of the high pressure NMOS pipe M7 is connected, and the cathode of Zener diode D2 is connected with power end VDD.
As the over-voltage of chip output pin and the preferred embodiment of reverse-connection protection circuit, the anode and high pressure of the resistance R3
The grid of NMOS tube M7 is connected, and the cathode of resistance R3 is connected with the source electrode of high pressure NMOS pipe M5.
As the over-voltage of chip output pin and the preferred embodiment of reverse-connection protection circuit, anode and the Zener two of the resistance R4
The cathode of pole pipe D2 is connected, and the cathode of resistance R4 is connected with the grid of high pressure NMOS pipe M5.
The embodiment of the present invention also provides a kind of chip output pin over-voltage and reverse connecting protection method, and the guard method uses
Above-mentioned protection circuit, the protection circuit include that power end VDD, signal input part Vsig, signal output end Vout, electric wire connect
Ground terminal GND, positive overvoltage crowbar, reverse voltage protection circuit and esd protection circuit, when chip output pin operating voltage
When between the power end VDD and electric wire ground terminal GND voltage, the forward direction overvoltage crowbar and reverse-voltage protection
Circuit does not work, when there are be delivered to electric wire ground terminal by the esd protection circuit when Electro-static Driven Comb for chip output pin
GND；When chip output pin operating voltage is greater than power end vdd voltage, at the forward direction overvoltage crowbar start-up operation
In high-impedance state；When chip output pin operating voltage is lower than electric wire ground terminal GND voltage, reverse voltage protection circuit starts
Work is in high-impedance state.
The embodiment of the present invention is equipped with positive overvoltage crowbar, reverse voltage protection circuit and esd protection circuit, works as chip
When output pin voltage is located in normal voltage range (between power end VDD and electric wire ground terminal GND), positive over-voltage is protected
Protection circuit and reverse voltage protection circuit do not work, and chip is in normal operating conditions, if having electrostatic on output pin at this time
Release phenomenon occurs, and electric current will be directed at electric wire ground terminal GND by esd protection circuit, to protect internal circuit；When chip is defeated
Pin voltage, which is raised, out (is greater than power end VDD) when normal voltage range, and positive overvoltage crowbar start-up operation is placed in
High-impedance state, so that too high voltages be avoided to damage chip internal circuits；(it is lower than electric wire when chip output pin voltage is pulled low
Ground terminal GND), reverse voltage protection circuit start-up operation is placed in high-impedance state, to protect chip internal circuits.The present invention is real
The protection to chip internal circuits in chip output pin overtension or reversal connection is showed, when normal work only increases several microamperes
Electric current.
Detailed description of the invention
It, below will be to embodiment party in order to illustrate more clearly of embodiments of the present invention or technical solution in the prior art
Formula or attached drawing needed to be used in the description of the prior art are briefly described.It should be evident that the accompanying drawings in the following description is only
It is merely exemplary, it for those of ordinary skill in the art, without creative efforts, can also basis
The attached drawing of offer, which is extended, obtains other implementation attached drawings.
Fig. 1 is a kind of chip output pin over-voltage provided in the embodiment of the present invention and reverse-connection protection circuit schematic diagram.
Specific embodiment
Embodiments of the present invention are illustrated by particular specific embodiment below, those skilled in the art can be by this explanation
Content disclosed by book is understood other advantages and efficacy of the present invention easily, it is clear that described embodiment is the present invention one
Section Example, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art are not doing
Every other embodiment obtained under the premise of creative work out, shall fall within the protection scope of the present invention.
Those skilled in the art know that " high-impedance state " is a kind of state of tri-state gate circuit.The output of logic gate
In addition to having high and low level two states, there are also the third state high-impedance state, high-impedance state is neither high level is also not low electricity
It is flat.It if high-impedance state inputs next stage circuit again, has no effect to junior's circuit, is possible to if being surveyed with multimeter
It is high level it could also be possible that low level, the circuit connect below with it are fixed.
Referring to Fig. 1, a kind of chip output pin over-voltage and reverse-connection protection circuit, including the input of power end VDD, signal are provided
Vsig, signal output end Vout and electric wire ground terminal GND are held, further includes positive overvoltage crowbar, reverse voltage protection circuit
And esd protection circuit.It is described forward direction overvoltage crowbar include high pressure NMOS pipe M1, high voltage PMOS pipe M2, high voltage PMOS pipe M3,
Zener diode D1, resistance R1 and resistance R2；The esd protection circuit includes high pressure NMOS pipe M4, high pressure NMOS pipe M5 and height
Press PMOS tube M6；The reverse voltage protection circuit includes high pressure NMOS pipe M7, Zener diode D2, resistance R3 and resistance R4.
In positive overvoltage crowbar, the grid of the high pressure NMOS pipe M1 is connected with the power end VDD, high pressure NMOS
The source electrode of pipe M1 is connected with the signal input part Vsig, the drain electrode and the drain electrode of the high pressure NMOS pipe M5 of high pressure NMOS pipe M1
It is connected；The grid of the high voltage PMOS pipe M2 is connected with the drain electrode of high voltage PMOS pipe M3, the source electrode and high pressure of high voltage PMOS pipe M2
The drain electrode of NMOS tube M5 is connected, and the drain electrode of high voltage PMOS pipe M2 is connected with the signal input part Vsig；The high voltage PMOS pipe
The grid of M3 is connected with the cathode of the Zener diode D1, the drain electrode phase of the source electrode and high pressure NMOS pipe M5 of high voltage PMOS pipe M3
Even, the drain electrode of high voltage PMOS pipe M3 is connected with the anode of resistance R2；The drain electrode of the anode and high pressure NMOS pipe M5 of the resistance R1
It is connected, the cathode of resistance R1 is connected with the grid of high voltage PMOS pipe M3.The leakage of the anode and high voltage PMOS pipe M3 of the resistance R2
Extremely it is connected, the cathode of resistance R2 is connected with electric wire ground terminal GND.
In esd protection circuit, the grid and source electrode of the high pressure NMOS pipe M4 respectively with the electric wire ground terminal GND phase
Even, the drain electrode of high pressure NMOS pipe M4 is connected with the drain electrode of high pressure NMOS pipe M5, the source electrode and the height of the high voltage PMOS pipe M6
The drain electrode of NMOS tube M5 is pressed to be connected.The grid of the high pressure NMOS pipe M5 is connected with the drain electrode of high pressure NMOS pipe M7, high pressure NMOS
The source electrode of pipe M5 is connected with signal output end Vout, and the drain electrode of high pressure NMOS pipe M5 is connected with the source electrode of high voltage PMOS pipe M6.Institute
It states high voltage PMOS pipe M6 grid to be connected with electric wire ground terminal GND, the drain electrode of the source electrode and high pressure NMOS pipe M5 of high voltage PMOS pipe M6
It is connected, the drain electrode of high voltage PMOS pipe M6 is connected with the source electrode of high pressure NMOS pipe M5.
In reverse voltage protection circuit, the anode phase of the grid and the Zener diode D2 of the high pressure NMOS pipe M7
Even, the source electrode of high pressure NMOS pipe M7 is connected with the source electrode of high pressure NMOS pipe M5, the drain electrode of high pressure NMOS pipe M7 and high pressure NMOS pipe
The grid of M5 is connected；The anode of the resistance R3 is connected with the grid of high pressure NMOS pipe M7, the cathode and high pressure NMOS of resistance R3
The source electrode of pipe M5 is connected；The anode of the resistance R4 is connected with the cathode of the Zener diode D2, the cathode and height of resistance R4
The grid of NMOS tube M5 is pressed to be connected.The anode of the Zener diode D2 is connected with the grid of the high pressure NMOS pipe M7, Zener
The cathode of diode D2 is connected with power end VDD.
Specifically, positive overvoltage crowbar effect is raised when chip bearing value in chip output pin, cutting
External high pressure and chip internal circuits, to guarantee that chip internal circuits are not damaged by positive high pressure.When chip output pin is believed
Number output end Vout voltage in the normal range when (between power end VDD and electric wire ground terminal GND), due to two pole of Zener
The burning voltage of pipe D1 is greater than or equal to chip and works normally power end vdd voltage, Zener diode D1 cut-off, high voltage PMOS pipe
The grid of M3 is drawn high by resistance R1 to the source voltage close to high voltage PMOS pipe M3, high voltage PMOS pipe M3 cut-off, high voltage PMOS pipe
The grid of M2 is pulled low to ground electric wire ground terminal GND by resistance R2, while the grid level power end VDD of high pressure NMOS pipe M1 is greater than
The transmission gate conducting of Vsig, high voltage PMOS pipe M2 and high pressure NMOS pipe M1 composition, simultaneously because Zener diode D2's stablizes electricity
Pressure is greater than or equal to chip normal working voltage power end VDD, and Zener diode D2 ends, and the grid of high pressure NMOS pipe M7 is electric
Resistance R4 is pulled low near signal output end Vout, and high pressure NMOS pipe M7 is in off state, and the grid of high pressure NMOS pipe M5 is by R4
It draws high to power end VDD, while the grid level GND of high voltage PMOS pipe M6 is less than Vout, high pressure NMOS pipe M5 and high voltage PMOS
The transmission gate conducting of pipe M6 composition, chip interior output Vsig signal can normally be exported to Vout pin；When chip exports
Pin Vout voltage is raised when chip normal working voltage range, and electric current passes through high pressure NMOS pipe M7 source electrode to leakage from Vout
The positive parasitic diode and resistance R4 of pole flow to power end VDD, high pressure NMOS pipe M5 and high voltage PMOS pipe M6 are connected, therefore
The drain voltage of high pressure NMOS pipe M5 is close to Vout, since Vout is greater than the burning voltage of Zener diode D1, Zener two at this time
Pole pipe D1 conducting, there is current flowing resistance R1, when resistance R1 both end voltage is greater than the threshold voltage of high voltage PMOS pipe M3, high pressure
PMOS tube M3 conducting, the anode of resistance R2 are pulled to close to Vout, high voltage PMOS pipe and M2 cut-off at this time, simultaneously because Vout
Level is higher than power end VDD, and high pressure NMOS pipe M1 is also at off state, what high pressure NMOS pipe M1 and high voltage PMOS pipe M2 were formed
Transmission gate is high-impedance state, and chip internal circuits is avoided to be damaged by high pressure.
Specifically, esd protection circuit is used to protect chip internal circuits when static discharge phenomenon occurs.High voltage PMOS pipe
There are a parasitic forward diode, the source electrode phases of the substrate and high pressure NMOS pipe M5 of high pressure NMOS pipe M5 for the drain-to-source of M6
Even, there is a parasitism forward diode to drain electrode in the source electrode of high pressure NMOS pipe M5, electrostatic without waiting for high pressure NMOS pipe M5 with
High voltage PMOS pipe M6 conducting, but the drain electrode of high pressure NMOS pipe M4 is directly reached by this 2 parasitic diodes；High pressure NMOS
The connection type of pipe M4 is grounded-grid NMOS, and the NMOS tube under CMOS technology has a lateral parasitic n-p-n transistor, this
Parasitic transistor can absorb a large amount of electric current when opening, and in normal operating conditions, high pressure NMOS pipe M4 lateral transistor will not
Conducting, when Electro-static Driven Comb phenomenon occurs, snowslide will occur for the depletion region of high pressure NMOS pipe M4 drain electrode and substrate, and along with electricity
The generation in sub- hole pair, the other source electrode in the hole that a part generates absorb, remaining flowing through substrate, thus release electrostatic.
Specifically, reverse voltage protection circuit is for guaranteeing to be pulled low when electric wire ground terminal GND in chip output pin
It is placed in high-impedance state, to guarantee that chip internal circuits are not reversed voltage damage.The working principle of reverse voltage protection circuit
Are as follows: when chip output pin Vout voltage in the normal range when (between power end VDD and electric wire ground terminal GND), by
It is greater than or equal to chip normal working voltage power end VDD, the grid of high pressure NMOS pipe M7 in the burning voltage of Zener diode D2
Pole is pulled low near Vout by resistance R3, and high pressure NMOS pipe M7 is in off state, and the grid of high pressure NMOS pipe M5 is by resistance R4
It draws high to power end VDD, high pressure NMOS pipe M5 is in the conductive state, simultaneously because the grid level (GND) of high voltage PMOS pipe M6
Lower than the transmission gate conducting of Vout, high pressure NMOS pipe M5 and high voltage PMOS pipe M6 composition, simultaneously because Zener diode D1's is steady
Constant voltage is greater than or equal to chip normal working voltage power end VDD, and the grid of high voltage PMOS pipe M3 is drawn high by resistance R1 to connecing
The grid of the source voltage of nearly high voltage PMOS pipe M3, high voltage PMOS pipe M3 cut-off, M2 is pulled low to ground GND, high voltage PMOS pipe by R2
The transmission gate of M2 and high pressure NMOS pipe M1 composition is also switched on, and chip interior output Vsig signal can be exported normally to Vout pin
On；When chip output pin Vout voltage is pulled low to lower than ground GND, voltage is greater than Zener between power end VDD and Vout
The burning voltage of diode D2, Zener diode D2 conducting have current flowing resistance R3, the grid electricity of high pressure NMOS pipe M7 at this time
Flat to be greater than source level, high pressure NMOS pipe M7 is in the conductive state, and the grid of high pressure NMOS pipe M5 is pulled low to Vout, high pressure
NMOS tube M5 is in off state, simultaneously because the grid voltage GND of high voltage PMOS pipe M6 is greater than Vout, high voltage PMOS pipe M6
Cut-off, therefore the transmission gate of high pressure NMOS pipe M5 and high voltage PMOS pipe M6 composition is in high-impedance state, to guarantee chip interior
Internal circuit is not influenced by backward voltage.
The embodiment of the present invention also provides a kind of chip output pin over-voltage and reverse connecting protection method, and the guard method uses
Above-mentioned protection circuit, the protection circuit include that power end VDD, signal input part Vsig, signal output end Vout, electric wire connect
Ground terminal GND, positive overvoltage crowbar, reverse voltage protection circuit and esd protection circuit, when chip output pin operating voltage
When between the power end VDD and electric wire ground terminal GND voltage, the forward direction overvoltage crowbar and reverse-voltage protection
Circuit does not work, when there are be delivered to electric wire ground terminal by the esd protection circuit when Electro-static Driven Comb for chip output pin
GND；When chip output pin operating voltage is greater than power end vdd voltage, at the forward direction overvoltage crowbar start-up operation
In high-impedance state；When chip output pin operating voltage is lower than electric wire ground terminal GND voltage, reverse voltage protection circuit starts
Work is in high-impedance state.The embodiment of the present invention is equipped with positive overvoltage crowbar, reverse voltage protection circuit and ESD protection electricity
Road, when chip output pin voltage is located in normal voltage range (between power end VDD and electric wire ground terminal GND),
Positive overvoltage crowbar and reverse voltage protection circuit do not work, and chip is in normal operating conditions, at this time output pin
If upper have Electro-static Driven Comb phenomenon, electric current will be directed at electric wire ground terminal GND by esd protection circuit, to protect internal electricity
Road；(it is greater than power end VDD) when normal voltage range when chip output pin voltage is raised, positive overvoltage crowbar is opened
Beginning work is placed in high-impedance state, so that too high voltages be avoided to damage chip internal circuits；When chip output pin voltage is pulled low
When (be lower than electric wire ground terminal GND), reverse voltage protection circuit start-up operation is placed in high-impedance state, to protect chip interior electric
Road.The present invention realizes the protection to chip internal circuits in chip output pin overtension or reversal connection, when normal work
Only increase several microamperes of electric current.
Although above having used general explanation and specific embodiment, the present invention is described in detail, at this
On the basis of invention, it can be made some modifications or improvements, this will be apparent to those skilled in the art.Therefore,
These modifications or improvements without departing from theon the basis of the spirit of the present invention are fallen within the scope of the claimed invention.
Claims (9)
1. a kind of chip output pin over-voltage and reverse-connection protection circuit, including power end VDD, signal input part Vsig, signal are defeated
Outlet Vout and electric wire ground terminal GND, which is characterized in that further include positive overvoltage crowbar, reverse voltage protection circuit and
Esd protection circuit；
The forward direction overvoltage crowbar includes high pressure NMOS pipe M1, high voltage PMOS pipe M2, high voltage PMOS pipe M3, Zener diode
D1, resistance R1 and resistance R2；The esd protection circuit includes high pressure NMOS pipe M4, high pressure NMOS pipe M5 and high voltage PMOS pipe M6；
The reverse voltage protection circuit includes high pressure NMOS pipe M7, Zener diode D2, resistance R3 and resistance R4；
The grid of the high pressure NMOS pipe M1 is connected with the power end VDD, and the source electrode and the signal of high pressure NMOS pipe M1 is defeated
Enter to hold Vsig to be connected, the drain electrode of high pressure NMOS pipe M1 is connected with the drain electrode of the high pressure NMOS pipe M5；The high voltage PMOS pipe M2
Grid be connected with the drain electrode of high voltage PMOS pipe M3, the source electrode of high voltage PMOS pipe M2 is connected with the drain electrode of high pressure NMOS pipe M5, high
The drain electrode of pressure PMOS tube M2 is connected with the signal input part Vsig；The grid of the high voltage PMOS pipe M3 and two pole of Zener
The cathode of pipe D1 is connected, and the source electrode of high voltage PMOS pipe M3 is connected with the drain electrode of high pressure NMOS pipe M5, the drain electrode of high voltage PMOS pipe M3
It is connected with the anode of resistance R2；The anode of the resistance R1 is connected with the drain electrode of high pressure NMOS pipe M5；
The grid and source electrode of the high pressure NMOS pipe M4 is connected with the electric wire ground terminal GND respectively, the leakage of high pressure NMOS pipe M4
Pole is connected with the drain electrode of high pressure NMOS pipe M5, the drain electrode phase of the source electrode of the high voltage PMOS pipe M6 and the high pressure NMOS pipe M5
Even；
The grid of the high pressure NMOS pipe M7 is connected with the anode of the Zener diode D2, the source electrode and height of high pressure NMOS pipe M7
The source electrode of NMOS tube M5 is pressed to be connected, the drain electrode of high pressure NMOS pipe M7 is connected with the grid of high pressure NMOS pipe M5；The resistance R3's
Anode is connected with the grid of high pressure NMOS pipe M7；The anode of the resistance R4 is connected with the cathode of the Zener diode D2.
2. a kind of chip output pin over-voltage according to claim 1 and reverse-connection protection circuit, which is characterized in that the electricity
The anode of resistance R1 is connected with the drain electrode of high pressure NMOS pipe M5, and the cathode of resistance R1 is connected with the grid of high voltage PMOS pipe M3.
3. a kind of chip output pin over-voltage according to claim 1 and reverse-connection protection circuit, which is characterized in that the electricity
The anode of resistance R2 is connected with the drain electrode of high voltage PMOS pipe M3, and the cathode of resistance R2 is connected with electric wire ground terminal GND.
4. a kind of chip output pin over-voltage according to claim 1 and reverse-connection protection circuit, which is characterized in that the height
The grid of pressure NMOS tube M5 is connected with the drain electrode of high pressure NMOS pipe M7, source electrode and the signal output end Vout phase of high pressure NMOS pipe M5
Even, the drain electrode of high pressure NMOS pipe M5 is connected with the source electrode of high voltage PMOS pipe M6.
5. a kind of chip output pin over-voltage according to claim 1 and reverse-connection protection circuit, which is characterized in that the height
Pressure PMOS tube M6 grid is connected with electric wire ground terminal GND, and the source electrode of high voltage PMOS pipe M6 is connected with the drain electrode of high pressure NMOS pipe M5,
The drain electrode of high voltage PMOS pipe M6 is connected with the source electrode of high pressure NMOS pipe M5.
6. a kind of chip output pin over-voltage according to claim 1 and reverse-connection protection circuit, which is characterized in that described neat
The anode of diode D2 received is connected with the grid of the high pressure NMOS pipe M7, cathode and the power end VDD phase of Zener diode D2
Even.
7. a kind of chip output pin over-voltage according to claim 1 and reverse-connection protection circuit, which is characterized in that the electricity
The anode of resistance R3 is connected with the grid of high pressure NMOS pipe M7, and the cathode of resistance R3 is connected with the source electrode of high pressure NMOS pipe M5.
8. a kind of chip output pin over-voltage according to claim 1 and reverse-connection protection circuit, which is characterized in that the electricity
The anode of resistance R4 is connected with the cathode of Zener diode D2, and the cathode of resistance R4 is connected with the grid of high pressure NMOS pipe M5.
9. a kind of chip output pin over-voltage and reverse connecting protection method, the guard method is used as claim 1 to 8 is any one
The protection circuit of item, the protection circuit include power end VDD, signal input part Vsig, signal output end Vout, electric wire ground connection
Hold GND, positive overvoltage crowbar, reverse voltage protection circuit and esd protection circuit, which is characterized in that when chip efferent duct
When foot operating voltage is between the power end VDD and electric wire ground terminal GND voltage, the forward direction overvoltage crowbar and anti-
It does not work to voltage protection circuit, when there are be delivered to when Electro-static Driven Comb by the esd protection circuit for chip output pin
Electric wire ground terminal GND；When chip output pin operating voltage is greater than power end vdd voltage, the forward direction overvoltage crowbar
It starts to work and is in high-impedance state；When chip output pin operating voltage is lower than electric wire ground terminal GND voltage, backward voltage is protected
Protection circuit, which is started to work, is in high-impedance state.
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| CN201910605777.3A CN110311668B (en) | 2019-07-05 | 2019-07-05 | Chip output pin forward overvoltage and reverse voltage protection circuit and method |
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| CN110311668B CN110311668B (en) | 2022-11-04 |
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| CN110311668B (en) | 2022-11-04 |
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