CN110310991B

CN110310991B - Field effect transistor, preparation method thereof and transistor array device

Info

Publication number: CN110310991B
Application number: CN201810259749.6A
Authority: CN
Inventors: 何正宇; 李伟
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2018-03-27
Filing date: 2018-03-27
Publication date: 2021-05-07
Anticipated expiration: 2038-03-27
Also published as: CN110310991A

Abstract

An embodiment of the present invention provides a field effect transistor, comprising an insulating substrate, a channel material layer disposed on the insulating substrate, two p-type contact layers disposed on the channel material layer at intervals, and disposed on the two p-type contact layers. The gate dielectric layer and gate on the channel material layer between the two p-type contact layers are respectively arranged on the source and drain electrodes on the two p-type contact layers, and the material of the channel material layer is a two-dimensional transition metal chalcogenide compound , the material of the p-type contact layer is MO _X , M is a transition metal, 0<x<3, and M is the same as the transition metal in the channel material layer. The present invention forms a good p-type contact by arranging a p-type contact layer between the source and the drain and the channel material, thereby improving the quality of the field effect transistor. In the present invention, the material of the gate dielectric layer is also set as the oxide MO ₃ of the corresponding transition metal in the channel material layer, so as to realize the preparation of the ultra-thin and high dielectric constant gate dielectric layer, and further improve the quality of the field effect transistor.

Description

Field effect transistor, preparation method thereof and transistor array device

Technical Field

The invention relates to the technical field of field effect transistors, in particular to a field effect transistor, a preparation method thereof and a transistor array device.

Background

TMD (Transition Metal chalcogenide) materials are considered to be very suitable as channel materials for fabricating CMOS (Complementary Metal Oxide Semiconductor) circuits, resulting in field effect transistors, due to their atomic-scale thickness and large band gap (1.8eV-2.4 eV). However, in order to prepare a high quality TMD FET (Field Effect Transistor), the following two problems need to be solved: 1. how to form good electrical contact between the source drain metal and the TMD material; 2. how to fabricate a high quality gate dielectric layer on TMD material.

For the problem of electrical contact, two aspects can be taken:(1) reducing the contact resistance between the source drain metal and the TMD material; (2) so that the source and drain metal and the TMD material effectively form N/P type conductive contact. Among other things, the efficient formation of N/P type conductive contacts depends primarily on the relative position between the metal and the conduction band bottom or valence band top of the TMD material. Due to the formation of the gap state and the metal-TMD material alloy, a strong Fermi pinning effect can be formed between the work function of the metal and the TMD material, namely, even if the metal with different work functions is selected, the relative position between the conduction band bottom and the valence band top of the TMD material is slightly changed. It is therefore easier to form a better electrical contact of one type and more difficult to form another type for TMD materials. For example, for the common TMD (MoS)₂,WS₂,MoSe₂,WSe₂) It is easier to form an N-type electrical contact than a P-type contact. If the TMD material is used in a CMOS circuit, it is important to be able to controllably realize N-type or P-type contacts, but since the conventional method of doping the two-dimensional TMD material with silicon damages the two-dimensional material lattice, thereby affecting the electrical performance, it is necessary to find a new method to effectively form P-type conductive contacts between the metal and the TMD material to obtain a high-performance TMD FET.

In addition, the high-quality gate dielectric layer can form stable and reliable gate control on the TMD material, and stable threshold voltage and smaller sub-threshold swing amplitude can be obtained. However, since there is no dangling bond on the surface of the TMD material, it becomes extremely difficult to form a high quality thin layer gate dielectric on the surface of the TMD material, and therefore, it is necessary to find a new effective method for forming a high quality thin layer gate dielectric on the surface of the TMD material to obtain a high performance TMD FET.

Disclosure of Invention

In view of this, a first aspect of the embodiments of the present invention provides a field effect transistor, in which a p-type contact layer is disposed between a source/drain metal and a channel TMD material, so as to implement a good p-type contact, and improve performance and quality of the field effect transistor, so as to solve a problem that in an existing TMD FET, the source/drain metal and the TMD material are difficult to form a good p-type contact, which results in difficulty in manufacturing a high-performance and high-quality TMD FET.

Specifically, a first aspect of an embodiment of the present invention provides a field effect transistor, including:

an insulating substrate;

the channel material layer is arranged on the insulating substrate and is made of two-dimensional transition metal chalcogenide;

two p-type contact layers arranged on the channel material layer at intervals, wherein the p-type contact layers are made of transition metal oxide with a general formula of MO_XWherein M is transition metal, x is more than 0 and less than 3, and the transition metal species in the p-type contact layer is the same as the transition metal species in the channel material layer;

the gate dielectric layer is arranged on the channel material layer between the two p-type contact layers;

the source electrode and the drain electrode are respectively arranged on the two p-type contact layers;

and the grid electrode is arranged on the grid dielectric layer.

In the first aspect of the present invention, the two-dimensional transition metal chalcogenide compound includes molybdenum disulfide (MoS)₂) Tungsten disulfide (WS)₂) Molybdenum diselenide (MoSe)₂) Tungsten diselenide (WSe)₂) Molybdenum ditelluride (MoTe)₂) Tungsten ditelluride (WTE)₂) One or more of (a).

In the first aspect of the present invention, the MO_XWherein M is molybdenum (Mo) or tungsten (W), i.e., the MO_XIs MoO_XOr WO_X。

In the first aspect of the present invention, the p-type contact layer has a thickness of 1nm to 6 nm.

In the first aspect of the present invention, the p-type contact layer is obtained by in-situ oxidation of the channel material layer, and the p-type contact layer and the channel material layer are bonded by a chemical bond.

In an embodiment of the first aspect of the present invention, the gate dielectric layer is made of a transition metal oxide, and a general formula of the transition metal oxide is MO₃Wherein M is a transition metal, and the transition metal species in the gate dielectric layer and the channel material layerThe transition metals of (3) are the same. Specifically, the gate dielectric layer is made of molybdenum trioxide (MoO)₃) Or tungsten trioxide (WO)₃). In the first aspect of the present invention, the gate dielectric layer is obtained by in-situ oxidation of a material of the channel material layer, and the gate dielectric layer and the channel material layer are bonded by a chemical bond.

In the first aspect of the present invention, the two p-type contact layers are connected to the gate dielectric layer, or the two p-type contact layers are respectively spaced from the gate dielectric layer.

In another embodiment of the first aspect of the present invention, the gate dielectric layer is made of at least one of aluminum oxide and hafnium oxide.

In the first aspect of the invention, the thickness of the gate dielectric layer is 1nm-6 nm; the thickness of the gate dielectric layer is equal to, larger than or smaller than that of the p-type contact layer.

In the first aspect of the present invention, the channel material layer has an equal thickness or an unequal thickness, and the thickness of the channel material layer at the maximum thickness is 1nm to 10 nm.

In the first aspect of the present invention, the material of the insulating substrate includes Si and SiO₂At least one of SOI, SiC and sapphire.

In the first aspect of the present invention, the source electrode and the drain electrode are made of one or more materials selected from platinum, copper, nickel, palladium, gold, titanium, and chromium.

In the first aspect of the present invention, the material of the gate includes one of gold, palladium, and tungsten.

According to the field effect transistor provided by the first aspect of the embodiment of the invention, by utilizing the difference of electrical characteristics caused by the difference of oxidation degrees of in-situ oxidation products of channel materials, the P-type contact layer is arranged between the source and drain metal and the channel material layer, the material of the P-type contact layer is MOx which is the in-situ incomplete oxidation product of the channel material, the oxidation product has higher conductivity and high work function, so that hole injection is facilitated, and further, good P-type contact can be realized between the source and drain metal and the channel material layer, and the performance and the quality of the field effect transistor are improved; and embodiments of the invention further provide a gateThe material of the dielectric layer is set as a channel material complete oxidation product MO₃The preparation of the ultrathin gate dielectric layer with high dielectric constant is realized, and the performance and the quality of the field effect transistor are further improved.

A second aspect of an embodiment of the present invention provides a field effect transistor, including:

an insulating substrate;

the source electrode and the drain electrode are arranged on the channel material layer at intervals;

a gate dielectric layer arranged on the channel material layer between the source and the drain, the gate dielectric layer is made of transition metal oxide with a general formula of MO₃Wherein M is transition metal, and the transition metal species in the gate dielectric layer is the same as the transition metal species in the channel material layer;

and the grid electrode is arranged on the grid dielectric layer.

In a second aspect of the invention, the two-dimensional transition metal chalcogenide comprises MoS₂,WS₂,MoSe₂,WSe₂,MoTe₂,WTe₂One or more of (a).

In the second aspect of the present invention, the MO_XWherein M is Mo or W.

In the second aspect of the invention, the thickness of the gate dielectric layer is 1nm-6 nm.

In the second aspect of the present invention, the gate dielectric layer is obtained by completely oxidizing the channel material layer in situ, and the gate dielectric layer and the channel material layer are bonded by a chemical bond.

In the second aspect of the present invention, a p-type contact layer is disposed between the source electrode and the channel material layer, a p-type contact layer is disposed between the drain electrode and the channel material layer, the two p-type contact layers are both made of transition metal oxide, and the transition metal oxide has a general formula of MO_XWherein M is a transition metal, 0 < x < 3, andthe transition metal species in the p-type contact layer are the same as the transition metal species in the channel material layer.

In the second aspect of the present invention, the p-type contact layer has a thickness of 1nm to 6 nm.

In the second aspect of the present invention, the p-type contact layer is obtained by in-situ oxidation of the channel material layer, and the p-type contact layer and the channel material layer are bonded by a chemical bond.

In the second aspect of the present invention, the two p-type contact layers are connected to the gate dielectric layer, or the two p-type contact layers are respectively spaced from the gate dielectric layer.

In the second aspect of the present invention, the thickness of the gate dielectric layer is equal to, greater than or less than the thickness of the p-type contact layer.

In the second aspect of the present invention, the channel material layer has an equal thickness or an unequal thickness, and the thickness of the channel material layer at the maximum thickness is 1nm to 10 nm.

In the field effect transistor provided in the second aspect of the embodiments of the present invention, the difference in electrical characteristics due to the difference in oxidation degree of the in-situ oxidation product of the channel material is utilized, and the material of the gate dielectric layer is set to be the in-situ complete oxidation product MO of the channel material₃The oxidation product is an insulator, has a large dielectric constant and can be controllably prepared, so that the preparation of an ultrathin gate dielectric layer with a high dielectric constant is realized, and the performance and the quality of the field effect transistor are improved; and the embodiment of the invention further arranges a P-type contact layer between the source/drain electrode metal and the channel material layer, wherein the material of the P-type contact layer is the in-situ incomplete oxidation product MO of the channel material_xThe oxidation product has higher conductivity and high work function, thereby being beneficial to hole injection, further realizing good P-type contact between the source and drain metal and the channel material layer and improving the performance and the quality of the field effect transistor.

The third aspect of the embodiments of the present invention further provides a method for manufacturing a field effect transistor, including the following steps:

providing an insulating substrate, and arranging a two-dimensional transition metal chalcogenide material layer on the insulating substrate, wherein the two-dimensional transition metal chalcogenide material layer comprises a source-drain region positioned on the insulating substrate and a gate region positioned between the source-drain region;

protecting the grid region by adopting photoresist, heating the source and drain regions which are not protected by the photoresist in an oxygen-rich or ozone environment to ensure that the surface of the two-dimensional transition metal chalcogenide material layer of the source and drain regions is incompletely oxidized to generate a transition metal oxide to obtain a p-type contact layer, forming a channel material layer by the unoxidized two-dimensional transition metal chalcogenide material layer, wherein the general formula of the transition metal oxide is MO_XWherein M is transition metal, x is more than 0 and less than 3, and the transition metal species in the p-type contact layer is the same as the transition metal species in the channel material layer;

and forming a source electrode and a drain electrode in the source-drain region, and sequentially forming a gate dielectric layer and a gate electrode in the gate region after washing away the photoresist to obtain the field effect transistor.

In the third aspect of the present invention, the specific operation of forming the gate dielectric layer is: protecting the source electrode and the drain electrode by adopting photoresist, and heating the grid electrode area which is not protected by the photoresist in an oxygen-rich or ozone environment to ensure that the surface of the two-dimensional transition metal chalcogenide material layer of the grid electrode area is completely oxidized to generate transition metal oxide to obtain the grid dielectric layer, wherein the general formula of the transition metal oxide is MO₃And M is transition metal, and the transition metal type in the gate dielectric layer is the same as that in the channel material layer.

The fourth aspect of the embodiments of the present invention further provides a method for manufacturing a field effect transistor, including the following steps:

adopting photoresist to protect the source and drain regions, and protecting the source and drain regions from the photoresist in an oxygen-rich or ozone environmentThe gate region is heated, the surface of the two-dimensional transition metal chalcogenide material layer of the gate region is completely oxidized to generate transition metal oxide to obtain a gate dielectric layer, the unoxidized two-dimensional transition metal chalcogenide material layer forms a channel material layer, and the general formula of the transition metal oxide is MO₃Wherein M is transition metal, and the transition metal species in the gate dielectric layer is the same as the transition metal species in the channel material layer;

and then forming a source electrode and a drain electrode in the source and drain regions after the grid electrode is arranged on the grid dielectric layer and the photoresist is washed away, so as to obtain the field effect transistor.

In the fourth aspect of the present invention, before the source and the drain are prepared, two p-type contact layers are prepared in the source and drain region, and the specific preparation process of the p-type contact layers is as follows: protecting the grid by photoresist, and heating the source and drain regions which are not protected by the photoresist in an oxygen-rich or ozone environment to ensure that the surfaces of the two-dimensional transition metal chalcogenide material layers of the source and drain regions are subjected to incomplete oxidation to generate transition metal oxides to obtain two p-type contact layers, wherein the general formula of the transition metal oxides is MO_XAnd M is transition metal, x is more than 0 and less than 3, and the transition metal type in the p-type contact layer is the same as that in the channel material layer.

The embodiment of the invention utilizes the characteristic that TMD material can be oxidized layer by layer and the electrical property of the oxidation product can change along with the change of oxygen defect density, adopts the same process method and equipment, and simultaneously solves the two problems of P-type electrical contact and ultra-thin gate dielectric growth of TMD FET by oxidizing the surface of the TMD material layer to different degrees, the process is simple, and the manufacturing cost of the device is greatly reduced. Specifically, the embodiment of the invention utilizes the characteristics that MOx obtained after a TMD material is incompletely oxidized has higher conductivity and high work function, and obtains a P-type contact layer by incompletely oxidizing a surface TMD material of a source drain region, thereby solving the problem of poor P-type electrical contact of a TMD FET; meanwhile, in the embodiment of the invention, a product MO obtained by completely oxidizing TMD material is utilized₃The method has the characteristics of high resistivity and high dielectric constant, and the gate dielectric layer is obtained by completely oxidizing the TMD material on the surface layer of the gate region, so that the problem of uniform and ultrathin gate dielectric growth in the TMD FET is solved.

A fifth aspect of embodiments of the present invention provides a transistor array device comprising an array structure formed by field effect transistors according to the first or second aspect of embodiments of the present invention.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments or the background art of the present invention, the drawings required to be used in the embodiments or the background art of the present invention will be described below.

FIG. 1 is a schematic diagram of a field effect transistor according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a field effect transistor according to another embodiment of the present invention;

FIG. 3 is a schematic diagram of a field effect transistor according to another embodiment of the present invention;

FIG. 4 is a schematic flow chart illustrating the fabrication of the field effect transistor shown in FIG. 1 according to one embodiment of the present invention;

fig. 5 is a schematic flow chart illustrating a process for manufacturing the field effect transistor shown in fig. 3 according to the embodiment of the present invention.

Detailed Description

The embodiments of the present invention will be described below with reference to the drawings.

TMD materials are widely used as channel materials to fabricate field effect transistors due to their atomic-scale thickness and large band gap, however, there are two problems that are currently occurring that are continuously hindering the fabrication of high quality TMD FETs: 1. how to form good electrical contact between the source drain metal and the TMD material; 2. how to fabricate a high quality gate dielectric layer on TMD material. In order to effectively solve the problems and prepare and obtain the high-quality TMD FET, the embodiment of the invention provides a novel field effect transistor structure by utilizing the characteristics that an oxidation product obtained after a TMD material is incompletely oxidized has higher conductivity and high work function, and the oxidation product obtained after the TMD material is completely oxidized has higher resistivity and high dielectric constant.

Specifically, as shown in fig. 1 and 2, an embodiment of the present invention provides a field effect transistor including: an insulating substrate 10; a channel material layer 20 disposed on the insulating substrate 10, two p-type contact layers 31 and 32 disposed on the channel material layer 20 and respectively located at two opposite ends of the insulating substrate 10, and a source 40 and a drain 50 respectively disposed on the two p-type contact layers 31 and 32; a

gate dielectric layer

160 or 260 disposed on the channel material layer 20 between the two p-type contact layers 31 and 32, and a gate electrode 70 disposed on the

gate dielectric layer

160 or 260; the channel material layer 20 is made of a two-dimensional transition metal chalcogenide compound; the p-type contact layers 31 and 32 are made of transition metal oxide, and the general formula of the transition metal oxide is MO_XWherein M is a transition metal, 0 < x < 3, and the transition metal species in the p-type contact layers 31, 32 are the same as the transition metal species in the channel material layer 20.

In the field effect transistor provided by the embodiment of the invention, because the channel material two-dimensional transition metal chalcogenide can obtain oxidation products with different oxygen defect densities after being oxidized in different degrees, and the electrical characteristics of the oxidation products are changed along with the change of the oxygen defect density, the characteristics of different electrical characteristics of the channel material in-situ oxidation products caused by different oxidation degrees (high oxidation degree and low oxygen defect density) are utilized, the P-type contact layer is arranged between the source and drain electrode metal and the channel material layer and is made of the in-situ incomplete oxidation product of the channel material layer material, the oxidation product has higher conductivity and high work function, so that hole injection is facilitated, good P-type contact can be realized between the source and drain electrode metal and the channel material layer, the performance and the quality of the field effect transistor are improved, and the P-type contact layer can be obtained by carrying out in-situ incomplete oxidation on the channel material layer material, the preparation process is simple.

In an embodiment of the present invention, the two-dimensional transition metal chalcogenide comprises MoS₂,WS₂,MoSe₂,WSe₂,MoTe₂,WTe₂One or more of (a). Correspondingly, the p-type contact layers 31 and 32 are made of MO_XSaid MO being_XIn the formula, M is Mo or W. Specifically, for example, the channel material layer 20 may be made of MoS₂、MoSe₂、MoTe₂Respectively, the material of the p-type contact layers 31 and 32 is MoO_X(ii) a The material of the channel material layer 20 may be WS₂、WSe₂、WTe₂Respectively, the material of the p-type contact layers 31 and 32 is WO_X。

In the embodiment of the invention, different degrees of oxidation (incomplete oxidation or complete oxidation) can be realized by regulating and controlling specific process parameters of the oxidation process. It should be noted that the thickness of the oxidized product obtained after the oxidation of the channel material according to the embodiment of the present invention is greater than the thickness of the original channel material, for example, the thickness of the oxidized product obtained after the oxidation of the channel material with a single layer structure thickness of about 1nm is increased to about 1.3 nm.

In the embodiment of the present invention, the p-type contact layers 31 and 32 are obtained by in-situ incomplete oxidation of the channel material layer 20, and the p-type contact layers 31 and 32 are bonded to the channel material layer 20 through chemical bonds. The oxidation product MO obtained by incomplete oxidation of the channel material layer 20 material_XThe P-type contact layers 31 and 32 can effectively improve hole injection, so that good P-type contact between the source and drain

metals

40 and 50 and the channel material layer 20 is realized, and the performance and quality of the field effect transistor are improved.

In an embodiment of the present invention, the thickness of the p-type contact layers 31 and 32 is greater than that of the single-layer two-dimensional transition metal chalcogenide material, and optionally, the thickness of the p-type contact layers 31 and 32 is 1nm to 6nm, specifically, 2nm to 5nm, and 3nm to 4 nm.

As shown in fig. 1, in an embodiment of the present invention, the gate dielectric layer 160 is made of a transition metal oxide, and the general formula of the transition metal oxide is MO₃Wherein M is a transition metal, and the transition metal species in the gate dielectric layer 160 and the channel material layerThe transition metals in 20 are the same kind. In the embodiment of the invention, the material of the gate dielectric layer 160 is further set to be the oxide MO of the corresponding transition metal in the channel material layer 20₃The preparation of the ultrathin gate dielectric layer 160 with high dielectric constant is realized, so that the quality of the field effect transistor is further improved. Specifically, the gate dielectric layer 160 is made of molybdenum trioxide or tungsten trioxide. In the embodiment of the present invention, the gate dielectric layer 160 is obtained by completely oxidizing the channel material layer 20 in situ, and the gate dielectric layer 160 and the channel material layer 20 are bonded by a chemical bond. The oxidation product MO obtained by completely oxidizing the channel material layer 20 material₃Has the characteristics of higher resistivity and high dielectric constant, and can obtain uniform and ultrathin high-quality gate dielectric. In this embodiment, when the gate dielectric layer 160 is made of the oxide MO of the corresponding transition metal in the channel material layer 20₃In this case, the thickness of the channel material layer 20 in the region where the p-type contact layers 31 and 32 are located and the thickness of the region where the gate dielectric layer 160 is located may be equal or may not be equal. The thickness of the gate dielectric layer 160 may be equal to, greater than, or less than the thickness of the p-type contact layers 31, 32. Specifically, the thickness of the gate dielectric layer 160 is greater than that of the single-layer two-dimensional transition metal chalcogenide material, and is optionally 1nm to 6nm, and further optionally 2nm to 5nm, and 3nm to 4 nm.

In one embodiment of the present invention, the two p-type contact layers 31 and 32 and the gate dielectric layer 160 are connected together to form an integral film with equal or different thickness. In another embodiment of the present invention, the two p-type contact layers 31 and 32 are respectively disposed at a distance from the gate dielectric layer 160.

As shown in fig. 2, in another embodiment of the present invention, the gate dielectric layer 260 is made of at least one of aluminum oxide and hafnium oxide. In this embodiment, the thickness of the gate dielectric layer 260 is equal to, greater than or less than the thickness of the p-type contact layers 31 and 32, and optionally, the thickness of the gate dielectric layer 260 is greater than the thickness of the p-type contact layers 31 and 32.

In addition, it should be noted that the

gate dielectric layer

160 or 260 shown in fig. 1 and 2 is disposed between the two P-type contact layers 31 and 32, but the gate dielectric layer is substantially used for controlling the conduction and the turn-off of the channel layer below the two P-type contact layers, so as long as the

gate dielectric layer

160 or 260 can affect the channel material layer between the two P-type contact layers 31 and 32, and the position thereof does not need to be disposed between the two P-type contact layers 31 and 32. For example, the

gate dielectric layer

160 or 260 may be formed on a plane perpendicular to the two P-type contact layers, with the

gate dielectric layer

160 or 260 between the two P-type contact layers 31 and 32, in consideration of the possibility of three-dimensional layout of the transistor structure. For the same reason, the two P-type contact layers may not be on the same plane.

In the embodiment of the present invention, the two-dimensional transition metal chalcogenide of the channel material layer 20 may be a single layer or more, for example, 1 to 10 layers, each layer having a thickness of three atomic layers. In one embodiment of the present invention, the channel material layer 20 has a uniform thickness. In another embodiment of the present invention, the channel material layer 20 has a non-uniform thickness, specifically, the channel material layer 20 has different thicknesses in the region where the p-type contact layers 31 and 32 are located and in the region other than the p-type contact layers 31 and 32, and optionally, the thickness of the channel material layer 20 in the region other than the p-type contact layers 31 and 32 is greater than the thickness of the channel material layer 20 in the region where the p-type contact layers 31 and 32 are located. Specifically, alternatively, the thickness of the channel material layer 20 at the maximum thickness is 1nm to 10nm, specifically, 2nm to 8nm, 3nm to 7nm, 4nm to 6nm, 5nm to 9 nm; when the thickness is equal, the thickness at the maximum thickness is the thickness at any position of the channel material layer 20.

In the embodiment of the present invention, the material of the insulating substrate 10 includes Si and SiO₂At least one of SOI, SiC and sapphire.

In the embodiment of the present invention, the materials of the source electrode 40 and the drain electrode 50 respectively include one or more of platinum, copper, nickel, palladium, gold, titanium, and chromium. When the source electrode 40 and the drain electrode 50 are made of the above-mentioned materials, the source electrode 40 and the drain electrode 50 may have a multi-layer structure, such as Ti/Au, Pt/Au, Cr/Au, etc. stacked on top of each other.

In the embodiment of the present invention, the material of the gate electrode 70 includes one of gold, palladium, and tungsten.

In the field effect transistor provided by the embodiment of the invention, the P-type contact layer is arranged between the source/drain metal and the channel material layer, and the material of the P-type contact layer is oxide MO of corresponding transition metal in the channel material layer_XThe oxide MO_XThe conductivity is high, the work function is high, hole injection is facilitated, good P-type contact between source and drain metal and a channel material layer can be achieved, and the quality of a field effect transistor is improved; in the embodiment of the invention, the material of the gate dielectric layer is further set to be the oxide MO of the corresponding transition metal in the channel material layer₃The preparation of the ultrathin gate dielectric layer with high dielectric constant is realized, and the quality of the field effect transistor is further improved.

As shown in fig. 3, a field effect transistor according to another embodiment of the present invention includes: an insulating substrate 10; a channel material layer 20 disposed on the insulating substrate 10, and a source electrode 40 and a drain electrode 50 disposed on the channel material layer 20 and respectively located at two opposite ends of the insulating substrate 10; a gate dielectric layer 160 disposed on the channel material layer 20 between the source electrode 40 and the drain electrode 50, and a gate electrode 70 disposed on the gate dielectric layer 160; the channel material layer 20 is made of a two-dimensional transition metal chalcogenide compound; the gate dielectric layer 160 is made of transition metal oxide, and the general formula of the transition metal oxide is MO₃Where M is a transition metal, and the transition metal species in the gate dielectric layer 160 is the same as the transition metal species in the channel material layer 20. In an embodiment of the present invention, the two-dimensional transition metal chalcogenide comprises MoS₂,WS₂,MoSe₂,WSe₂,MoTe₂,WTe₂One or more of (a). The MO is₃Wherein M is Mo or W. In the field effect transistor provided in this embodiment, the material of the gate dielectric layer is set to be the oxide MO of the corresponding transition metal in the channel material layer₃The oxide is an insulator with large dielectric constant and can be controlledTherefore, the preparation of the ultrathin gate dielectric layer with high dielectric constant is realized, and the quality of the field effect transistor is improved.

Correspondingly, as shown in fig. 4, an embodiment of the present invention further provides a method for manufacturing the field effect transistor shown in fig. 1 and fig. 2, including the following steps:

step 1: as shown in fig. 4 (a), an insulating substrate 10 is provided, wherein the material of the insulating substrate 10 includes Si, SiO₂At least one of SOI, SiC and sapphire, specifically SiO₂A composite structure formed by the layer and the P-type doped Si layer, and the like.

Step 2: as shown in fig. 4 (b), a TMD material layer 21 is disposed on the insulating substrate 10, where the thickness of the TMD material layer 21 is more than two layers, for example, 2 to 10 layers, and a single layer of TMD material is composed of three atomic layers, and the TMD material layer 21 may be directly grown on the insulating substrate 10 by a chemical vapor deposition method, or may be prepared on another substrate and then transferred to the surface of the insulating substrate 10. Source and drain regions at opposite ends of the insulating substrate 10 and a gate region between the source and drain regions are defined on the TMD material layer 21.

And step 3: as shown in fig. 4 (c) - (d), a photoresist 11 is used to protect the underlying TMD material above the gate region by using a photolithography technique, and then the entire device is placed in an oxygen-rich environment, and a laser is used to locally heat the unprotected region (i.e., the source and drain region) of the photoresist 11, so that the surface of the channel material layer of the source and drain region is incompletely oxidized to generate a transition metal oxide MO_XAnd obtaining the p-type contact layers 31 and 32, wherein M is transition metal and x is more than 0 and less than 3. In the oxidation process, the oxidation degree and the oxidized thickness of the TMD material in the source and drain region can be regulated and controlled by adjusting the laser heating power and heating time. After the oxidation is completed, a source-drain metal is covered on the p-type contact layers 31 and 32 by using an electron beam evaporation method to form a source electrode 40 and a drain electrode 50, wherein the source electrode and the drain electrode are usually made of a high work function metal, and specifically may include one or more of platinum, copper, nickel, palladium, gold, titanium, and chromium. Optionally, the heating power is 0.5W-3W, and the heating time is 6s-15 s. Specifically, heatingThe power may be 1W and the heating time 10 s. In other embodiments, the heating may be performed in ozone, or a common heating manner may be used instead of using laser, for example, the heating may be performed on a hot plate to generate a transition metal oxide by incomplete oxidation of the surface of the channel material layer in the source/drain region, so as to obtain a p-type contact layer, and optionally, the heating temperature of the common heating manner is 100 ℃ to 150 ℃.

And 4, step 4: as shown in fig. 4 (e) - (f), the photoresist 11 on the gate region is washed away, the

photoresist

12 and 13 is used to protect the source 40 and the drain 50, then the whole device is placed in an oxygen-rich environment, the laser is used to locally heat the unprotected region of the photoresist (i.e. the gate region), and the heating power and the heating time are selected to make the TMD material with a specific thickness in the gate region be completely oxidized into MO₃And a gate dielectric layer 160 is formed. After the oxidation of this step is completed, the unoxidized TMD material forms the channel material layer 20, and then the gate dielectric layer 160 is covered with metal by using the electron beam evaporation method to form the gate electrode 70, and then the

photoresists

12 and 13 above the source electrode 40 and the drain electrode 50 are washed away, thereby obtaining the field effect transistor as shown in fig. 4 (f). The gate 70 is made of one of gold, palladium and tungsten. Optionally, the heating power is 8W-15W, and the heating time is 25s-35 s. Specifically, the heating power may be 10W and the heating time may be 30 s. In other embodiments, the heating may be performed in ozone, or a common heating manner may be used instead of using laser, for example, the heating may be performed on a hot plate to generate a transition metal oxide by incomplete oxidation of the surface of the channel material layer in the source/drain region, so as to obtain a p-type contact layer, and optionally, the heating temperature of the common heating manner is 100 ℃ to 150 ℃.

In the embodiment of the present invention, when the gate dielectric layer 160 is made of the conventional material (e.g., at least one of aluminum oxide and hafnium oxide), in step 4, after the photoresist on the gate region is washed away, the source 40 and the drain 50 are protected by the photoresist, and the gate dielectric layer 260 and the gate 70 are prepared according to the conventional method, for example, the gate dielectric layer 160 is prepared by using an atomic layer deposition method, and the gate 70 is prepared by using an electron beam evaporation method.

As shown in fig. 5, an embodiment of the present invention further provides a method for manufacturing the field effect transistor shown in fig. 3, including the following steps:

step 1: as shown in fig. 5 (a), an insulating substrate 10 is provided, wherein the material of the insulating substrate 10 includes Si, SiO₂At least one of SOI, SiC and sapphire, specifically SiO₂A composite structure formed by the layer and the P-type doped Si layer, and the like.

Step 2: as shown in fig. 5 (b), a TMD material layer 21 is disposed on the insulating substrate 10, where the thickness of the TMD material layer 21 is more than two layers, for example, 2 to 10 layers, and a single layer of TMD material is composed of three atomic layers, and the TMD material layer 21 may be directly grown on the insulating substrate 10 by a chemical vapor deposition method, or may be prepared on another substrate and then transferred to the surface of the insulating substrate 10. Source and drain regions at opposite ends of the insulating substrate 10 and a gate region between the source and drain regions are defined on the TMD material layer 21.

And step 3: as shown in fig. 5 (c) - (d), the gate region is protected, metal is covered on the source and drain regions by electron beam evaporation to form a source 40 and a drain 50, the source 40 and the drain 50 are protected by photoresist, the device is placed in an oxygen-rich environment, the photoresist unprotected region (i.e. the gate region) is locally heated by laser, and the heating power and the heating time of the laser are selected during the heating process, so that the TMD material with a specific thickness in the gate region is completely oxidized into MO₃And obtaining the gate dielectric layer 160. After the oxidation of this step is completed, a metal is covered on the gate dielectric layer 160 by an electron beam evaporation method to form the gate electrode 70. The material of the source electrode and the drain electrode is usually a high work function metal, and may specifically include one or more of platinum, copper, nickel, palladium, gold, titanium, and chromium. The gate 70 is made of one of gold, palladium and tungsten.

And 4, step 4: as shown in fig. 5 (e), the photoresist above the source and drain regions is washed away, and finally the field effect transistor shown in fig. 5 (e) is obtained.

The preparation method provided by the embodiment of the invention has the advantages that the process is simple, the industrial production is easy to realize, two problems in the preparation process of the TMD field effect transistor are solved simultaneously through the simple heating oxidation process method, the quality of the field effect transistor is improved, and the production cost is greatly reduced.

It should be noted that, the embodiments of the present invention are mainly developed around TMD materials, but other semiconductor materials that can be oxidized and the conductivity of the oxidized product can be changed with the change of the oxygen defect density may also be manufactured to obtain corresponding field effect transistors according to the idea of the present invention.

The following examples are intended to illustrate the invention in more detail.

Example 1

A preparation method of a field effect transistor comprises the following steps:

step 1: providing an insulating substrate, wherein the insulating substrate is SiO₂A composite structure formed by the layer and the P-type doped Si layer;

step 2: SiO on insulating substrate by chemical vapor deposition₂Layer growth to obtain WSe with 2-layer structure₂Layers (each layer structure comprising 3 atomic layer thicknesses) in the WSe₂Defining source and drain regions at two opposite ends of the insulating substrate and a gate region between the source and drain regions;

and step 3: using photolithography techniques to protect the underlying WSe with photoresist over the gate region₂The material is prepared by placing the device in oxygen-rich environment, locally heating the unprotected source/drain region with laser, and adjusting laser heating power and heating time during heating process to make WSe in the source/drain region₂Incomplete oxidation of 1 layer thickness of the layer surface to form transition metal oxide WO_XAnd x is more than 0 and less than 3, so that two p-type contact layers are obtained. After the oxidation is finished, covering metal on the two p-type contact layers by adopting an electron beam evaporation method to form a source electrode and a drain electrode, wherein the metal of the source electrode and the metal of the drain electrode are both laminated Ti/Au, the thickness of the Ti/Au is 10nm/90nm, the lower layer is titanium (Ti), and the upper layer is gold (Au).

And 4, step 4: washing away over the gate regionPhotoresist is adopted, and an atomic layer deposition method is adopted to deposit and prepare a gate dielectric layer in a gate region, wherein the gate dielectric layer is made of aluminum oxide (Al)₂O₃) And then preparing a metal gold gate on the gate dielectric layer aluminum oxide layer to obtain the field effect transistor, wherein the structure of the field effect transistor is shown in figure 2.

Example 2

step 1: providing an insulating substrate, wherein the insulating substrate is sapphire;

step 2: adopting a chemical vapor deposition method to grow a WTE with a 4-layer structure on an insulating substrate₂Layer at the WTE₂Defining source and drain regions at two opposite ends of the insulating substrate and a gate region between the source and drain regions;

and step 3: protecting the underlying WTE with photoresist over the gate region using photolithography₂The material is prepared by placing the device in oxygen-rich environment, locally heating the unprotected source/drain region with laser, and adjusting laser heating power and heating time during heating process to make WTE in the source/drain region₂Incomplete oxidation of 2 layer thickness on the layer surface to form transition metal oxide WO_XAnd x is more than 0 and less than 3, so that two p-type contact layers are obtained. After the oxidation is finished, covering metal on the two p-type contact layers by adopting an electron beam evaporation method to form a source electrode and a drain electrode, wherein the metal of the source electrode and the metal of the drain electrode are both laminated Pt/Au, the thickness of the Pt/Au is 8nm/90nm, the lower layer is platinum (Pt), and the upper layer is gold (Au).

And 4, step 4: washing off photoresist above the grid region, protecting the source electrode and the drain electrode by using the photoresist, putting the whole device in an oxygen-enriched environment, locally heating the grid region unprotected by the photoresist by using laser, and selecting proper laser heating power and heating time in the heating process to ensure that the WTE with the specific thickness of the grid region₂The material is completely oxidized to WO₃And obtaining the gate dielectric layer. After the oxidation of the step is finished, the WTE which is not oxidized₂The material forms a channel material layer, and a gate dielectric layer is covered with metal gold by adopting an electron beam evaporation methodForming a grid electrode, and then washing away the photoresist above the source electrode and the drain electrode to obtain the field effect transistor, wherein the structure of the field effect transistor is shown in figure 1.

Example 3

step 2: SiO on insulating substrate by chemical vapor deposition₂Growth of a layer to obtain a WS having a 10-layer structure₂Layer in WS₂Defining source and drain regions at two opposite ends of the insulating substrate and a gate region between the source and drain regions;

and step 3: and covering metal on the source drain region by adopting an electron beam evaporation method to form a source electrode and a drain electrode, wherein the metal of the source electrode and the metal of the drain electrode are both Cr/Au which are arranged in a laminated mode, the thickness of the Cr/Au is 2nm/90nm, the lower layer is chromium (Cr), and the upper layer is gold (Au). Protecting the source electrode and the drain electrode by using photoresist, putting the whole device into an oxygen-enriched environment, locally heating the gate region unprotected by using laser, and selecting proper laser heating power and heating time in the heating process to ensure that the WS with the thickness of 4-layer structure of the gate region₂The material is completely oxidized to WO₃And obtaining the gate dielectric layer. After the oxidation of the step is finished, covering metal gold on the gate dielectric layer by adopting an electron beam evaporation method to form a gate;

and 4, step 4: and washing away the photoresist above the source and drain regions to obtain the field effect transistor, wherein the structure of the field effect transistor is shown in figure 3.

Example 4

step 2: MoS with 8-layer structure is obtained by growing on an insulating substrate by adopting a chemical vapor deposition method₂Layer of said MoS₂Defining source and drain regions at two opposite ends of the insulating substrate and a gate region between the source and drain regions;

and step 3: protecting the underlying MoS with photoresist over the gate region using photolithography techniques₂The material is prepared by placing the device in oxygen-rich environment, locally heating the unprotected source/drain region with laser, and adjusting laser heating power and heating time during heating process to make MoS in the source/drain region₂Incomplete oxidation occurs in the thickness of 2 layers on the surface of the layer to generate transition metal oxide MoO_XAnd x is more than 0 and less than 3, so that two p-type contact layers are obtained. After the oxidation is finished, covering metal on the two p-type contact layers by adopting an electron beam evaporation method to form a source electrode and a drain electrode, wherein the metal of the source electrode and the metal of the drain electrode are both laminated Ti/Au, the thickness of the Ti/Au is 10nm/90nm, the lower layer is titanium (Ti), and the upper layer is gold (Au).

And 4, step 4: washing off photoresist above the grid region, protecting the source electrode and the drain electrode by using the photoresist, putting the whole device in an oxygen-enriched environment, locally heating the grid region unprotected by the photoresist by using laser, and selecting proper laser heating power and heating time in the heating process to ensure that MoS with the thickness of 2 layers in the grid region₂The material is completely oxidized into MoO₃And obtaining the gate dielectric layer. After the oxidation of this step is completed, the unoxidized MoS₂The material forms a channel material layer, metal gold is covered on the gate dielectric layer by adopting an electron beam evaporation method to form a gate, and then photoresist above the source electrode and the drain electrode is washed off to obtain the field effect transistor.

Example 5

step 2: SiO on insulating substrate by chemical vapor deposition₂The layer is grown to obtain MoSe with a 5-layer structure₂Layer of said MoSe₂Defining source and drain regions at two opposite ends of the insulating substrate and a gate region between the source and drain regions;

and step 3: using photolithography to apply light over the gate regionUnder-etching protection MoSe₂Material, putting the device into oxygen-enriched environment, heating the source and drain regions unprotected by the photoresist by laser, and adjusting the laser heating power and time to make the MoSe in the source and drain regions₂Incomplete oxidation occurs in the thickness of 2 layers on the surface of the layer to generate transition metal oxide MoO_XAnd x is more than 0 and less than 3, so that two p-type contact layers are obtained. After the oxidation is finished, covering metal on the two p-type contact layers by adopting an electron beam evaporation method to form a source electrode and a drain electrode, wherein the metal of the source electrode and the metal of the drain electrode are both laminated Cr/Au, the thickness of the Cr/Au is 2nm/90nm, the lower layer is chromium (Cr), and the upper layer is gold (Au).

And 4, step 4: washing off photoresist above the grid region, protecting the source electrode and the drain electrode by using the photoresist, putting the whole device in an oxygen-enriched environment, locally heating the grid region unprotected by the photoresist by using laser, and selecting proper laser heating power and heating time in the heating process to ensure that MoSe with the thickness of 2 layers in the grid region₂The material is completely oxidized into MoO₃And obtaining the gate dielectric layer. After the oxidation of the step is completed, the MoSe which is not oxidized₂The material forms a channel material layer, metal gold is covered on the gate dielectric layer by adopting an electron beam evaporation method to form a gate, and then photoresist above the source electrode and the drain electrode is washed off to obtain the field effect transistor.

Example 6

step 2: MoTe with 6-layer structure is obtained by growing on an insulating substrate by adopting a chemical vapor deposition method₂Layer of said MoTe₂Defining source and drain regions at two opposite ends of the insulating substrate and a gate region between the source and drain regions;

and step 3: protecting the underlying MoTe with photoresist over the gate region using photolithography₂Material, putting the device into oxygen-enriched environment, heating the unprotected source/drain region with laser, addingIn the thermal process, the power and the heating time of laser heating are adjusted to ensure that the MoTe of the source and drain regions₂Incomplete oxidation occurs in the thickness of 2 layers on the surface of the layer to generate transition metal oxide MoO_XAnd x is more than 0 and less than 3, so that two p-type contact layers are obtained. After the oxidation is finished, covering metal on the two p-type contact layers by adopting an electron beam evaporation method to form a source electrode and a drain electrode, wherein the metal of the source electrode and the metal of the drain electrode are both laminated Pt/Au, the thickness of the Pt/Au is 8nm/90nm, the lower layer is platinum (Pt), and the upper layer is gold (Au).

And 4, step 4: washing off photoresist above the gate region, protecting the source and drain with the photoresist, placing the device in oxygen-rich environment, locally heating the gate region unprotected by the photoresist with laser, and selecting appropriate laser heating power and heating time during heating to obtain MoTe with thickness of 2 layers in the gate region₂The material is completely oxidized into MoO₃And obtaining the gate dielectric layer. After the oxidation of this step is completed, the unoxidized MoS₂The material forms a channel material layer, metal gold is covered on the gate dielectric layer by adopting an electron beam evaporation method to form a gate, and then photoresist above the source electrode and the drain electrode is washed off to obtain the field effect transistor.

Claims

1. a field effect transistor, is characterized in that, comprises:

insulating substrate;

a channel material layer, disposed on the insulating substrate, and the material of the channel material layer is a two-dimensional transition metal chalcogenide;

Two p-type contact layers are arranged on the channel material layer at intervals, the material of the p-type contact layer is a transition metal oxide, and the general formula of the transition metal oxide is MO _X , wherein M is a transition metal , 0<x<3, and the transition metal species in the p-type contact layer is the same as the transition metal species in the channel material layer, and the p-type contact layer is made of the channel material layer through in-situ Obtained by incomplete oxidation;

a gate dielectric layer, disposed on the channel material layer between the two p-type contact layers;

a source electrode and a drain electrode, respectively disposed on the two p-type contact layers;

The gate is disposed on the gate dielectric layer.

2. The field effect transistor of claim 1, wherein the two-dimensional transition metal chalcogenide comprises one or more of MoS ₂ , WS ₂ , MoSe ₂ , WSe ₂ , MoTe ₂ , and WTe ₂ kind.

3 . The field effect transistor according to claim 1 , wherein, in the MO _X , the M is Mo or W. 4 .

4 . The field effect transistor of claim 1 , wherein the p-type contact layer has a thickness of 1 nm-6 nm. 5 .

5 . The field effect transistor of claim 1 , wherein the p-type contact layer and the channel material layer are bonded by chemical bonds. 6 .

6 . The field effect transistor of claim 1 , wherein the material of the gate dielectric layer is transition metal oxide, the general formula of the transition metal oxide is MO ₃ , wherein M is a transition metal, and The M is the same as the transition metal species in the channel material layer.

7 . The field effect transistor according to claim 6 , wherein the material of the gate dielectric layer is MoO ₃ or WO ₃ .

8 . The field effect transistor of claim 6 , wherein the gate dielectric layer is obtained by in-situ complete oxidation of the channel material layer material, and the gap between the gate dielectric layer and the channel material layer is obtained. bonded by chemical bonds.

9 . The field effect transistor of claim 6 , wherein the two p-type contact layers and the gate dielectric layer are connected together, or the two p-type contact layers are respectively connected to the gate dielectric layer. 10 . Layer interval settings.

10 . The field effect transistor of claim 1 , wherein the gate dielectric layer is made of at least one of aluminum oxide and hafnium oxide. 11 .

11 . The field effect transistor of claim 1 , wherein the gate dielectric layer has a thickness of 1 nm to 6 nm, and the gate dielectric layer has a thickness equal to, greater than or less than a thickness of the p-type contact layer. 12 .

12 . The field effect transistor of claim 1 , wherein the thickness of the channel material layer at the maximum thickness is 1 nm-10 nm. 13 .

13 . The field effect transistor of claim 1 , wherein the material of the insulating substrate comprises at least one of Si, SiO ₂ , SOI, SiC, and sapphire. 14 .

14 . The field effect transistor of claim 1 , wherein the material of the source electrode and the drain electrode respectively comprises one or more of platinum, copper, nickel, palladium, gold, titanium, and chromium. 15 . .

15. The field effect transistor of claim 1, wherein the material of the gate comprises one of gold, palladium, and tungsten.

16. A field effect transistor, comprising:

insulating substrate;

a source electrode and a drain electrode, which are arranged on the channel material layer at intervals;

A gate dielectric layer, disposed on the channel material layer between the source electrode and the drain electrode, the material of the gate dielectric layer is transition metal oxide, and the general formula of the transition metal oxide is MO ₃ , wherein M is a transition metal, and the M is of the same type as the transition metal in the channel material layer, and the gate dielectric layer is obtained by in-situ complete oxidation of the channel material layer material;

The gate is disposed on the gate dielectric layer.

17. The field effect transistor of claim 16, wherein the two-dimensional transition metal chalcogenide comprises one or more of MoS ₂ , WS ₂ , MoSe ₂ , WSe ₂ , MoTe ₂ , and WTe ₂ kind.

18 . The field effect transistor according to claim 16 or 17 , wherein, in the MO ₃ , the M is Mo or W. 19 .

19. The field effect transistor of claim 16, wherein the gate dielectric layer has a thickness of 1 nm-6 nm.

20 . The field effect transistor of claim 16 , wherein the gate dielectric layer and the channel material layer are bonded by chemical bonds. 21 .

21. The field effect transistor of claim 16, wherein a p-type contact layer is disposed between the source electrode and the channel material layer, and a p-type contact layer is disposed between the drain electrode and the channel material layer A p-type contact layer is provided, and the materials of the two p-type contact layers are transition metal oxides. The general formula of the transition metal oxides is MO _X , wherein M is a transition metal, 0<x<3, and The M is the same as the transition metal species in the channel material layer.

22. a preparation method of field effect transistor, is characterized in that, comprises the following steps:

An insulating substrate is provided, and a two-dimensional transition metal chalcogenide material layer is provided on the insulating substrate, and the two-dimensional transition metal chalcogenide material layer includes a source-drain region on the insulating substrate and a source-drain region on the insulating substrate the gate region between the drain regions;

The gate region is protected by photoresist, and the source and drain regions that are not protected by the photoresist are heated in an oxygen-rich or ozone environment, so that the two-dimensional transition metal chalcogenide material in the source and drain regions is formed. Incomplete oxidation occurs on the surface of the layer to generate a transition metal oxide to obtain a p-type contact layer, and the unoxidized two-dimensional transition metal chalcogenide material layer constitutes a channel material layer, and the general formula of the transition metal oxide is MO _X , wherein M is a transition metal, 0<x<3, and the M is the same as the transition metal in the channel material layer;

A source electrode and a drain electrode are formed in the source and drain regions, and after the photoresist is washed off, a gate dielectric layer and a gate electrode are sequentially formed in the gate region to obtain a field effect transistor.

23. The preparation method according to claim 22, wherein the specific operation of forming the gate dielectric layer is: protecting the source electrode and the drain electrode with a photoresist, and protecting the unaffected electrodes in an oxygen-rich or ozone environment The gate region protected by the photoresist is heated, so that the surface of the two-dimensional transition metal chalcogenide material layer in the gate region is completely oxidized to generate a transition metal oxide to obtain the gate dielectric layer. The general formula of the oxide is MO ₃ , wherein M is a transition metal, and M is the same as the transition metal in the channel material layer.

24. A preparation method of a field effect transistor, characterized in that, comprising the following steps:

An insulating substrate is provided, a two-dimensional transition metal chalcogenide material layer is provided on the insulating substrate, and the two-dimensional transition metal chalcogenide material layer includes a source-drain region on the insulating substrate and a source-drain region on the insulating substrate the gate region between the drain regions;

The source and drain regions are protected by photoresist, and the gate region that is not protected by the photoresist is heated in an oxygen-rich or ozone environment, so that the two-dimensional transition metal chalcogenide material in the gate region is formed. The surface of the layer is completely oxidized to generate a transition metal oxide to obtain a gate dielectric layer, and the two-dimensional transition metal chalcogenide material layer that is not oxidized constitutes a channel material layer. The general formula of the transition metal oxide is MO ₃ , wherein M is a transition metal, and the M is the same as the transition metal in the channel material layer;

Then, a gate electrode is formed on the gate dielectric layer, and a source electrode and a drain electrode are formed in the source and drain regions after the photoresist is washed away to obtain a field effect transistor.

25. The preparation method according to claim 24, wherein before preparing the source electrode and the drain electrode, two p-type contact layers are first prepared in the source-drain region, and the specific The preparation process is: using photoresist to protect the gate, and heating the source and drain regions not protected by the photoresist in an oxygen-rich or ozone environment, so that the two-dimensional transition metal sulfur in the source and drain regions is Incomplete oxidation occurs on the surface of the group compound material layer to generate transition metal oxides to obtain two p-type contact layers. The general formula of the transition metal oxides is MO _X , wherein M is a transition metal, 0<x<3, so The M is the same as the transition metal species in the channel material layer.

26. A transistor array device, characterized by comprising an array structure formed by the field effect transistor of any one of claims 1-15 or 16-21.