CN110287072A - Method, apparatus, computer equipment and the storage medium of accidental validation response - Google Patents
Method, apparatus, computer equipment and the storage medium of accidental validation response Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 48
- 238000010200 validation analysis Methods 0.000 title claims abstract description 34
- 238000012360 testing method Methods 0.000 claims abstract description 92
- 238000013461 design Methods 0.000 claims abstract description 88
- 238000004590 computer program Methods 0.000 claims description 21
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test buses, lines or interfaces, e.g. stuck-at or open line faults
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
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Abstract
The present invention relates to method, apparatus, computer equipment and the storage medium of accidental validation response, this method includes selecting a time point at random, to obtain time point to be verified；Since time point to be verified, the request signal that design under test is sent is obtained；The busy environment of response signal is constructed to carry out the verifying of design under test；Judge that design under test is verified whether to terminate；If it is not, then selecting down time point at the beginning at random, to obtain time point to be verified, and the request signal described since time point to be verified, acquisition design under test is sent is returned to.The present invention not only can satisfy the verifying done to response signal, and it is random due to carrying out on a timeline, also it is able to verify that the response signal under a variety of request scenes is busy, and specific request scene inside design under test is not needed to understand, it realizes simple to verifying personnel requirement, workload is few, and versatile and implementation is simple.
Description
Technical field
The present invention relates to chip verification methods, more specifically refer to that the method, apparatus of accidental validation response, computer are set
Standby and storage medium.
Background technique
In the module level verification of chip, it is often necessary to verify the field that module to be tested is interacted with surrounding other module by signal
Scape.Request signal, the scene of peripheral module feedback response signal are issued comprising module to be tested in these interaction scenarios.Because peripheral
The response time of module is uncertain, uncertain this requires needing to simulate this response time when verifying module to be tested.
As shown in Figures 1 and 2, typical test case executes on time shaft, there is many request and response.Assuming that all
Request from design under test, from other peripheral modules, each request and response are considered as one kind for all responses
Operation scenario first combs testing for all interactions then just having N number of test scene on the execution time shaft of this test case
Scene is demonstrate,proved, then starts to verify scene one, confirms that work in scene one, reconstructs response signal and does by extracting design code,
After completing first scene, then start to verify second scenario, to the last a scene completes verifying, and entire verifying terminates.
If there is N number of scene, then N number of test cases is needed.Traditional verification method can use direct use-case verification mode, by drawing
Find the scene occurrence condition to be verified with inside modules signal relation to be tested, then by judging that these conditions meet when, produce
Raw periphery feedback signal is busy, makes the scene for needing to know clearly all access peripheral modules in this way, and every kind of field
Scape will be constructed by reference internal signal relationship, if access scenario is more, workload is just very big for verifying personnel；
In addition, traditional verification method usually only can once construct a kind of busy scene of response signal, can not very well simulation it is true
Situation is also not big enough to the pressure of module to be tested.
In addition, module divides several scenes to the operation of bus, for example carries out write operation to the certain addresses of bus, to total
The certain addresses of line carry out read operation etc., if all regarding each operation as a kind of scene, that just has many operation scenarios, verifying
If when to verify the busy responses of bus of these scenes, it is necessary to each operation scenario is all understood, then by pair
Every kind of operation scenario is determined than chip interior signal relation, it is busy so as to generate corresponding bus signals according to special scenes.
It can thus be seen that verifying personnel need to every kind of operation scenario of bus operation will it is clear that and comb, secondly also
The scene for needing to verify is found by reference to design code, and the busy feelings of corresponding response signal are then generated according to request signal
Condition, in this way, the requirement to verifying personnel is very high, and workload is also very big, and is not easy to extend to verifying scene, has also been easy
It omits.
Therefore, it is necessary to design a kind of new method, realize that personnel requirement is simple, and workload is few, versatile to verifying
And implementation is simple.
Summary of the invention
It is an object of the invention to overcome the deficiencies of existing technologies, method, apparatus, the computer of accidental validation response are provided
Equipment and storage medium.
To achieve the above object, the invention adopts the following technical scheme: the method for accidental validation response, comprising:
A time point is selected at random, to obtain time point to be verified；
Since time point to be verified, the request signal that design under test is sent is obtained；
The busy environment of response signal is constructed to carry out the verifying of design under test；
Judge that design under test is verified whether to terminate；
If it is not, then selecting down time point at the beginning at random, to obtain time point to be verified, and return described to be verified
Time point obtains the request signal that design under test is sent.
Its further technical solution are as follows: it is described to select a time point at random, to obtain time point to be verified, comprising:
Centered on time shaft, some time point is selected by using random device, to obtain time point to be verified.
Its further technical solution are as follows: the request signal includes read data request and write data requests.
Its further technical solution are as follows: described to construct the busy environment of response signal to carry out the verifying of design under test, packet
It includes:
Response signal is constructed according to request signal；
Response signal is sent to design under test after one random time, so that design under test is tested
Card.
Its further technical solution are as follows: the judgement verifies whether to terminate to design under test, comprising:
Judge whether the time point to be verified meets setting condition；
If so, the verifying to design under test terminates；
If it is not, then the verifying of design under test is not finished.
The present invention also provides the devices of accidental validation response, comprising:
First module of selection, for selecting a time point at random, to obtain time point to be verified；
Signal acquiring unit, for since time point to be verified, obtaining the request signal that design under test is sent；
Construction unit, for constructing the busy environment of response signal to carry out the verifying of design under test；
Judging unit verifies whether to terminate for judging to design under test；
Module of selection again, for if it is not, then select down time point at the beginning at random, to obtain time point to be verified, and
Return to the request signal described since time point to be verified, acquisition design under test is sent.
Its further technical solution are as follows: the construction unit includes:
Signal constructs subelement, for constructing response signal according to request signal；
Signal transmission sub-unit, for response signal to be sent to design under test after one random time, with
It is verified for design under test.
The present invention also provides a kind of computer equipment, the computer equipment includes memory and processor, described to deposit
Computer program is stored on reservoir, the processor realizes above-mentioned method when executing the computer program.
The present invention also provides a kind of storage medium, the storage medium is stored with computer program, the computer journey
Sequence can realize above-mentioned method when being executed by processor.
Compared with the prior art, the invention has the advantages that: the present invention by centered on time shaft, by using with
Machine method determines that at some random time point, no longer centered on scene, detection request signal is effective, is requesting
It is busy that response signal is then generated when signal is effective, after waiting this time request response, then random next time point, on a timeline
The busy construction of response signal is repeatedly carried out, the scene verifying done to response signal is more randomly completed, not only can satisfy pair
The busy verifying of response signal, and, the response signal that is also able to verify that a variety of request scenes under random due to carrying out on a timeline
It is busy, and do not need to understand specific request scene inside design under test, realize, workload simple to verifying personnel requirement
Few, versatile and implementation is simple.
The invention will be further described in the following with reference to the drawings and specific embodiments.
Detailed description of the invention
Technical solution in order to illustrate the embodiments of the present invention more clearly, below will be to needed in embodiment description
Attached drawing is briefly described, it should be apparent that, drawings in the following description are some embodiments of the invention, general for this field
For logical technical staff, without creative efforts, it is also possible to obtain other drawings based on these drawings.
Fig. 1 is the execution flow diagram of the typical test case of the prior art；
Fig. 2 is the flow diagram of the conventional authentication of the prior art；
Fig. 3 is the application scenarios schematic diagram of the method for accidental validation provided in an embodiment of the present invention response；
Fig. 4 is the flow diagram of the method for accidental validation provided in an embodiment of the present invention response；
Fig. 5 is the sub-process schematic diagram of the method for accidental validation provided in an embodiment of the present invention response；
Fig. 6 is the sub-process schematic diagram of the method for accidental validation provided in an embodiment of the present invention response；
Fig. 7 is the schematic block diagram of the device of accidental validation provided in an embodiment of the present invention response；
Fig. 8 is the schematic block diagram of the construction unit of the device of accidental validation provided in an embodiment of the present invention response；
Fig. 9 is the schematic block diagram of computer equipment provided in an embodiment of the present invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are some of the embodiments of the present invention, instead of all the embodiments.Based on this hair
Embodiment in bright, every other implementation obtained by those of ordinary skill in the art without making creative efforts
Example, shall fall within the protection scope of the present invention.
It should be appreciated that ought use in this specification and in the appended claims, term " includes " and "comprising" instruction
Described feature, entirety, step, operation, the presence of element and/or component, but one or more of the other feature, whole is not precluded
Body, step, operation, the presence or addition of element, component and/or its set.
It is also understood that mesh of the term used in this description of the invention merely for the sake of description specific embodiment
And be not intended to limit the present invention.As description of the invention and it is used in the attached claims, unless on
Other situations are hereafter clearly indicated, otherwise " one " of singular, "one" and "the" are intended to include plural form.
It will be further appreciated that the term "and/or" used in description of the invention and the appended claims is
Refer to any combination and all possible combinations of one or more of associated item listed, and including these combinations.
Fig. 3 and Fig. 4 are please referred to, Fig. 3 is that the application scenarios of the method for accidental validation provided in an embodiment of the present invention response show
It is intended to.Fig. 3 is the schematic flow chart of the method for accidental validation provided in an embodiment of the present invention response.Accidental validation response
Monitoring method is applied in server.The server and design under test, that is, chip to be verified carry out data interaction, with realization pair
The verifying of design under test.
Fig. 4 is the flow diagram of the method for accidental validation response provided in an embodiment of the present invention.As shown in figure 4, the party
Method includes the following steps S110 to S150.
S110, a time point is selected at random, to obtain time point to be verified.
In the present embodiment, time point to be verified refers to the time point selected at random, centered on time shaft, by using
Random device determines that it is effective to detect request signal at some random time point.
Specifically, centered on time shaft, some time point is selected by using random device, when obtaining to be verified
Between point.
S120, since time point to be verified, obtain design under test send request signal.
In the present embodiment, above-mentioned request signal includes read data request and write data requests.
S130, the busy environment of response signal is constructed to carry out the verifying of design under test.
In one embodiment, referring to Fig. 5, above-mentioned step S130 may include step S131~S132.
S131, response signal is constructed according to request signal；
S132, response signal is sent to design under test after one random time, for design under test into
Row verifying.
Other modules of the periphery such as design under test and server have signal interaction, and design under test issues request signal, clothes
Other peripheral modules such as business device just provide response signal after a period of time, construct the busy scene of response signal with this.
The busy environment of construction response signal, which refers to, allows response signal to be just given to mould to be verified after one random time
Block, can verify design under test with this work normally when response signal is hurried.
S140, judge that design under test is verified whether to terminate.
In one embodiment, referring to Fig. 6, above-mentioned step S140 may include step S141~S143.
S141, judge whether the time point to be verified meets setting condition；
S142, if so, the verifying to design under test terminates；
S143, if it is not, then the verifying of design under test is not finished.
One time point to be verified is the equal of a scene, and the time point on time shaft can rely on the test case,
The time point selected at random is replaced, the verifying to multiple scenes can be completed, specifically, when the quantity at time point to be verified meets
The threshold value of setting, then it is believed that currently having covered all scenes to design under test.
S150, if it is not, then selecting down time point at the beginning at random, to obtain time point to be verified, and return to the step
Rapid S120；
If so, into end step.
Centered on time shaft, by since some time point, waiting design under test to other peripheral modules at random
Request signal is sent, then the response signal of environment construction peripheral module is busy, to verify design under test for this response
Can the busy scene of signal work normally；Then random time point again, and start after this time point, then wait to be tested
It demonstrate,proves module and request signal is sent to peripheral module, equally, the response signal of environment construction peripheral module is busy, go down repeatedly,
Until verification platform terminates.By taking certain chip checking as an example, need to verify design under test by bus access peripheral module, in this way
It just will appear read and write access of the design under test to bus
By centered on time shaft, rather than centered on verifying scene, by starting at some random time point
Then the request signal for waiting design under test generates the busy mode of corresponding response signal, as long as random time point every time
It is not fixed point, can theoretically covers all scenes on time shaft, without is combed to various verifying scenes.
Because not needing to pay close attention to specific scene, without necessarily referring to design code, it is only necessary to start at random time point yet
Simple to verifying personnel requirement to the request signal of design under test, workload is also seldom.If there is N number of scene, only need
There is 1 test case, this test case then executed into many times, can theoretically complete the covering to N number of scene,
Understanding requirement of the verifying personnel to verifying scene is reduced, and general, implementation is simple.It, can be any using the invention
The place of signal interaction is simply completed the busy scene verifying of response signal.
Above-mentioned method can be used for verifying any field for having request signal with peripheral module and peripheral module is needed to respond
Scape.
The method of above-mentioned accidental validation response, by centered on time shaft, by using random device, determine with
At some time point of machine, no longer centered on scene, detection request signal is effective, then generates when request signal is effective
Response signal is busy, after waiting this time request response, then random next time point, response signal is repeatedly carried out on a timeline
Busy construction more randomly completes the scene verifying done to response signal, not only can satisfy the verifying done to response signal,
And it is random due to carrying out on a timeline, also it is able to verify that the response signal under a variety of request scenes is busy, and do not need to manage
The specific request scene in design under test inside is solved, realization is simple to verifying personnel requirement, and workload is few, versatile and realization
Mode is simple.
Fig. 7 is a kind of schematic block diagram of the device 300 of accidental validation response provided in an embodiment of the present invention.Such as Fig. 7 institute
Show, corresponding to the method for above accidental validation response, the present invention also provides a kind of devices 300 of accidental validation response.This is random
The device 300 of auth response includes the unit for executing the method for above-mentioned accidental validation response, which can be configured in
In server.
Specifically, referring to Fig. 7, the device 300 of accidental validation response includes:
First module of selection 301, for selecting a time point at random, to obtain time point to be verified；
Signal acquiring unit 302, for since time point to be verified, obtaining the request signal that design under test is sent；
Construction unit 303, for constructing the busy environment of response signal to carry out the verifying of design under test；
Judging unit 304 verifies whether to terminate for judging to design under test；
Module of selection 305 again, for if it is not, then select down time point at the beginning at random, to obtain time point to be verified,
And return to the request signal described since time point to be verified, acquisition design under test is sent.
In one embodiment, as shown in figure 8, the construction unit 303 includes:
Signal constructs subelement 3031, for constructing response signal according to request signal；
Signal transmission sub-unit 3032, for response signal to be sent to mould to be verified after one random time
Block, so that design under test is verified.
It should be noted that it is apparent to those skilled in the art that, the dress of above-mentioned accidental validation response
The specific implementation process of 300 and each unit is set, it can be with reference to the corresponding description in preceding method embodiment, for convenience of description
With it is succinct, details are not described herein.
The device 300 of above-mentioned accidental validation response can be implemented as a kind of form of computer program, the computer program
It can be run in computer equipment as shown in Figure 9.
Referring to Fig. 9, Fig. 9 is a kind of schematic block diagram of computer equipment provided by the embodiments of the present application.The computer
Equipment 500 can be server.
Refering to Fig. 9, which includes processor 502, memory and the net connected by system bus 501
Network interface 505, wherein memory may include non-volatile memory medium 503 and built-in storage 504.
The non-volatile memory medium 503 can storage program area 5031 and computer program 5032.The computer program
5032 include program instruction, which is performed, and processor 502 may make to execute a kind of side of accidental validation response
Method.
The processor 502 is for providing calculating and control ability, to support the operation of entire computer equipment 500.
The built-in storage 504 provides environment for the operation of the computer program 5032 in non-volatile memory medium 503, should
When computer program 5032 is executed by processor 502, processor 502 may make to execute a kind of method that accidental validation responds.
The network interface 505 is used to carry out network communication with other equipment.It will be understood by those skilled in the art that in Fig. 9
The structure shown, only the block diagram of part-structure relevant to application scheme, does not constitute and is applied to application scheme
The restriction of computer equipment 500 thereon, specific computer equipment 500 may include more more or fewer than as shown in the figure
Component perhaps combines certain components or with different component layouts.
Wherein, the processor 502 is for running computer program 5032 stored in memory, to realize following step
It is rapid:
A time point is selected at random, to obtain time point to be verified；
Since time point to be verified, the request signal that design under test is sent is obtained；
The busy environment of response signal is constructed to carry out the verifying of design under test；
Judge that design under test is verified whether to terminate；
If it is not, then selecting down time point at the beginning at random, to obtain time point to be verified, and return described to be verified
Time point obtains the request signal that design under test is sent.
Wherein, the request signal includes read data request and write data requests.
In one embodiment, processor 502 realize it is described select a time point at random, walked with obtaining time point to be verified
When rapid, it is implemented as follows step:
Centered on time shaft, some time point is selected by using random device, to obtain time point to be verified.
In one embodiment, processor 502 is realizing the busy environment of the building response signal to carry out design under test
Verification step when, be implemented as follows step:
Response signal is constructed according to request signal；
Response signal is sent to design under test after one random time, so that design under test is tested
Card.
In one embodiment, processor 502 realize the judgement to design under test when verifying whether end step,
It is implemented as follows step:
Judge whether the time point to be verified meets setting condition；
If so, the verifying to design under test terminates；
If it is not, then the verifying of design under test is not finished.
It should be appreciated that in the embodiment of the present application, processor 502 can be central processing unit (Central
Processing Unit, CPU), which can also be other general processors, digital signal processor (Digital
Signal Processor, DSP), specific integrated circuit (Application Specific Integrated Circuit,
ASIC), ready-made programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic
Device, discrete gate or transistor logic, discrete hardware components etc..Wherein, general processor can be microprocessor or
Person's processor is also possible to any conventional processor etc..
Those of ordinary skill in the art will appreciate that be realize above-described embodiment method in all or part of the process,
It is that relevant hardware can be instructed to complete by computer program.The computer program includes program instruction, computer journey
Sequence can be stored in a storage medium, which is computer readable storage medium.The program instruction is by the department of computer science
At least one processor in system executes, to realize the process step of the embodiment of the above method.
Therefore, the present invention also provides a kind of storage mediums.The storage medium can be computer readable storage medium.This is deposited
Storage media is stored with computer program, and processor is made to execute following steps when wherein the computer program is executed by processor:
A time point is selected at random, to obtain time point to be verified；
Since time point to be verified, the request signal that design under test is sent is obtained；
The busy environment of response signal is constructed to carry out the verifying of design under test；
Judge that design under test is verified whether to terminate；
If it is not, then selecting down time point at the beginning at random, to obtain time point to be verified, and return described to be verified
Time point obtains the request signal that design under test is sent.
Wherein, the request signal includes read data request and write data requests.
In one embodiment, the processor is realized and described selects the time at random executing the computer program
Point is implemented as follows step when obtaining time point step to be verified:
Centered on time shaft, some time point is selected by using random device, to obtain time point to be verified.
In one embodiment, the processor realizes what the building response signal was done executing the computer program
When verification step of the environment to carry out design under test, it is implemented as follows step: response signal is constructed according to request signal；
Response signal is sent to design under test after one random time, so that design under test is tested
Card.
In one embodiment, the processor realizes the judgement to design under test executing the computer program
When verifying whether end step, be implemented as follows step:
Judge whether the time point to be verified meets setting condition；
If so, the verifying to design under test terminates；
If it is not, then the verifying of design under test is not finished.
The storage medium can be USB flash disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), magnetic disk
Or the various computer readable storage mediums that can store program code such as CD.
Those of ordinary skill in the art may be aware that list described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and algorithm steps, can be realized with electronic hardware, computer software, or a combination of the two, in order to clearly demonstrate hardware
With the interchangeability of software, each exemplary composition and step are generally described according to function in the above description.This
A little functions are implemented in hardware or software actually, the specific application and design constraint depending on technical solution.Specially
Industry technical staff can use different methods to achieve the described function each specific application, but this realization is not
It is considered as beyond the scope of this invention.
In several embodiments provided by the present invention, it should be understood that disclosed device and method can pass through it
Its mode is realized.For example, the apparatus embodiments described above are merely exemplary.For example, the division of each unit, only
Only a kind of logical function partition, there may be another division manner in actual implementation.Such as multiple units or components can be tied
Another system is closed or is desirably integrated into, or some features can be ignored or not executed.
The steps in the embodiment of the present invention can be sequentially adjusted, merged and deleted according to actual needs.This hair
Unit in bright embodiment device can be combined, divided and deleted according to actual needs.In addition, in each implementation of the present invention
Each functional unit in example can integrate in one processing unit, is also possible to each unit and physically exists alone, can also be with
It is that two or more units are integrated in one unit.
If the integrated unit is realized in the form of SFU software functional unit and when sold or used as an independent product,
It can store in one storage medium.Based on this understanding, technical solution of the present invention is substantially in other words to existing skill
The all or part of part or the technical solution that art contributes can be embodied in the form of software products, the meter
Calculation machine software product is stored in a storage medium, including some instructions are used so that a computer equipment (can be a
People's computer, terminal or network equipment etc.) it performs all or part of the steps of the method described in the various embodiments of the present invention.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can readily occur in various equivalent modifications or replace
It changes, these modifications or substitutions should be covered by the protection scope of the present invention.Therefore, protection scope of the present invention should be with right
It is required that protection scope subject to.
Claims (9)
1. the method for accidental validation response characterized by comprising
A time point is selected at random, to obtain time point to be verified；
Since time point to be verified, the request signal that design under test is sent is obtained；
The busy environment of response signal is constructed to carry out the verifying of design under test；
Judge that design under test is verified whether to terminate；
If it is not, then selecting down time point at the beginning at random, to obtain time point to be verified, and return described from the time to be verified
Point starts, and obtains the request signal that design under test is sent.
2. the method for accidental validation response according to claim 1, which is characterized in that it is described to select a time point at random,
To obtain time point to be verified, comprising:
Centered on time shaft, some time point is selected by using random device, to obtain time point to be verified.
3. the method for accidental validation response according to claim 1, which is characterized in that the request signal includes reading data
Request and write data requests.
4. the method for accidental validation response according to claim 1, which is characterized in that the busy ring of the building response signal
Border is to carry out the verifying of design under test, comprising:
Response signal is constructed according to request signal；
Response signal is sent to design under test after one random time, so that design under test is verified.
5. the method for accidental validation response according to claim 1, which is characterized in that the judgement is to design under test
It verifies whether to terminate, comprising:
Judge whether the time point to be verified meets setting condition；
If so, the verifying to design under test terminates；
If it is not, then the verifying of design under test is not finished.
6. the device of accidental validation response characterized by comprising
First module of selection, for selecting a time point at random, to obtain time point to be verified；
Signal acquiring unit, for since time point to be verified, obtaining the request signal that design under test is sent；
Construction unit, for constructing the busy environment of response signal to carry out the verifying of design under test；
Judging unit verifies whether to terminate for judging to design under test；
Module of selection again, for obtain time point to be verified, and returning if it is not, then select down time point at the beginning at random
The request signal that since time point to be verified, acquisition design under test is sent.
7. the method for accidental validation according to claim 6 response, which is characterized in that the construction unit includes:
Signal constructs subelement, for constructing response signal according to request signal；
Signal transmission sub-unit, for response signal to be sent to design under test after one random time, for
Authentication module is verified.
8. a kind of computer equipment, which is characterized in that the computer equipment includes memory and processor, on the memory
It is stored with computer program, the processor is realized as described in any one of claims 1 to 5 when executing the computer program
Method.
9. a kind of storage medium, which is characterized in that the storage medium is stored with computer program, and the computer program is located
Reason device can realize the method as described in any one of claims 1 to 5 when executing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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